Motorola MCM6227AWJ45, MCM6227AWJ45R2, MCM6227AWJ20R2, MCM6227AWJ25, MCM6227AWJ25R2 Datasheet
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MCM6227A
1
MOTOROLA FAST SRAM
1M x 1 Bit Static Random
Access Memory
The MCM6227A is a 1,048,576 bit static random–access memory organized
as 1,048,576 words of 1 bit, fabricated using high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes while CMOS circuitry reduces power consumption and provides for
greater reliability.
The MCM6227A is equipped with a chip enable (E
) pin. In less than a cycle time
after E
goes high, the part enters a low–power standby mode, remaining in that
state until E
goes low again.
The MCM6227A is available in 400 mil, 28–lead surface–mount SOJ packages.
• Single 5 V ± 10% Power Supply
• Fast Access Times: 20, 25, 35, and 45 ns
• Equal Address and Chip Enable Access Times
• Input and Output are TTL Compatible
• Three–State Output
• Low Power Operation: 160/140/130/120 mA Maximum, Active AC
BLOCK DIAGRAM
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
A2
A3
A4
A5
A6
A7
A8
A9
MEMORY MATRIX
1024 ROWS x
1024 COLUMNS
ROW
DECODER
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
E
W
Q
D
SS
V
V
CC
A0
A1
Order this document
by MCM6227A/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6227A
WJ PACKAGE
400 MIL SOJ
CASE 810–03
19
18
17
16
15
28
27
26
25
24
23
22
21
20
A0
A1
A2
A3
A4
A5
NC
A6
A7
A8
A9
Q
W
V
SS
V
CC
A19
A18
A17
A16
A14
NC
A13
A12
A11
A10
D
A15
10
11
12
13
14
1
2
3
4
5
6
7
8
9
A0 – A19 Address Inputs. . . . . . . . . . . . .
W
Write Enable. . . . . . . . . . . . . . . . . . . . .
E
Chip Enable. . . . . . . . . . . . . . . . . . . . . .
D Data Input. . . . . . . . . . . . . . . . . . . . . . . .
Q Data Output. . . . . . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . . .
V
CC
+ 5 V Power Supply. . . . . . . . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . . .
PIN NAMES
E
REV 4
5/95
Motorola, Inc. 1994
MCM6227A
2
MOTOROLA FAST SRAM
MCM6227A TRUTH TABLE
E W Mode I/O Pin Cycle Current
H X Not Selected High–Z — I
SB1
, I
SB2
L H Read D
out
Read I
CCA
L L Write High–Z Write I
CCA
H = High, L = Low, X = Don’t Care
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Symbol Value Unit
Power Supply Voltage Relative to V
SS
V
CC
– 0.5 to 7.0 V
Voltage Relative to VSS for Any Pin
Except V
CC
Vin, V
out
– 0.5 to VCC + 0.5 V
Output Current I
out
± 20
mA
Power Dissipation P
D
1.1 W
Temperature Under Bias T
bias
– 10 to + 85 °C
Operating Temperature T
A
0 to + 70 °C
Storage Temperature T
stg
– 55 to + 150 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
Supply Voltage (Operating Voltage Range) V
CC
4.5 5.5 V
Input High Voltage V
IH
2.2 VCC + 0.3** V
Input Low Voltage V
IL
– 0.5* 0.8 V
*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns).
**VIH (max) = VCC = 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns).
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Symbol Min Typ* Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
lkg(I)
— — ± 1 µA
Output Leakage Current (E = VIH, V
out
= 0 to VCC) I
lkg(O)
— — ± 1 µA
AC Active Supply Current (I
out
= 0 mA, VCC = max)
MCM6227A–20: t
AVAV
= 20 ns
MCM6227A–25: t
AVAV
= 25 ns
MCM6227A–35: t
AVAV
= 35 ns
MCM6227A–45: t
AVAV
= 45 ns
I
CCA
—
—
—
—
120
110
100
90
160
140
130
120
mA
AC Standby Current (VCC = max, E = VIH, f = f
max
) I
SB1
— 7 20 mA
CMOS Standby Current (E ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V
or ≥ VCC – 0.2 V, VCC = max, f = 0 MHz)
I
SB2
— 4 15 mA
Output Low Voltage (IOL = + 8.0 mA) V
OL
— — 0.4 V
Output High Voltage (IOH = – 4.0 mA) V
OH
2.4 — — V
*Typical values are measured at 25°C, VCC = 5 V.
against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to these high–impedance
circuits.
This CMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
This device contains circuitry to protect the
inputs
MCM6227A
3
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
A
= 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Symbol Typ Max Unit
Input Capacitance All Inputs Except Clocks and D, Q
E
and W
C
in
4
5
6
8
pF
Input and Output Capacitance D, Q Cin, C
out
5 8 pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .
Output Load See Figure 1A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE TIMING (See Notes 1 and 2)
6227A–20 6227A–25 6227A–35 6227A–45
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Read Cycle Time t
AVAV
20 — 25 — 35 — 45 — ns 2,3
Address Access Time t
AVQV
— 20 — 25 — 35 — 45 ns
Enable Access Time t
ELQV
— 20 — 25 — 35 — 45 ns 4
Output Hold from Address Change t
AXQX
5 — 5 — 5 — 5 — ns
Enable Low to Output Active t
ELQX
5 — 5 — 5 — 5 — ns 5, 6, 7
Enable High to Output High–Z t
EHQZ
0 9 0 10 0 12 — 18 ns 5, 6, 7
Power Up Time t
ELICCH
0 — 0 — 0 — 0 — ns
Power Down Time t
EHICCL
— 20 — 25 — 35 — 45 ns
NOTES:
1. W
is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E
going low.
5. At any given voltage and temperature, t
EHQZ
max is less than t
ELQX
min, both for a given device and from device to device.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E
≤ VIL).
AC TEST LOADS
Figure 1A Figure 1B
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never provides data later than that time.
TIMING LIMITS
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
5 pF
+ 5 V
OUTPUT
255
Ω
480
Ω
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