Motorola MCM6226BBXJ35, MCM6226BBXJ35R2, MCM6226BBXJ20, MCM6226BBXJ20R2, MCM6226BBXJ25 Datasheet
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
128K x 8 Bit Static Random
Access Memory
The MCM6226BB is a 1,048,576 bit static random access memory organized
as 131,072 words of 8 bits. Static design eliminates the need for external clocks
or timing strobes while CMOS circuitry reduces power consumption and provides
for greater reliability .
The MCM6226BB is equipped with both chip enable (E1
enable (G
) pins, allowing for greater system flexibility and eliminating bus conten-
tion problems.
The MCM6226BB is available in 300 mil and 400 mil, 32 lead surface–mount
SOJ packages.
• Single 5 V ± 10% Power Supply
• Fast Access Times: 15/17/20/25/35 ns
• Equal Address and Chip Enable Access Times
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Low Power Operation: 190/180/165/150/130 mA Maximum, Active AC
BLOCK DIAGRAM
A
A
A
A
A
A
A
A
A
ROW
DECODER
MEMORY MATRIX
512 ROWS x
2048 COLUMNS
and E2) and output
Order this document
by MCM6226BB/D
MCM6226BB
XJ PACKAGE
400 MIL SOJ
CASE 857A–02
EJ PACKAGE
300 MIL SOJ
CASE 857–02
PIN ASSIGNMENT
1
NC
A
2
3
A
A
4
5
A
6
A
A
7
8
A
A
9
A
10
11
A
12
A
13
DQ
14
DQ
15
DQ
V
16
SS
V
32
CC
A
31
E2
30
W
29
A
28
A
27
A
26
A
25
G
24
23
A
22
E1
DQ
21
20
DQ
19
DQ
18
DQ
DQ
17
DQ
DQ
E1
E2
W
G
REV 2
10/31/96
Motorola, Inc. 1996
MOTOROLA FAST SRAM
CONTROL
INPUT
DATA
COLUMN I/O
COLUMN DECODER
A
A
AA
AAAA
PIN NAMES
A Address Inputs. . . . . . . . . . . . . . . . . . . .
W
G
E1
, E2 Chip Enables. . . . . . . . . . . . . . . .
DQ Data Inputs/Outputs. . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . . .
V
CC
V
SS
+ 5 V Power Supply. . . . . . . . . . . . .
Write Enable. . . . . . . . . . . . . . . . . . . . .
Output Enable. . . . . . . . . . . . . . . . . . .
Ground. . . . . . . . . . . . . . . . . . . . . . . .
MCM6226BB
1
TRUTH TABLE
E1 E2 G W Mode I/O Pin Cycle Current
H X X X Not Selected High–Z — I
X L X X Not Selected High–Z — I
L H H H Output Disabled High–Z — I
L H L H Read D
L H X L Write D
H = High, L = Low, X = Don’t Care
out
in
Read I
Write I
SB1
SB1
, I
, I
CCA
CCA
CCA
SB2
SB2
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Power Supply Voltage Relative to V
Voltage Relative to VSS for Any Pin
Except V
Output Current (per I/O) I
Power Dissipation P
Temperature Under Bias T
Operating Temperature T
Storage Temperature T
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
CC
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
SS
Symbol Value Unit
V
CC
Vin, V
out
bias
stg
out
D
A
– 0.5 to 7.0 V
– 0.5 to VCC + 0.5 V
± 20
1.0 W
– 10 to + 85 °C
0 to + 70 °C
– 55 to + 150 °C
mA
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to these high–impedance
circuits.
This CMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
DC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V
*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns).
**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns).
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (E* = VIH, V
AC Active Supply Current (I
VIL or VIH, VIL = 0, VIH ≥ 3 V, cycle time ≥ t
VCC = max) MCM6226BB–20: t
AC Standby Current (VCC = max, E* = VIH, f = f
CMOS Standby Current (E* ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V
or ≥ VCC – 0.2 V, VCC = max, f = 0 MHz)
Output Low Voltage (IOL = + 8.0 mA) V
Output High Voltage (IOH = – 4.0 mA) V
*E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
out
= 0 to VCC) I
out
= 0 mA, all inputs = MCM6226BB–15: t
min, MCM6226BB–17: t
AVAV
MCM6226BB–25: t
MCM6226BB–35: t
) MCM6226BB–15: t
max
MCM6226BB–17: t
MCM6226BB–20: t
MCM6226BB–25: t
MCM6226BB–35: t
AVAV
AVAV
AVAV
AVAV
AVAV
AVAV
AVAV
AVAV
AVAV
AVAV
= 15 ns
= 17 ns
= 20 ns
= 25 ns
= 35 ns
= 15 ns
= 17 ns
= 20 ns
= 25 ns
= 35 ns
CC
IH
IL
lkg(I)
lkg(O)
I
CCA
I
SB1
I
SB2
OL
OH
4.5 5.5 V
2.2 VCC + 0.3** V
– 0.5* 0.8 V
— ± 1 µA
— ± 1 µA
—
—
—
—
—
—
—
—
—
—
— 5 mA
— 0.4 V
2.4 — V
195
180
165
150
130
45
40
35
30
25
mA
mA
MCM6226BB
2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
Input Capacitance All Inputs Except Clocks and DQs
I/O Capacitance DQ C
= 25°C, Periodically Sampled Rather Than 100% Tested)
A
Characteristic
E1
, E2, G, and W
Symbol Typ Max Unit
C
in
C
ck
I/O
4
5
5 8 pF
6
8
AC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
READ CYCLE TIMING (See Notes 1, 2, and 3)
6226BB–15 6226BB–17 6226BB–20 6226BB–25 6226BB–35
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes
Read Cycle Time t
Address Access Time t
Enable Access Time t
Output Enable Access Time t
Output Hold from Address
Change
Enable Low to Output Active t
Output Enable Low to Output
Active
Enable High to Output High–Z t
Output Enable High to Output
High–Z
NOTES:
1. W
is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles.
3. E1
and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
4. All timings are referenced from the last valid address to the first transitioning address.
5. Addresses valid prior to or coincident with E
6. At any given voltage and temperature, t
and from device to device.
7. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.
8. This parameter is sampled and not 100% tested.
9. Device is continuously selected (E
AVAV
AVQV
ELQV
GLQV
t
AXQX
ELQX
t
GLQX
EHQZ
t
GHQZ
≤ VIL, G ≤ VIL).
15 — 17 — 20 — 25 — 35 — ns 4
— 15 — 17 — 20 — 25 — 35 ns
— 15 — 17 — 20 — 25 — 35 ns 5
— 6 — 7 — 7 — 8 — 8 ns
3 — 3 — 3 — 3 — 3 — ns
5 — 5 — 5 — 5 — 5 — ns 6, 7, 8
0 — 0 — 0 — 0 — 0 — ns 6, 7, 8
— 6 — 7 — 7 — 8 — 8 ns 6, 7, 8
— 6 — 7 — 7 — 8 — 8 ns 6, 7, 8
going low.
max is less than t
EHQZ
Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .
Output Load See Figure 1a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ELQX
min, and t
max is less than t
GHQZ
min, both for a given device
GLQX
pF
OUTPUT
Z0 = 50
Ω
(a) (b)
MOTOROLA FAST SRAM
RL = 50
VL = 1.5 V
Ω
+5 V
OUTPUT
255
Ω
Figure 1. AC Test Loads
480
5 pF
TIMING LIMITS
The table of timing values shows either a
Ω
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the device point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
MCM6226BB
3
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