MCM101525
2
MOTOROLA FAST SRAM
TRUTH TABLE (X = Don’t Care)
S
W Operation Data Output Current
H X Not Enabled X L —
L H Read X Q/Q I
EE
L L Write X L I
EE
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Symbol Value Unit
VEE Pin Potential (to Ground) V
EE
– 7.0 to + 0.5 V
Voltage Relative to VCC for Any Pin
Except V
EE
Vin, V
outVEE
– 0.5 to+ 0.5 V
Output Current (per I/O) I
out
– 50 mA
Power Dissipation P
D
2.0 W
Temperature Under Bias T
bias
– 30 to + 85 °C
Operating Temperature T
J
0 to + 60 °C
Storage Temperature — Plastic T
stg
– 55 to + 125 °C
NOTE:Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to the OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time
could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 0 V, VEE = – 5.2 V ± 5%, TJ = 0 to + 60°C, Unless Otherwise Noted)
DC OPERATING CONDITIONS AND SUPPLY CURRENTS
Parameter Symbol Min Typ Max Unit
Supply Voltage (Operating Voltage Range) V
EE
– 5.46 – 5.2 – 4.94 V
Input High Voltage V
IH
– 1165 — – 880 mV
Input Low Voltage V
IL
– 1810 — – 1475 mV
Output High Voltage V
OH
– 1025 — – 880 mV
Output Low Voltage V
OL
– 1810 — – 1620 mV
Input Low Current I
IL
– 50 — — µA
Input High Current I
IH
— — 220 µA
Chip Select Input Low Current I
IL(CS)
0.5 — 170 µA
Operating Power Supply Current: tAVAV = 20 ns (All Outputs Open)* I
EE
— — – 195 mA
Quiescent Power Supply Current: fo = 0 MHz (Outputs Open) I
EEQ
— — – 150 mA
Voltage Compensation (VOH) ∆VOH/∆V
EE
± 35 mV/V @ – 4.94 to – 5.46 V
Voltage Compensation (VOL) ∆VOL/∆V
EE
± 60 mV/V @ – 4.94 to – 5.46 V
*Address Increment
RISE/FALL TIME CHARACTERISTICS
Parameter Symbol Test Condition Min Typ Max Unit
Output Rise Time t
r
20% to 80% 0.5 1.0 1.5 ns
Output Fall Time t
f
20% to 80% 0.5 1.0 1.5 ns
CAPACITANCE (f = 1.0 MHz, T
A
= 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol Typ Max Unit
Input Capacitance Address and Data
S
, W
C
in
C
ck
3.5
4
7
7
pF
Output Capacitance Q, Q C
out
4 8 pF
This device contains circuitry to protect
the inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to these high
impedance circuits.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed circuit board and transverse air flow of at least
500 linear feet per minute is maintained.