Motorola MCF5282, MCF5281 User Manual

MCF5282UM/D

®

Rev. 2

1/2004

MCF5282 ColdFire

Microcontroller User’s Manual

Devices Supported:

MCF5281

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

Motorola Literature Distribution;
P.O. Box 5405
Denver, Colorado 80217
1-800-521-6274 or 480-768-2130

JAPAN:

Motorola Japan Ltd.;
SPS, Technical Information Center,
3-20-1, Minami-Azabu Minato-ku,
Tokyo 106-8573 Japan
81-3-3440-3569

ASIA/PACIFIC:

Motorola Semiconductors H.K. Ltd.;
Silicon Harbour Centre
2 Dai King Street,
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
852-26668334

HOME PAGE:

http://motorola.com/semiconductors

Information in this document is provided solely to enable system and software implementers to use

Motorola products. There are no express or implied copyright licenses granted hereunder to design

or fabricate any integrated circuits or integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein.

Motorola makes no warranty, representation or guarantee regarding the suitability of its products

for any particular purpose, nor does Motorola assume any liability arising out of the application or

use of any product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters which may be provided in

Motorola data sheets and/or specifications can and do vary in different applications and actual

performance may vary over time. All operating parameters, including “Typicals” must be validated

for each customer application by customer’s technical experts. Motorola does not convey any

license under its patent rights nor the rights of others. Motorola products are not designed,

intended, or authorized for use as components in systems intended for surgical implant into the

body, or other applications intended to support or sustain life, or for any other application in which

the failure of the Motorola product could create a situation where personal injury or death may

occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized

application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,

affiliates, and distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that Motorola was

negligent regarding the design or manufacture of the part.

Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital
dna is a trademark of Motorola, Inc. All other product or service names are the property of their
respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

© Motorola, Inc. 2004

Overview

1

ColdFire Core

Enhanced Multiply-Accumulate Unit (EMAC)

Cache

Static RAM (SRAM)

ColdFire Flash Module (CFM)

Power Management

System Control Module (SCM)

Clock Module

Interrupt Controller Modules

Edge Port Module (EPORT)

Chip Select Module

External Interface Module (EIM)

Signal Descriptions

Synchronous DRAM Controller Module

2

3

4

5

6

7

8

9

10

11

12

13

14

15

DMA Controller Module

Fast Ethernet Controller (FEC)

Watchdog Timer Module

Programmable Interrupt Timer (PIT) Modules

General Purpose Timer (GPT) Modules

DMA Timers

Queued Serial Peripheral Interface Module (QSPI)

UART Modules

2

C Module

I

FlexCAN Module

General Purpose I/O Module

Chip Configuration Module (CCM)

Queued Analog-to-Digital Converter (QADC)

Reset Controller Module

16

17

18

19

20

21

22

23

24

25

26

27

28

29

Debug Support

IEEE 1149.1 Test Access Port (JTAG)

Mechanical Data

Electrical Characteristics

Appendix A: List of Memory Maps

Index

30

31

32

33

A

IND

1

Overview

2

3

4

5

6

7

8

9

10

11

12

13

14

15

ColdFire Core

Enhanced Multiply-Accumulate Unit (EMAC)

Cache

Static RAM (SRAM)

ColdFire Flash Module (CFM)

Power Management

System Control Module (SCM)

Clock Module

Interrupt Controller Modules

Edge Port Module (EPORT)

Chip Select Module

External Interface Module (EIM)

Signal Descriptions

Synchronous DRAM Controller Module

16

17

18

19

20

21

22

23

24

25

26

27

28

29

DMA Controller Module

Fast Ethernet Controller (FEC)

Watchdog Timer Module

Programmable Interrupt Timer (PIT) Modules

General Purpose Timer (GPT) Modules

DMA Timers

Queued Serial Peripheral Interface Module (QSPI)

UART Modules

2

C Module

I
FlexCAN Module

General Purpose I/O Module

Chip Configuration Module (CCM)

Queued Analog-to-Digital Converter (QADC)

Reset Controller Module

30

31

32

33

A

IND

Debug Support

IEEE 1149.1 Test Access Port (JTAG)

Mechanical Data

Electrical Characteristics

Appendix A: List of Memory Maps

Index

CONTENTS

Paragraph
Number

Title

Page

Number

Chapter 1

Overview

1.1 MCF5282 Key Features...................................................................................... 1-1

1.1.1 Version 2 ColdFire Core................................................................................. 1-8

1.1.2 System Control Module................................................................................ 1-10

1.1.3 External Interface Module (EIM) ................................................................. 1-10

1.1.4 Chip Select.................................................................................................... 1-11

1.1.5 Power Management ...................................................................................... 1-11

1.1.6 General Input/Output Ports........................................................................... 1-11

1.1.7 Interrupt Controllers (INTC0/INTC1).......................................................... 1-11

1.1.8 SDRAM Controller....................................................................................... 1-11

1.1.9 Test Access Port............................................................................................ 1-12

1.1.10 UART Modules............................................................................................. 1-12

1.1.11 DMA Timers (DTIM0-DTIM3) ................................................................... 1-13

1.1.12 General-Purpose Timers (GPTA/GPTB)...................................................... 1-13

1.1.13 Periodic Interrupt Timers (PIT0-PIT3)......................................................... 1-13

1.1.14 Software Watchdog Timer............................................................................ 1-14

1.1.15 Phase Locked Loop (PLL)............................................................................ 1-14

1.1.16 DMA Controller............................................................................................ 1-14

1.1.17 Reset.............................................................................................................. 1-14

1.2 MCF5282-Specific Features ............................................................................. 1-15

1.2.1 Fast Ethernet Controller (FEC)..................................................................... 1-15

1.2.2 FlexCAN....................................................................................................... 1-15

1.2.3 I

1.2.4 Queued Serial Peripheral Interface (QSPI)................................................... 1-15

1.2.5 Queued Analog-to-Digital Converter (QADC) ............................................ 1-15

2

C Bus.......................................................................................................... 1-15

Chapter 2

ColdFire Core

2.1 Processor Pipelines ............................................................................................. 2-1

2.2 Processor Register Description........................................................................... 2-2

2.2.1 User Programming Model .............................................................................. 2-2

2.2.2 EMAC Programming Model ......................................................................... 2-5

2.2.3 Supervisor Programming Model..................................................................... 2-5

MOTOROLA Contents v

CONTENTS

Paragraph
Number

2.3 Programming Model ........................................................................................... 2-8

2.4 Additions to the Instruction Set Architecture ..................................................... 2-9

2.5 Exception Processing Overview ....................................................................... 2-10

2.6 Exception Stack Frame Definition.................................................................... 2-12

2.7 Processor Exceptions ........................................................................................ 2-13

2.7.1 Access Error Exception ................................................................................ 2-13

2.7.2 Address Error Exception............................................................................... 2-14

2.7.3 Illegal Instruction Exception......................................................................... 2-14

2.7.4 Divide-By-Zero............................................................................................. 2-14

2.7.5 Privilege Violation........................................................................................ 2-14

2.7.6 Trace Exception ............................................................................................ 2-14

2.7.7 Unimplemented Line-A Opcode................................................................... 2-15

2.7.8 Unimplemented Line-F Opcode ................................................................... 2-15

2.7.9 Debug Interrupt............................................................................................. 2-15

2.7.10 RTE and Format Error Exception................................................................. 2-16

2.7.11 TRAP Instruction Exception......................................................................... 2-16

2.7.12 Interrupt Exception ....................................................................................... 2-16

2.7.13 Fault-on-Fault Halt ....................................................................................... 2-16

2.7.14 Reset Exception ............................................................................................ 2-16

2.8 Instruction Execution Timing ........................................................................... 2-21

2.8.1 Timing Assumptions..................................................................................... 2-21

2.8.2 MOVE Instruction Execution Times ............................................................ 2-22

2.9 Standard One Operand Instruction Execution Times ....................................... 2-24

2.10 Standard Two Operand Instruction Execution Times....................................... 2-24

2.11 Miscellaneous Instruction Execution Times..................................................... 2-26

2.12 EMAC Instruction Execution Times ................................................................ 2-27

2.13 Branch Instruction Execution Times ................................................................ 2-28

2.14 ColdFire Instruction Set Architecture Enhancements ...................................... 2-28

Title

Page

Number

Chapter 3

Enhanced Multiply-Accumulate Unit (EMAC)

3.1 Multiply-Accumulate Unit.................................................................................. 3-1

3.2 Introduction to the MAC..................................................................................... 3-2

3.3 General Operation............................................................................................... 3-3

3.4 Memory Map/Register Set.................................................................................. 3-6

3.4.1 MAC Status Register (MACSR) .................................................................... 3-6

3.4.2 Mask Register (MASK)................................................................................ 3-11

3.5 EMAC Instruction Set Summary...................................................................... 3-12

3.5.1 EMAC Instruction Execution Times ............................................................ 3-12

3.5.2 Data Representation...................................................................................... 3-13

3.5.3 MAC Opcodes .............................................................................................. 3-14

vi MCF5282 User’s Manual MOTOROLA

CONTENTS

Paragraph
Number

Title

Page

Number

Chapter 4

Cache

4.1 Cache Features.................................................................................................... 4-1

4.2 Cache Physical Organization .............................................................................. 4-1

4.3 Cache Operation ................................................................................................. 4-3

4.3.1 Interaction with Other Modules...................................................................... 4-3

4.3.2 Memory Reference Attributes ........................................................................ 4-4

4.3.3 Cache Coherency and Invalidation................................................................. 4-4

4.3.4 Reset................................................................................................................ 4-5

4.3.5 Cache Miss Fetch Algorithm/Line Fills ......................................................... 4-5

4.4 Cache Programming Model ................................................................................ 4-7

4.4.1 Cache Registers Memory Map ....................................................................... 4-7

4.4.2 Cache Registers............................................................................................... 4-7

Chapter 5

Static RAM (SRAM)

5.1 SRAM Features................................................................................................... 5-1

5.2 SRAM Operation ................................................................................................ 5-1

5.3 SRAM Programming Model............................................................................... 5-1

5.3.1 SRAM Base Address Register (RAMBAR)................................................... 5-2

5.3.2 SRAM Initialization........................................................................................ 5-3

5.3.3 SRAM Initialization Code .............................................................................. 5-4

5.3.4 Power Management ........................................................................................ 5-4

Chapter 6

ColdFire Flash Module (CFM)

6.1 Features............................................................................................................... 6-1

6.2 Block Diagram.................................................................................................... 6-2

6.3 Memory Map ...................................................................................................... 6-4

6.3.1 CFM Configuration Field ............................................................................... 6-5

6.3.2 Flash Base Address Register (FLASHBAR).................................................. 6-5

6.3.3 CFM Registers ................................................................................................ 6-8

6.3.4 Register Descriptions...................................................................................... 6-9

6.4 CFM Operation ................................................................................................. 6-17

6.4.1 Read Operations............................................................................................ 6-17

6.4.2 Write Operations........................................................................................... 6-17

6.4.3 Program and Erase Operations ..................................................................... 6-17

6.4.4 Stop Mode..................................................................................................... 6-22

6.4.5 Master Mode................................................................................................. 6-23

MOTOROLA Contents vii

CONTENTS

Paragraph
Number

6.5 Flash Security Operation .................................................................................. 6-23

6.5.1 Back Door Access......................................................................................... 6-24

6.5.2 Erase Verify Check....................................................................................... 6-24

6.6 Reset.................................................................................................................. 6-24

6.7 Interrupts........................................................................................................... 6-25

Title

Page

Number

Chapter 7

Power Management

7.1 Features............................................................................................................... 7-1

7.2 Memory Map and Registers................................................................................ 7-1

7.2.1 Programming Model....................................................................................... 7-1

7.2.2 Memory Map .................................................................................................. 7-2

7.2.3 Register Descriptions...................................................................................... 7-2

7.3 Functional Description........................................................................................ 7-5

7.3.1 Low-Power Modes.......................................................................................... 7-5

7.3.2 Peripheral Behavior in Low-Power Modes .................................................... 7-7

7.3.3 Summary of Peripheral State During Low-Power Modes............................ 7-16

Chapter 8

System Control Module (SCM)

8.1 Overview............................................................................................................. 8-1

8.2 Features............................................................................................................... 8-1

8.3 Memory Map and Register Definition................................................................ 8-2

8.4 Register Descriptions.......................................................................................... 8-3

8.4.1 Internal Peripheral System Base Address Register (IPSBAR)....................... 8-3

8.4.2 Memory Base Address Register (RAMBAR) ................................................ 8-4

8.4.3 Core Reset Status Register (CRSR)................................................................ 8-6

8.4.4 Core Watchdog Control Register (CWCR) .................................................... 8-6

8.4.5 Core Watchdog Service Register (CWSR)..................................................... 8-9

8.5 Internal Bus Arbitration ...................................................................................... 8-9

8.5.1 Overview....................................................................................................... 8-11

8.5.2 Arbitration Algorithms ................................................................................. 8-11

8.5.3 Bus Master Park Register (MPARK)............................................................ 8-12

8.6 System Access Control Unit (SACU)............................................................... 8-14

8.6.1 Overview....................................................................................................... 8-14

8.6.2 Features......................................................................................................... 8-14

8.6.3 Memory Map/Register Definition ................................................................ 8-15

viii MCF5282 User’s Manual MOTOROLA

CONTENTS

Paragraph
Number

Title

Page

Number

Chapter 9

Clock Module

9.1 Features............................................................................................................... 9-1

9.2 Modes of Operation ............................................................................................ 9-1

9.2.1 Normal PLL Mode.......................................................................................... 9-1

9.2.2 1:1 PLL Mode................................................................................................. 9-2

9.2.3 External Clock Mode...................................................................................... 9-2

9.3 Low-power Mode Operation .............................................................................. 9-2

9.4 Block Diagram.................................................................................................... 9-3

9.5 Signal Descriptions ............................................................................................. 9-4

9.5.1 EXTAL ........................................................................................................... 9-4

9.5.2 XTAL.............................................................................................................. 9-5

9.5.3 CLKOUT ........................................................................................................ 9-5

9.5.4 CLKMOD[1:0] ............................................................................................... 9-5

9.5.5 RSTOUT......................................................................................................... 9-5

9.6 Memory Map and Registers................................................................................ 9-5

9.6.1 Module Memory Map..................................................................................... 9-5

9.6.2 Register Descriptions...................................................................................... 9-6

9.7 Functional Description...................................................................................... 9-10

9.7.1 System Clock Modes .................................................................................... 9-10

9.7.2 Clock Operation During Reset...................................................................... 9-11

9.7.3 System Clock Generation ............................................................................. 9-11

9.7.4 PLL Operation .............................................................................................. 9-12

Chapter 10

Interrupt Controller Modules

10.1 68K/ColdFire Interrupt Architecture Overview ............................................... 10-1

10.1.1 Interrupt Controller Theory of Operation ..................................................... 10-3

10.2 Memory Map .................................................................................................... 10-5

10.3 Register Descriptions........................................................................................ 10-6

10.3.1 Interrupt Pending Registers (IPRHn, IPRLn)............................................... 10-6

10.3.2 Interrupt Mask Register (IMRHn, IMRLn) .................................................. 10-8

10.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)................................... 10-9

10.3.4 Interrupt Request Level Register (IRLRn) ................................................. 10-10

10.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn)............ 10-11

10.3.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63)).................................. 10-11

10.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK). 10-15

10.4 Prioritization Between Interrupt Controllers .................................................. 10-16

10.5 Low-Power Wakeup Operation ...................................................................... 10-17

MOTOROLA Contents ix

CONTENTS

Paragraph
Number

Title

Page

Number

Chapter 11

Edge Port Module (EPORT)

11.1 Introduction....................................................................................................... 11-1

11.2 Low-Power Mode Operation ............................................................................ 11-1

11.3 Interrupt/General-Purpose I/O Pin Descriptions............................................... 11-2

11.4 Memory Map and Registers.............................................................................. 11-3

11.4.1 Memory Map ................................................................................................ 11-3

11.4.2 Registers........................................................................................................ 11-3

Chapter 12

Chip Select Module

12.1 Overview........................................................................................................... 12-1

12.2 Chip Select Module Signals.............................................................................. 12-1

12.3 Chip Select Operation....................................................................................... 12-3

12.3.1 General Chip Select Operation ..................................................................... 12-3

12.4 Chip Select Registers ........................................................................................ 12-5

12.4.1 Chip Select Module Registers....................................................................... 12-6

Chapter 13

External Interface Module (EIM)

13.1 Features............................................................................................................. 13-1

13.2 Bus and Control Signals ................................................................................... 13-1

13.3 Bus Characteristics ........................................................................................... 13-2

13.4 Data Transfer Operation ................................................................................... 13-2

13.4.1 Bus Cycle Execution..................................................................................... 13-3

13.4.2 Data Transfer Cycle States ........................................................................... 13-5

13.4.3 Read Cycle.................................................................................................... 13-6

13.4.4 Write Cycle................................................................................................... 13-8

13.4.5 Fast Termination Cycles ............................................................................... 13-9

13.4.6 Back-to-Back Bus Cycles ........................................................................... 13-10

13.4.7 Burst Cycles................................................................................................ 13-10

13.5 Misaligned Operands ...................................................................................... 13-14

Chapter 14

Signal Descriptions

14.1 Overview........................................................................................................... 14-1

14.1.1 Single-Chip Mode....................................................................................... 14-17

14.1.2 External Boot Mode.................................................................................... 14-17

x MCF5282 User’s Manual MOTOROLA

CONTENTS

Paragraph
Number

14.2 MCF5282 External Signals............................................................................. 14-18

14.2.1 External Interface Module (EIM) Signals .................................................. 14-18

14.2.2 SDRAM Controller Signals........................................................................ 14-21

14.2.3 Clock and Reset Signals ............................................................................. 14-22

14.2.4 Chip Configuration Signals ........................................................................ 14-22

14.2.5 External Interrupt Signals ........................................................................... 14-23

14.2.6 Ethernet Module Signals............................................................................. 14-23

14.2.7 Queued Serial Peripheral Interface (QSPI) Signals.................................... 14-25

14.2.8 FlexCAN Signals ........................................................................................ 14-26

14.2.9 I2C Signals .................................................................................................. 14-26

14.2.10 UART Module Signals ............................................................................... 14-26

14.2.11 General Purpose Timer Signals .................................................................. 14-27

14.2.12 DMA Timer Signals.................................................................................... 14-28

14.2.13 Analog-to-Digital Converter Signals.......................................................... 14-29

14.2.14 Debug Support Signals ............................................................................... 14-30

14.2.15 Test Signals................................................................................................. 14-32

14.2.16 Power and Reference Signals ..................................................................... 14-33

Title

Page

Number

Chapter 15

Synchronous DRAM Controller Module

15.1 Overview........................................................................................................... 15-1

15.1.1 Definitions .................................................................................................... 15-1

15.1.2 Block Diagram and Major Components ....................................................... 15-2

15.2 SDRAM Controller Operation.......................................................................... 15-3

15.2.1 DRAM Controller Signals ............................................................................ 15-4

15.2.2 Memory Map for SDRAMC Registers......................................................... 15-4

15.2.3 General Synchronous Operation Guidelines................................................. 15-9

15.2.4 Initialization Sequence................................................................................ 15-17

15.3 SDRAM Example ........................................................................................... 15-19

15.3.1 SDRAM Interface Configuration................................................................ 15-20

15.3.2 DCR Initialization....................................................................................... 15-20

15.3.3 DACR Initialization.................................................................................... 15-21

15.3.4 DMR Initialization...................................................................................... 15-22

15.3.5 Mode Register Initialization ....................................................................... 15-23

15.3.6 Initialization Code....................................................................................... 15-24

Chapter 16

DMA Controller Module

16.1 Overview........................................................................................................... 16-1

16.1.1 DMA Module Features ................................................................................. 16-2

MOTOROLA Contents xi

CONTENTS

Paragraph
Number

16.2 DMA Request Control (DMAREQC) .............................................................. 16-3

16.3 DMA Transfer Overview.................................................................................. 16-4

16.4 DMA Controller Module Programming Model................................................ 16-5

16.4.1 Source Address Registers (SAR0–SAR3) .................................................... 16-6

16.4.2 Destination Address Registers (DAR0–DAR3) ........................................... 16-6

16.4.3 Byte Count Registers (BCR0–BCR3) .......................................................... 16-7

16.4.4 DMA Control Registers (DCR0–DCR3)...................................................... 16-8

16.4.5 DMA Status Registers (DSR0–DSR3) ....................................................... 16-10

16.5 DMA Controller Module Functional Description .......................................... 16-11

16.5.1 Transfer Requests (Cycle-Steal and Continuous Modes)........................... 16-11

16.5.2 Data Transfer Modes .................................................................................. 16-12

16.5.3 Channel Initialization and Startup .............................................................. 16-13

16.5.4 Data Transfer .............................................................................................. 16-14

16.5.5 Termination................................................................................................. 16-15

Title

Page

Number

Chapter 17

Fast Ethernet Controller (FEC)

17.1 Overview........................................................................................................... 17-1

17.1.1 Features......................................................................................................... 17-1

17.2 Modes of Operation .......................................................................................... 17-2

17.2.1 Full and Half Duplex Operation ................................................................... 17-2

17.2.2 Interface Options........................................................................................... 17-2

17.2.3 Address Recognition Options ....................................................................... 17-3

17.2.4 Internal Loopback......................................................................................... 17-3

17.3 FEC Top-Level Functional Diagram ................................................................ 17-4

17.4 Functional Description...................................................................................... 17-5

17.4.1 Initialization Sequence.................................................................................. 17-6

17.4.2 User Initialization (Prior to Asserting ECR[ETHER_EN]).......................... 17-6

17.4.3 Microcontroller Initialization........................................................................ 17-7

17.4.4 User Initialization (After Asserting ECR[ETHER_EN]) ............................. 17-7

17.4.5 Network Interface Options............................................................................ 17-8

17.4.6 FEC Frame Transmission ............................................................................. 17-9

17.4.7 FEC Frame Reception................................................................................. 17-10

17.4.8 Ethernet Address Recognition .................................................................... 17-11

17.4.9 Hash Algorithm........................................................................................... 17-13

17.4.10 Full Duplex Flow Control........................................................................... 17-16

17.4.11 Inter-Packet Gap (IPG) Time...................................................................... 17-17

17.4.12 Collision Handling...................................................................................... 17-17

17.4.13 Internal and External Loopback.................................................................. 17-17

17.4.14 Ethernet Error-Handling Procedure............................................................ 17-18

17.5 Programming Model ....................................................................................... 17-20

xii MCF5282 User’s Manual MOTOROLA

CONTENTS

Paragraph
Number

17.5.1 Top Level Module Memory Map ............................................................... 17-20

17.5.2 Detailed Memory Map (Control/Status Registers) ..................................... 17-20

17.5.3 MIB Block Counters Memory Map............................................................ 17-21

17.5.4 Registers...................................................................................................... 17-23

17.6 Buffer Descriptors........................................................................................... 17-45

17.6.1 Driver/DMA Operation with Buffer Descriptors........................................ 17-45

17.6.2 Ethernet Receive Buffer Descriptor (RxBD).............................................. 17-47

17.6.3 Ethernet Transmit Buffer Descriptor (TxBD) ............................................ 17-49

Title

Page

Number

Chapter 18

Watchdog Timer Module

18.1 Introduction....................................................................................................... 18-1

18.2 Low-Power Mode Operation ............................................................................ 18-1

18.3 Block Diagram.................................................................................................. 18-2

18.4 Signals............................................................................................................... 18-2

18.5 Memory Map and Registers.............................................................................. 18-2

18.5.1 Memory Map ................................................................................................ 18-2

18.5.2 Registers........................................................................................................ 18-3

Chapter 19

Programmable Interrupt Timer Modules (PIT0–PIT3)

19.1 Overview........................................................................................................... 19-1

19.2 Block Diagram.................................................................................................. 19-1

19.3 Low-Power Mode Operation ............................................................................ 19-2

19.4 Signals............................................................................................................... 19-2

19.5 Memory Map and Registers.............................................................................. 19-3

19.5.1 Memory Map ................................................................................................ 19-3

19.5.2 Registers........................................................................................................ 19-3

19.6 Functional Description...................................................................................... 19-6

19.6.1 Set-and-Forget Timer Operation................................................................... 19-6

19.6.2 Free-Running Timer Operation .................................................................... 19-7

19.6.3 Timeout Specifications ................................................................................. 19-7

19.7 Interrupt Operation ........................................................................................... 19-8

Chapter 20

General Purpose Timer Modules

(GPTA and GPTB)

20.1 Features............................................................................................................. 20-1

20.2 Block Diagram.................................................................................................. 20-2

MOTOROLA Contents xiii

CONTENTS

Paragraph
Number

20.3 Low-Power Mode Operation ............................................................................ 20-3

20.4 Signal Description............................................................................................. 20-3

20.4.1 GPTn[2:0] ..................................................................................................... 20-3

20.4.2 GPTn3........................................................................................................... 20-4

20.4.3 SYNCn.......................................................................................................... 20-4

20.5 Memory Map and Registers.............................................................................. 20-4

20.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS) ................. 20-5

20.5.2 GPT Compare Force Register (GPCFORC)................................................. 20-6

20.5.3 GPT Output Compare 3 Mask Register (GPTOC3M).................................. 20-6

20.5.4 GPT Output Compare 3 Data Register (GPTOC3D).................................... 20-7

20.5.5 GPT Counter Register (GPTCNT) ............................................................... 20-7

20.5.6 GPT System Control Register 1 (GPTSCR1)............................................... 20-8

20.5.7 GPT Toggle-On-Overflow Register (GPTTOV).......................................... 20-9

20.5.8 GPT Control Register 1 (GPTCTL1)............................................................ 20-9

20.5.9 GPT Control Register 2 (GPTCTL2).......................................................... 20-10

20.5.10 GPT Interrupt Enable Register (GPTIE) .................................................... 20-10

20.5.11 GPT System Control Register 2 (GPTSCR2)............................................. 20-11

20.5.12 GPT Flag Register 1 (GPTFLG1)............................................................... 20-12

20.5.13 GPT Flag Register 2 (GPTFLG2)............................................................... 20-12

20.5.14 GPT Channel Registers (GPTCn)............................................................... 20-13

20.5.15 Pulse Accumulator Control Register (GPTPACTL) .................................. 20-13

20.5.16 Pulse Accumulator Flag Register (GPTPAFLG)........................................ 20-14

20.5.17 Pulse Accumulator Counter Register (GPTPACNT) ................................. 20-15

20.5.18 GPT Port Data Register (GPTPORT)......................................................... 20-16

20.5.19 GPT Port Data Direction Register (GPTDDR)........................................... 20-16

20.6 Functional Description.................................................................................... 20-17

20.6.1 Prescaler...................................................................................................... 20-17

20.6.2 Input Capture .............................................................................................. 20-17

20.6.3 Output Compare.......................................................................................... 20-17

20.6.4 Pulse Accumulator...................................................................................... 20-18

20.6.5 Event Counter Mode................................................................................... 20-18

20.6.6 Gated Time Accumulation Mode ............................................................... 20-19

20.6.7 General-Purpose I/O Ports.......................................................................... 20-19

20.7 Reset................................................................................................................ 20-21

20.8 Interrupts......................................................................................................... 20-21

20.8.1 GPT Channel Interrupts (CnF) ................................................................... 20-22

20.8.2 Pulse Accumulator Overflow (PAOVF)..................................................... 20-22

20.8.3 Pulse Accumulator Input (PAIF) ................................................................ 20-22

20.8.4 Timer Overflow (TOF) ............................................................................... 20-22

Title

Page

Number

xiv MCF5282 User’s Manual MOTOROLA

CONTENTS

Paragraph
Number

Title

Page

Number

Chapter 21

DMA Timers (DTIM0–DTIM3)

21.1 Overview........................................................................................................... 21-1

21.1.1 Key Features ................................................................................................. 21-2

21.2 DMA Timer Programming Model.................................................................... 21-2

21.2.1 Prescaler........................................................................................................ 21-2

21.2.2 Capture Mode ............................................................................................... 21-3

21.2.3 Reference Compare....................................................................................... 21-3

21.2.4 Output Mode................................................................................................. 21-3

21.2.5 Memory Map ................................................................................................ 21-3

21.2.6 DMA Timer Mode Registers (DTMRn)....................................................... 21-4

21.2.7 DMA Timer Extended Mode Registers (DTXMRn).................................... 21-5

21.2.8 DMA Timer Event Registers (DTERn)........................................................ 21-6

21.2.9 DMA Timer Reference Registers (DTRRn)................................................. 21-7

21.2.10 DMA Timer Capture Registers (DTCRn) .................................................... 21-7

21.2.11 DMA Timer Counters (DTCNn) .................................................................. 21-8

21.3 Using the DMA Timer Modules....................................................................... 21-8

21.3.1 Code Example............................................................................................... 21-9

21.3.2 Calculating Time-Out Values ..................................................................... 21-10

Chapter 22

Queued Serial Peripheral Interface

(QSPI) Module

22.1 Overview........................................................................................................... 22-1

22.2 Features............................................................................................................. 22-1

22.3 Module Description .......................................................................................... 22-1

22.3.1 Interface and Signals..................................................................................... 22-2

22.3.2 Internal Bus Interface.................................................................................... 22-3

22.4 Operation .......................................................................................................... 22-3

22.4.1 QSPI RAM.................................................................................................... 22-4

22.4.2 Baud Rate Selection...................................................................................... 22-6

22.4.3 Transfer Delays............................................................................................. 22-7

22.4.4 Transfer Length............................................................................................. 22-8

22.4.5 Data Transfer ................................................................................................ 22-8

22.5 Programming Model ......................................................................................... 22-9

22.5.1 QSPI Mode Register (QMR) ...................................................................... 22-10

22.5.2 QSPI Delay Register (QDLYR) ................................................................. 22-11

22.5.3 QSPI Wrap Register (QWR)....................................................................... 22-12

22.5.4 QSPI Interrupt Register (QIR).................................................................... 22-13

22.5.5 QSPI Address Register (QAR) ................................................................... 22-14

MOTOROLA Contents xv

CONTENTS

Paragraph
Number

22.5.6 QSPI Data Register (QDR)......................................................................... 22-14

22.5.7 Command RAM Registers (QCR0–QCR15).............................................. 22-15

22.5.8 Programming Example ............................................................................... 22-16

Title

Page

Number

Chapter 23

UART Modules

23.1 Overview........................................................................................................... 23-1

23.2 Serial Module Overview................................................................................... 23-2

23.3 Register Descriptions........................................................................................ 23-3

23.3.1 UART Mode Registers 1 (UMR1n).............................................................. 23-4

23.3.2 UART Mode Register 2 (UMR2n) ............................................................... 23-6

23.3.3 UART Status Registers (USRn) ................................................................... 23-7

23.3.4 UART Clock Select Registers (UCSRn) ...................................................... 23-8

23.3.5 UART Command Registers (UCRn) ............................................................ 23-9

23.3.6 UART Receive Buffers (URBn)................................................................. 23-11

23.3.7 UART Transmit Buffers (UTBn) ............................................................... 23-11

23.3.8 UART Input Port Change Registers (UIPCRn).......................................... 23-12

23.3.9 UART Auxiliary Control Register (UACRn)............................................. 23-13

23.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn).......................... 23-13

23.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n) ......................... 23-14

23.3.12 UART Input Port Register (UIPn).............................................................. 23-15

23.3.13 UART Output Port Command Registers (UOP1n/UOP0n) ....................... 23-15

23.4 UART Module Signal Definitions.................................................................. 23-17

23.5 Operation ........................................................................................................ 23-18

23.5.1 Transmitter/Receiver Clock Source............................................................ 23-18

23.5.2 Transmitter and Receiver Operating Modes............................................... 23-20

23.5.3 Looping Modes........................................................................................... 23-25

23.5.4 Multidrop Mode.......................................................................................... 23-26

23.5.5 Bus Operation ............................................................................................. 23-28

23.5.6 Programming .............................................................................................. 23-28

Chapter 24

2

I

C Interface

24.1 Overview........................................................................................................... 24-1

24.2 Interface Features.............................................................................................. 24-1

24.3 I2C System Configuration................................................................................. 24-3

24.4 I

24.4.1 Arbitration Procedure ................................................................................... 24-4

24.4.2 Clock Synchronization.................................................................................. 24-5

24.4.3 Handshaking ................................................................................................. 24-5

xvi MCF5282 User’s Manual MOTOROLA

2

C Protocol ...................................................................................................... 24-3

CONTENTS

Paragraph
Number

Title

Page

Number

24.4.4 Clock Stretching ........................................................................................... 24-5

24.5 Programming Model ......................................................................................... 24-6

24.5.1 I2C Address Register (I2ADR)..................................................................... 24-6

24.5.2 I2C Frequency Divider Register (I2FDR)..................................................... 24-7

2

24.5.3 I

24.5.4 I

C Control Register (I2CR)......................................................................... 24-8

2

C Status Register (I2SR)............................................................................ 24-9

24.5.5 I2C Data I/O Register (I2DR) ..................................................................... 24-10

2

24.6 I

C Programming Examples ........................................................................... 24-10

24.6.1 Initialization Sequence................................................................................ 24-10

24.6.2 Generation of START................................................................................. 24-11

24.6.3 Post-Transfer Software Response............................................................... 24-11

24.6.4 Generation of STOP.................................................................................... 24-12

24.6.5 Generation of Repeated START................................................................. 24-13

24.6.6 Slave Mode ................................................................................................. 24-13

24.6.7 Arbitration Lost........................................................................................... 24-14

Chapter 25

FlexCAN

25.1 Features............................................................................................................. 25-1

25.1.1 FlexCAN Memory Map................................................................................ 25-3

25.1.2 External Signals ............................................................................................ 25-3

25.2 The CAN System .............................................................................................. 25-4

25.3 Message Buffers ............................................................................................... 25-4

25.3.1 Message Buffer Structure ............................................................................. 25-4

25.3.2 Message Buffer Memory Map...................................................................... 25-7

25.4 Functional Overview......................................................................................... 25-8

25.4.1 Transmit Process........................................................................................... 25-9

25.4.2 Receive Process ............................................................................................ 25-9

25.4.3 Message Buffer Handling ........................................................................... 25-10

25.4.4 Remote Frames ........................................................................................... 25-12

25.4.5 Overload Frames......................................................................................... 25-13

25.4.6 Time Stamp................................................................................................. 25-13

25.4.7 Listen-Only Mode....................................................................................... 25-13

25.4.8 Bit Timing................................................................................................... 25-14

25.4.9 FlexCAN Error Counters............................................................................ 25-15

25.4.10 FlexCAN Initialization Sequence ............................................................... 25-16

25.4.11 Special Operating Modes............................................................................ 25-17

25.4.12 Interrupts..................................................................................................... 25-19

25.5 Programmer’s Model ...................................................................................... 25-20

25.5.1 CAN Module Configuration Register (CANMCR).................................... 25-20

25.5.2 FlexCAN Control Register 0 (CANCTRL0).............................................. 25-22

MOTOROLA Contents xvii

CONTENTS

Paragraph
Number

25.5.3 FlexCAN Control Register 1 (CANCTRL1).............................................. 25-23

25.5.4 Prescaler Divide Register (PRESDIV) ....................................................... 25-24

25.5.5 FlexCAN Control Register 2 (CANCTRL2).............................................. 25-25

25.5.6 Free Running Timer (TIMER).................................................................... 25-26

25.5.7 Rx Mask Registers...................................................................................... 25-26

25.5.8 FlexCAN Error and Status Register (ESTAT) ........................................... 25-28

25.5.9 Interrupt Mask Register (IMASK).............................................................. 25-30

25.5.10 Interrupt Flag Register (IFLAG)................................................................. 25-31

25.5.11 FlexCAN Receive Error Counter (RXECTR) ............................................ 25-32

25.5.12 FlexCAN Transmit Error Counter (TXECTR)........................................... 25-32

Title

Page

Number

Chapter 26

General Purpose I/O Module

26.1 Introduction....................................................................................................... 26-1

26.1.1 Overview....................................................................................................... 26-3

26.1.2 Features......................................................................................................... 26-3

26.1.3 Modes of Operation ...................................................................................... 26-3

26.2 External Signal Description .............................................................................. 26-4

26.3 Memory Map/Register Definition .................................................................... 26-6

26.3.1 Register Overview ........................................................................................ 26-6

26.3.2 Register Descriptions.................................................................................... 26-8

26.4 Functional Description.................................................................................... 26-25

26.4.1 Overview..................................................................................................... 26-25

26.4.2 Port Digital I/O Timing .............................................................................. 26-25

26.5 Initialization/Application Information............................................................ 26-26

Chapter 27

Queued Analog-to-Digital Converter (QADC)

27.1 Features............................................................................................................. 27-1

27.2 Block Diagram.................................................................................................. 27-2

27.3 Modes of Operation .......................................................................................... 27-3

27.3.1 Debug Mode ................................................................................................. 27-3

27.3.2 Stop Mode..................................................................................................... 27-3

27.4 Signals............................................................................................................... 27-4

27.4.1 Port QA Signal Functions............................................................................. 27-4

27.4.2 Port QB Signal Functions ............................................................................. 27-5

27.4.3 External Trigger Input Signals...................................................................... 27-6

27.4.4 Multiplexed Address Output Signals............................................................ 27-6

27.4.5 Multiplexed Analog Input Signals................................................................ 27-6

27.4.6 Voltage Reference Signals............................................................................ 27-7

xviii MCF5282 User’s Manual MOTOROLA

CONTENTS

Paragraph
Number

27.4.7 Dedicated Analog Supply Signals ................................................................ 27-7

27.4.8 Dedicated Digital I/O Port Supply Signal..................................................... 27-7

27.5 Memory Map .................................................................................................... 27-7

27.6 Register Descriptions........................................................................................ 27-8

27.6.1 QADC Module Configuration Register (QADCMCR)................................ 27-8

27.6.2 QADC Test Register (QADCTEST) ............................................................ 27-9

27.6.3 Port Data Registers (PORTQA and PORTQB) ............................................ 27-9

27.6.4 Port QA and QB Data Direction Register (DDRQA and DDRQB)........... 27-10

27.6.5 Control Registers ........................................................................................ 27-11

27.6.6 Status Registers........................................................................................... 27-19

27.6.7 Conversion Command Word Table (CCW) ............................................... 27-26

27.6.8 Result Registers .......................................................................................... 27-29

27.7 Functional Description.................................................................................... 27-31

27.7.1 Result Coherency........................................................................................ 27-31

27.7.2 External Multiplexing ................................................................................. 27-31

27.7.3 Analog Subsystem ...................................................................................... 27-34

27.8 Digital Control Subsystem.............................................................................. 27-37

27.8.1 Queue Priority Timing Examples ............................................................... 27-38

27.8.2 Boundary Conditions .................................................................................. 27-49

27.8.3 Scan Modes................................................................................................. 27-50

27.8.4 Disabled Mode............................................................................................ 27-50

27.8.5 Reserved Mode ........................................................................................... 27-50

27.8.6 Single-Scan Modes ..................................................................................... 27-50

27.8.7 Continuous-Scan Modes............................................................................. 27-54

27.8.8 QADC Clock (QCLK) Generation ............................................................. 27-57

27.8.9 Periodic/Interval Timer............................................................................... 27-58

27.8.10 Conversion Command Word Table ............................................................ 27-59

27.8.11 Result Word Table...................................................................................... 27-62

27.9 Signal Connection Considerations.................................................................. 27-62

27.9.1 Analog Reference Signals........................................................................... 27-63

27.9.2 Analog Power Signals................................................................................. 27-63

27.9.3 Conversion Timing Schemes...................................................................... 27-64

27.9.4 Analog Supply Filtering and Grounding .................................................... 27-67

27.9.5 Accommodating Positive/Negative Stress Conditions ............................... 27-69

27.9.6 Analog Input Considerations ...................................................................... 27-71

27.9.7 Analog Input Pins ....................................................................................... 27-73

27.10 Interrupts......................................................................................................... 27-75

27.10.1 Interrupt Operation ..................................................................................... 27-75

27.10.2 Interrupt Sources......................................................................................... 27-76

Title

Page

Number

MOTOROLA Contents xix

CONTENTS

Paragraph
Number

Title

Page

Number

Chapter 28

Reset Controller Module

28.1 Features............................................................................................................. 28-1

28.2 Block Diagram.................................................................................................. 28-2

28.3 Signals............................................................................................................... 28-2

28.3.1 RSTI............................................................................................................. 28-2

28.3.2 RSTO

28.4 Memory Map and Registers.............................................................................. 28-3

28.4.1 Reset Control Register (RCR) ...................................................................... 28-3

28.4.2 Reset Status Register (RSR) ......................................................................... 28-4

28.5 Functional Description...................................................................................... 28-6

28.5.1 Reset Sources................................................................................................ 28-6

28.5.2 Reset Control Flow ....................................................................................... 28-8

28.5.3 Concurrent Resets....................................................................................... 28-10

........................................................................................................... 28-2

Chapter 29

Debug Support

29.1 Overview........................................................................................................... 29-1

29.2 Signal Description............................................................................................. 29-2

29.3 Real-Time Trace Support.................................................................................. 29-3

29.3.1 Begin Execution of Taken Branch (PST = 0x5)........................................... 29-4

29.4 Programming Model ......................................................................................... 29-5

29.4.1 Revision A Shared Debug Resources ........................................................... 29-7

29.4.2 Address Attribute Trigger Register (AATR)................................................ 29-8

29.4.3 Address Breakpoint Registers (ABLR, ABHR) ........................................... 29-9

29.4.4 Configuration/Status Register (CSR) ......................................................... 29-10

29.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)....................................... 29-12

29.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR).................... 29-13

29.4.7 Trigger Definition Register (TDR)............................................................. 29-14

29.5 Background Debug Mode (BDM) .................................................................. 29-16

29.5.1 CPU Halt..................................................................................................... 29-16

29.5.2 BDM Serial Interface.................................................................................. 29-18

29.5.3 BDM Command Set ................................................................................... 29-20

29.6 Real-Time Debug Support .............................................................................. 29-37

29.6.1 Theory of Operation.................................................................................... 29-37

29.6.2 Concurrent BDM and Processor Operation................................................ 29-39

29.7 Processor Status, DDATA Definition............................................................. 29-40

29.7.1 User Instruction Set .................................................................................... 29-40

29.7.2 Supervisor Instruction Set........................................................................... 29-44

29.8 Motorola-Recommended BDM Pinout........................................................... 29-46

xx MCF5282 User’s Manual MOTOROLA

CONTENTS

Paragraph
Number

Title

Page

Number

Chapter 30

Chip Configuration Module (CCM)

30.1 Features............................................................................................................. 30-1

30.2 Modes of Operation .......................................................................................... 30-1

30.2.1 Master Mode................................................................................................. 30-2

30.2.2 Single-Chip Mode......................................................................................... 30-2

30.3 Block Diagram.................................................................................................. 30-2

30.4 Signal Descriptions ........................................................................................... 30-3

30.4.1 RCON ........................................................................................................... 30-3

30.4.2 CLKMOD[1:0] ............................................................................................. 30-3

30.4.3 D[26:24, 21, 19:16] (Reset Configuration Override) ................................... 30-3

30.5 Memory Map and Registers.............................................................................. 30-3

30.5.1 Programming Model..................................................................................... 30-3

30.5.2 Memory Map ................................................................................................ 30-4

30.5.3 Register Descriptions.................................................................................... 30-5

30.6 Functional Description...................................................................................... 30-8

30.6.1 Reset Configuration ...................................................................................... 30-8

30.6.2 Chip Mode Selection .................................................................................. 30-10

30.6.3 Boot Device Selection ................................................................................ 30-11

30.6.4 Output Pad Strength Configuration ............................................................ 30-11

30.6.5 Clock Mode Selection................................................................................. 30-11

30.6.6 Chip Select Configuration .......................................................................... 30-12

30.7 Reset................................................................................................................ 30-12

30.8 Interrupts......................................................................................................... 30-12

Chapter 31

IEEE 1149.1 Test Access Port (JTAG)

31.1 Features............................................................................................................. 31-2

31.2 Modes of Operation .......................................................................................... 31-3

31.3 External Signal Description .............................................................................. 31-3

31.3.1 Detailed Signal Description.......................................................................... 31-3

31.4 Memory Map/Register Definition .................................................................... 31-5

31.4.1 Memory Map ................................................................................................ 31-5

31.4.2 Register Descriptions.................................................................................... 31-5

31.5 Functional Description...................................................................................... 31-7

31.5.1 JTAG Module ............................................................................................... 31-7

31.5.2 TAP Controller ............................................................................................. 31-7

31.5.3 JTAG Instructions......................................................................................... 31-8

31.6 Initialization/Application Information............................................................ 31-11

31.6.1 Restrictions ................................................................................................. 31-11

MOTOROLA Contents xxi

CONTENTS

Paragraph
Number

31.6.2 Nonscan Chain Operation........................................................................... 31-12

Title

Page

Number

Chapter 32

Mechanical Data

32.1 Pinout ................................................................................................................ 32-2

32.2 Ordering Information........................................................................................ 32-7

Chapter 33

Electrical Characteristics

33.1 Maximum Ratings............................................................................................. 33-1

33.2 Thermal Characteristics .................................................................................... 33-3

33.3 DC Electrical Specifications............................................................................. 33-4

33.4 Phase Lock Loop Electrical Specifications ...................................................... 33-6

33.5 QADC Electrical Characteristics ...................................................................... 33-7

33.6 Flash Memory Characteristics .......................................................................... 33-9

33.7 External Interface Timing Characteristics ...................................................... 33-10

33.8 Processor Bus Output Timing Specifications ................................................. 33-11

33.9 General Purpose I/O Timing........................................................................... 33-17

33.10 Reset and Configuration Override Timing ..................................................... 33-18

33.11 I2C Input/Output Timing Specifications......................................................... 33-19

33.12 Fast Ethernet AC Timing Specifications ........................................................ 33-20

33.12.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER,

and ERXCLK) ........................................................................................ 33-21

33.12.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK). 33-21

33.12.3 MII Async Inputs Signal Timing (ECRS and ECOL) ................................ 33-22

33.12.4 MII Serial Management Channel Timing (EMDIO and EMDC)............... 33-23

33.13 DMA Timer Module AC Timing Specifications............................................ 33-24

33.14 QSPI Electrical Specifications........................................................................ 33-24

33.15 JTAG and Boundary Scan Timing.................................................................. 33-25

33.16 Debug AC Timing Specifications................................................................... 33-27

Appendix A

Register Memory Map

xxii MCF5282 User’s Manual MOTOROLA

ILLUSTRATIONS

Figure
Number

1-1 MCF5282 Block Diagram ............................................................................................ 1-7

2-1 ColdFire Processor Core Pipelines ............................................................................... 2-1

2-2 User Programming Model ............................................................................................ 2-4

2-3 Condition Code Register (CCR) ................................................................................... 2-4

2-4 EMAC Register Set ...................................................................................................... 2-5

2-5 Supervisor Programming Model................................................................................... 2-6

2-6 Status Register ..............................................................................................................2-6

2-7 Exception Stack Frame Form ..................................................................................... 2-12

2-8 D0 Hardware Configuration Info................................................................................ 2-17

2-9 D1 Hardware Configuration Info................................................................................ 2-19

3-1 Multiply-Accumulate Functionality Diagram .............................................................. 3-2

3-2 Infinite Impulse Response (IIR) Filter.......................................................................... 3-3

3-3 Four-Tap FIR Filter ...................................................................................................... 3-3

3-4 Fractional Alignment .................................................................................................... 3-4

3-5 Signed and Unsigned Integer Alignment...................................................................... 3-4

3-6 EMAC Register Set ...................................................................................................... 3-6

3-7 MAC Status Register (MACSR)................................................................................... 3-6

3-8 EMAC-Specific OEP Sequence Stall ......................................................................... 3-13

3-9 Two’s Complement, Signed Fractional Equation....................................................... 3-14

4-1 Cache Block Diagram................................................................................................... 4-3

4-2 Cache Control Register (CACR) .................................................................................. 4-8

4-3 Access Control Registers (ACR0, ACR1).................................................................. 4-11

5-1 SRAM Base Address Register (RAMBAR)................................................................. 5-2

6-1 CFM Block Diagram .................................................................................................... 6-3

6-2 CFM Array Memory Map............................................................................................. 6-4

6-3 Flash Base Address Register (FLASHBAR) ................................................................ 6-7

6-4 CFM Module Configuration Register (CFMCR) ......................................................... 6-9

6-5 CFM Clock Divider Register (CFMCLKD)............................................................... 6-10

6-6 CFM Security Register (CFMSEC)............................................................................ 6-11

6-7 CFM Protection Register (CFMPROT)...................................................................... 6-12

6-8 CFMPROT Protection Diagram ................................................................................. 6-13

6-9 CFM Supervisor Access Register (CFMSACC) ........................................................ 6-13

6-10 CFM Data Access Register (CFMDACC).................................................................. 6-14

6-11 CFM User Status Register (CFMUSTAT) ................................................................. 6-15

6-12 CFM Command Register (CFMCMD)....................................................................... 6-16

6-13 Example Program Algorithm...................................................................................... 6-21

Title

Page

Number

MOTOROLA Illustrations xxiii

ILLUSTRATIONS

Figure
Number

7-1 Low-Power Interrupt Control Register (LPICR) ......................................................... 7-3

7-2 Low-Power Control Register (LPCR) ......................................................................... 7-4

8-1 IPS Base Address Register (IPSBAR).......................................................................... 8-4

8-2 Memory Base Address Register (RAMBAR) .............................................................. 8-5

8-3 Core Reset Status Register (CRSR)............................................................................. 8-6

8-4 Core Watchdog Control Register (CWCR) ................................................................. 8-8

8-5 Core Watchdog Service Register (CWSR).................................................................. 8-9

8-6 Arbiter Module Functions........................................................................................... 8-10

8-7 Default Bus Master Park Register (MPARK)............................................................. 8-12

8-8 Master Privilege Register (MPR) .............................................................................. 8-16

8-9 Peripheral Access Control Register (PACRn) ............................................................ 8-17

8-10 GPACR Register......................................................................................................... 8-18

9-1 Clock Module Block Diagram...................................................................................... 9-3

9-2 PLL Block Diagram...................................................................................................... 9-4

9-3 Synthesizer Control Register (SYNCR) ....................................................................... 9-6

9-4 Synthesizer Status Register (SYNSR) .......................................................................... 9-8

9-5 Crystal Oscillator Example......................................................................................... 9-12

9-6 Lock Detect Sequence ................................................................................................ 9-15

10-1 Interrupt Pending Register High (IPRHn) .................................................................. 10-7

10-2 Interrupt Pending Register Low (IPRLn) ................................................................... 10-7

10-3 Interrupt Mask Register High (IMRHn) ..................................................................... 10-8

10-4 Interrupt Mask Register Low (IMRLn) ...................................................................... 10-8

10-5 Interrupt Force Register High (INTFRCHn) .............................................................. 10-9

10-6 Interrupt Force Register Low (INTFRCLn) ............................................................. 10-10

10-7 Interrupt RequestLevel Register (IRLRn) ................................................................ 10-10

10-8 IACK Level and Priority Register (IACKLPRn) ..................................................... 10-11

10-9 Interrupt Control Register (ICRnx)........................................................................... 10-12

10-10 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)............... 10-16

11-1 EPORT Block Diagram .............................................................................................. 11-1

11-2 EPORT Pin Assignment Register (EPPAR)............................................................... 11-4

11-3 EPORT Data Direction Register (EPDDR) ................................................................ 11-4

11-4 EPORT Port Interrupt Enable Register (EPIER)........................................................ 11-5

11-5 EPORT Port Data Register (EPDR) ........................................................................... 11-5

11-6 EPORT Port Pin Data Register (EPPDR)................................................................... 11-6

11-7 EPORT Port Flag Register (EPFR) ............................................................................ 11-6

12-1 Connections for External Memory Port Sizes ............................................................ 12-4

12-2 Chip Select Address Registers (CSARn)................................................................... 12-6

12-3 Chip Select Mask Registers (CSMRn) ...................................................................... 12-7

12-4 Chip Select Control Registers (CSCRn)..................................................................... 12-8

13-1 Signal Relationship to CLKOUT for Non-DRAM Access ........................................ 13-2

13-2 Connections for External Memory Port Sizes ............................................................ 13-3

13-3 Chip-Select Module Output Timing Diagram ............................................................ 13-3

Title

Page

Number

xxiv MCF5282 User’s Manual MOTOROLA

ILLUSTRATIONS

Figure
Number

13-4 Data Transfer State Transition Diagram..................................................................... 13-5

13-5 Read Cycle Flowchart................................................................................................. 13-7

13-6 Basic Read Bus Cycle................................................................................................. 13-7

13-7 Write Cycle Flowchart................................................................................................ 13-8

13-8 Basic Write Bus Cycle................................................................................................ 13-8

13-9 Read Cycle with Fast Termination ............................................................................. 13-9

13-10 Write Cycle with Fast Termination ............................................................................ 13-9

13-11 Back-to-Back Bus Cycles ......................................................................................... 13-10

13-12 Line Read Burst (2-1-1-1), External Termination .................................................... 13-11

13-13 Line Read Burst (2-1-1-1), Internal Termination ..................................................... 13-12

13-14 Line Read Burst (3-2-2-2), External Termination .................................................... 13-12

13-15 Line Read Burst-Inhibited, Fast Termination, External Termination....................... 13-13

13-16 Line Write Burst (2-1-1-1), Internal/External Termination...................................... 13-13

13-17 Line Write Burst (3-2-2-2) with One Wait State ...................................................... 13-14

13-18 Line Write Burst-Inhibited........................................................................................ 13-14

13-19 Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 13-15

13-20 Example of a Misaligned Word Transfer (32-Bit Port)............................................ 13-15

14-1 MCF5282 Block Diagram with Signal Interfaces ...................................................... 14-2

15-1 Synchronous DRAM Controller Block Diagram........................................................ 15-2

15-2 DRAM Control Register (DCR) ................................................................................. 15-5

15-3 DRAM Address and Control Register (DACRn) ....................................................... 15-6

15-4 DRAM Controller Mask Registers (DMRn) .............................................................. 15-8

15-5 Connections for External Memory Port Sizes .......................................................... 15-13

15-6 Burst Read SDRAM Access ..................................................................................... 15-14

15-7 Burst Write SDRAM Access .................................................................................... 15-15

15-8 Auto-Refresh Operation............................................................................................ 15-16

15-9 Self-Refresh Operation ............................................................................................. 15-17

15-10 Mode Register Set (mrs) Command ......................................................................... 15-19

15-11 Initialization Values for DCR ................................................................................... 15-20

15-12 SDRAM Configuration............................................................................................. 15-21

15-13 DACR Register Configuration.................................................................................. 15-21

15-14 DMR0 Register ......................................................................................................... 15-22

16-1 DMA Signal Diagram................................................................................................. 16-2

16-2 DMA Request Control Register (DMAREQC) .......................................................... 16-3

16-3 Dual-Address Transfer................................................................................................ 16-4

16-4 Source Address Registers (SARn).............................................................................. 16-6

16-5 Destination Address Registers (DARn)...................................................................... 16-6

16-6 Byte Count Registers (BCRn)—BCR24BIT = 1........................................................ 16-7

16-7 Byte Count Registers (BCRn)—BCR24BIT = 0........................................................ 16-7

16-8 DMA Control Registers (DCRn) ................................................................................ 16-8

16-9 DMA Status Registers (DSRn) ................................................................................ 16-10

17-1 FEC Block Diagram.................................................................................................... 17-4

17-2 Ethernet Address Recognition—Receive Block Decisions ...................................... 17-12

Title

Page

Number

MOTOROLA Illustrations xxv

ILLUSTRATIONS

Figure
Number

17-3 Ethernet Address Recognitionq—Microcode Decisions .......................................... 17-13

17-4 Ethernet Interrupt Event Register (EIR) ................................................................... 17-24

17-5 Interrupt Mask Register (EIMR)............................................................................... 17-26

17-6 Receive Descriptor Active Register (RDAR)........................................................... 17-27

17-7 Transmit Descriptor Active Register (TDAR).......................................................... 17-28

17-8 Ethernet Control Register (ECR)............................................................................. 17-28

17-9 MII Management Frame Register (MMFR) ............................................................. 17-29

17-10 MII Speed Control Register (MSCR) ....................................................................... 17-31

17-11 MIB Control Register (MIBC) ................................................................................. 17-32

17-12 Receive Control Register (RCR) .............................................................................. 17-33

17-13 Transmit Control Register (TCR) ............................................................................. 17-34

17-14 Physical Address Low Register (PALR) .................................................................. 17-36

17-15 Physical Address High Register (PAUR) ................................................................. 17-36

17-16 Opcode/Pause Duration Register (OPD) .................................................................. 17-37

17-17 Descriptor Individual Upper Address Register (IAUR) ........................................... 17-38

17-18 Descriptor Individual Lower Address Register (IALR) ........................................... 17-38

17-19 Descriptor Group Upper Address Register (GAUR)................................................ 17-39

17-20 Descriptor Group Lower Address Register (GALR)................................................ 17-40

17-21 FIFO Transmit FIFO Watermark Register (TFWR)................................................. 17-40

17-22 FIFO Receive Bound Register (FRBR) .................................................................... 17-41

17-23 FIFO Receive Start Register (FRSR)........................................................................ 17-42

17-24 Receive Descriptor Ring Start Register (ERDSR) ................................................... 17-43

17-25 Transmit Buffer Descriptor Ring Start Register (ETDSR)....................................... 17-43

17-26 Receive Buffer Size Register (EMRBR) .................................................................. 17-44

17-27 Receive Buffer Descriptor (RxBD) .......................................................................... 17-47

17-28 Transmit Buffer Descriptor (TxBD) ......................................................................... 17-50

18-1 Watchdog Timer Block Diagram................................................................................ 18-2

18-2 Watchdog Control Register (WCR)............................................................................ 18-3

18-3 Watchdog Modulus Register (WMR)......................................................................... 18-4

18-4 Watchdog Count Register (WCNTR)......................................................................... 18-5

18-5 Watchdog Service Register (WSR) ............................................................................ 18-6

19-1 PIT Block Diagram..................................................................................................... 19-1

19-2 PIT Control and Status Register (PCSR).................................................................... 19-4

19-3 PIT Modulus Register (PMR)..................................................................................... 19-6

19-4 PIT Count Register (PCNTR)..................................................................................... 19-6

19-5 Counter Reloading from the Modulus Latch .............................................................. 19-7

19-6 Counter in Free-Running Mode.................................................................................. 19-7

20-1 GPT Block Diagram ................................................................................................... 20-2

20-2 GPT Input Capture/Output Compare Select Register (GPTIOS) ............................... 20-5

20-3 GPT Input Compare Force Register (GPCFORC) ..................................................... 20-6

20-4 GPT Output Compare 3 Mask Register (GPTOC3M)................................................ 20-6

20-5 GPT Output Compare 3 Data Register (GPTOC3D).................................................. 20-7

Title

Page

Number

xxvi MCF5282 User’s Manual MOTOROLA

ILLUSTRATIONS

Figure
Number

20-6 GPT Counter Register (GPTCNT) ............................................................................. 20-7

20-7 GPT System Control Register 1 (GPTSCR1)............................................................. 20-8

20-8 Fast Clear Flag Logic.................................................................................................. 20-9

20-9 GPT Toggle-On-Overflow Register (GPTTOV)........................................................ 20-9

20-10 GPT Control Register 1 (GPTCTL1).......................................................................... 20-9

20-11 GPT Control Register 2 (GPTCTL2)........................................................................ 20-10

20-12 GPT Interrupt Enable Register (GPTIE) .................................................................. 20-10

20-13 GPT System Control Register 2 (GPTSCR2)........................................................... 20-11

20-14 GPT Flag Register 1 (GPTFLG1)............................................................................. 20-12

20-15 GPT Flag Register 2 (GPTFLG2)............................................................................. 20-12

20-16 GPT Channel[0:3] Register (GPTCn)....................................................................... 20-13

20-17 Pulse Accumulator Control Register (GPTPACTL) ................................................ 20-13

20-18 Pulse Accumulator Flag Register (GPTPAFLG)...................................................... 20-14

20-19 Pulse Accumulator Counter Register (GPTPACNT) ............................................... 20-15

20-20 GPT Port Data Register (GPTPORT)....................................................................... 20-16

20-21 GPT Port Data Direction Register (GPTDDR)......................................................... 20-16

20-22 Channel 3 Output Compare/Pulse Accumulator Logic ............................................ 20-19

21-1 DMA Timer Block Diagram....................................................................................... 21-2

21-2 DTMRn Bit Definitions .............................................................................................. 21-4

21-3 DTXMRn Bit Definitions ........................................................................................... 21-5

21-4 DTERn Bit Definitions ............................................................................................... 21-6

21-5 DTRRn Bit Definitions............................................................................................... 21-7

21-6 DTCRn Bit Definitions............................................................................................... 21-8

21-7 DTCNn Bit Definitions............................................................................................... 21-8

22-1 QSPI Block Diagram .................................................................................................. 22-2

22-2 QSPI RAM Model ...................................................................................................... 22-5

22-3 QSPI Mode Register (QMR) .................................................................................... 22-10

22-4 QSPI Clocking and Data Transfer Example ............................................................. 22-11

22-5 QSPI Delay Register (QDLYR) ............................................................................... 22-11

22-6 QSPI Wrap Register (QWR)..................................................................................... 22-12

22-7 QSPI Interrupt Register (QIR).................................................................................. 22-13

22-8 QSPI Address Register ............................................................................................. 22-14

22-9 QSPI Data Register (QDR)....................................................................................... 22-14

22-10 Command RAM Registers (QCR0–QCR15)............................................................ 22-15

22-11 QSPI Timing ............................................................................................................. 22-16

23-1 Simplified Block Diagram .......................................................................................... 23-1

23-2 UART Mode Registers 1 (UMR1n)............................................................................ 23-4

23-3 UART Mode Register 2 (UMR2n) ............................................................................. 23-6

23-4 UART Status Register (USRn) ................................................................................... 23-7

23-5 UART Clock Select Register (UCSRn)...................................................................... 23-8

23-6 UART Command Register (UCRn)............................................................................ 23-9

23-7 UART Receive Buffer (URBn) ................................................................................ 23-11

23-8 UART Transmit Buffer (UTBn) ............................................................................... 23-12

Title

Page

Number

MOTOROLA Illustrations xxvii

ILLUSTRATIONS

Figure
Number

23-9 UART Input Port Change Register (UIPCRn) ......................................................... 23-12

23-10 UART Auxiliary Control Register (UACRn)........................................................... 23-13

23-11 UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 23-13

23-12 UART Baud Rate Generator Register (UBG1n) ...................................................... 23-14

23-13 UART Baud Rate Generator Register (UBG2n) ...................................................... 23-14

23-14 UART Input Port Register (UIPn) ............................................................................ 23-15

23-15 UART Output Port Command Registers (UOP1n/UOP0n) ..................................... 23-15

23-16 UART Block Diagram Showing External and Internal Interface Signals ................ 23-17

23-17 UART/RS-232 Interface ........................................................................................... 23-18

23-18 Clocking Source Diagram......................................................................................... 23-19

23-19 Transmitter and Receiver Functional Diagram......................................................... 23-20

23-20 Transmitter Timing Diagram ................................................................................... 23-22

23-21 Receiver Timing ....................................................................................................... 23-23

23-22 Automatic Echo ........................................................................................................ 23-25

23-23 Local Loop-Back ...................................................................................................... 23-25

23-24 Remote Loop-Back ................................................................................................... 23-26

23-25 Multidrop Mode Timing Diagram ............................................................................ 23-27

23-26 UART Mode Programming Flowchart ..................................................................... 23-31

24-1 I2C Module Block Diagram ....................................................................................... 24-2

24-2 I2C Standard Communication Protocol...................................................................... 24-3

24-3 Repeated START........................................................................................................ 24-4

24-4 Synchronized Clock SCL............................................................................................ 24-5

24-5 I2C Address Register (I2ADR)................................................................................... 24-6

24-6 I2C Frequency Divider Register (I2FDR) ................................................................. 24-7

24-7 I2C Control Register (I2CR)....................................................................................... 24-8

24-8 I2CR Status Register (I2SR) ...................................................................................... 24-9

24-9 I

24-10 Flow-Chart of Typical I2C Interrupt Routine........................................................... 24-15

25-1 FlexCAN Block Diagram and Pinout ........................................................................ 25-2

25-2 Typical CAN system................................................................................................... 25-4

25-3 Extended ID Message Buffer Structure ...................................................................... 25-5

25-4 Standard ID Message Buffer Structure....................................................................... 25-5

25-5 FlexCAN Memory Map.............................................................................................. 25-8

25-6 CAN Module Configuration Register (CANMCR).................................................. 25-20

25-7 FlexCAN Control Register 0 (CANCTRL0) ............................................................ 25-22

25-8 FlexCAN Control Register 1 (CANCTRL1) ............................................................ 25-23

25-9 Prescaler Divide Register (PRESDIV) ..................................................................... 25-24

25-10 FlexCAN Control Register 2 (CANCTRL2) ............................................................ 25-25

25-11 Free Running Timer (TIMER).................................................................................. 25-26

25-12 Rx Mask Registers (RXGMASK, RX14MASK, and RX15MASK) ....................... 25-27

25-13 FlexCAN Error and Status Register (ESTAT) ......................................................... 25-28

25-14 Interrupt Mask Register (IMASK)............................................................................ 25-30

2

C Data I/O Register (I2DR) .................................................................................. 24-10

Title

Page

Number

xxviii MCF5282 User’s Manual MOTOROLA

ILLUSTRATIONS

Figure
Number

25-15 Interrupt Flag Register (IFLAG)............................................................................... 25-31

25-16 FlexCAN Receive Error Counter (RXECTR) .......................................................... 25-32

25-17 FlexCAN Transmit Error Counter (TXECTR)......................................................... 25-32

26-1 MCF5282 Ports Module Block Diagram.................................................................... 26-2

26-2 Port Output Data Registers (8-bit) .............................................................................. 26-8

26-3 Port Output Data Register (7-bit)................................................................................ 26-8

26-4 Port Output Data Registers (6-bit) .............................................................................. 26-8

26-5 Port Output Data Registers (4-bit) .............................................................................. 26-9

26-6 Port Data Direction Registers (8-bit) .......................................................................... 26-9

26-7 Port Data Direction Register (7-bit).......................................................................... 26-10

26-8 Port Data Direction Registers (6-bit) ........................................................................ 26-10

26-9 Port Data Direction Registers (4-bit) ........................................................................ 26-10

26-10 Port Pin Data/Set Data Registers (8-bit) .................................................................. 26-11

26-11 Port Pin Data/Set Data Register (7-bit)..................................................................... 26-11

26-12 Port Pin Data/Set Data Registers (6-bit) ................................................................... 26-11

26-13 Port Pin Data/Set Data Registers (4-bit) ................................................................... 26-12

26-14 Port Clear Output Data Registers (8-bit) .................................................................. 26-12

26-15 Port Clear Output Data Register (7-bit).................................................................... 26-13

26-16 Port Clear Output Data Registers (6-bit) .................................................................. 26-13

26-17 Port Clear Output Data Registers (4-bit) .................................................................. 26-13

26-18 Port B/C/D Pin Assignment Register (PBCDPAR).................................................. 26-14

26-19 Port E Pin Assignment Register (PEPAR) ............................................................... 26-15

26-20 Port F Pin Assignment Register (PFPAR)................................................................ 26-17

26-21 Port J Pin Assignment Register (PJPAR) ................................................................ 26-18

26-22 Port SD Pin Assignment Register (PSDPAR) .......................................................... 26-19

26-23 Port AS Pin Assignment Register (PASPAR) .......................................................... 26-19

26-24 Port EH/EL Pin Assignment Register (PEHLPAR) ................................................ 26-20

26-25 Port QS Pin Assignment Register (PQSPAR) .......................................................... 26-21

26-26 Port TC Pin Assignment Register (PTCPAR) ......................................................... 26-22

26-27 Port TD Pin Assignment Register (PTDPAR)......................................................... 26-23

26-28 Port UA Pin Assignment Register (PUAPAR)........................................................ 26-24

26-29 Digital Input Timing ................................................................................................. 26-25

26-30 Digital Output Timing .............................................................................................. 26-26

27-1 QADC Block Diagram................................................................................................ 27-2

27-2 QADC Input and Output Signals ................................................................................ 27-5

27-3 QADC Module Configuration Register (QADCMCR) .............................................. 27-9

27-4 QADC Port QA Data Register (PORTQA) .............................................................. 27-10

27-5 QADC Port QB Data Register (PORTQB)............................................................... 27-10

27-6 QADC Port QA Data Direction Register (DDRQA)................................................ 27-11

27-7 Port QB Data Direction Register (DDRQB)............................................................. 27-11

27-8 QADC Control Register 0 (QACR0)........................................................................ 27-12

27-9 QADC Control Register 1 (QACR1)........................................................................ 27-14

27-10 QADC Control Register 2 (QACR2)........................................................................ 27-17

Title

Page

Number

MOTOROLA Illustrations xxix

ILLUSTRATIONS

Figure
Number

27-11 QADC Status Register 0 (QASR0)........................................................................... 27-22

27-12 Queue Status Transition............................................................................................ 27-25

27-13 QADC Status Register 1 (QASR1)........................................................................... 27-26

27-14 Conversion Command Word Table (CCW) ............................................................. 27-27

27-15 Right-Justified Unsigned Result Register (RJURR)................................................. 27-29

27-16 Left-Justified Signed Result Register (LJSRR) ........................................................ 27-30

27-17 Left-Justified Unsigned Result Register (LJURR) ................................................... 27-31

27-18 External Multiplexing Configuration........................................................................ 27-33

27-19 QADC Analog Subsystem Block Diagram .............................................................. 27-35

27-20 Conversion Timing ................................................................................................... 27-36

27-21 Bypass Mode Conversion Timing ............................................................................ 27-36

27-22 QADC Queue Operation with Pause ........................................................................ 27-39

27-23 CCW Priority Situation 1.......................................................................................... 27-41

27-24 CCW Priority Situation 2.......................................................................................... 27-42

27-25 CCW Priority Situation 3.......................................................................................... 27-42

27-26 CCW Priority Situation 4.......................................................................................... 27-43

27-27 CCW Priority Situation 5.......................................................................................... 27-43

27-28 CCW Priority Situation 6.......................................................................................... 27-44

27-29 CCW Priority Situation 7.......................................................................................... 27-44

27-30 CCW Priority Situation 8.......................................................................................... 27-45

27-31 CCW Priority Situation 9.......................................................................................... 27-45

27-32 CCW Priority Situation 10........................................................................................ 27-46

27-33 CCW Priority Situation 11........................................................................................ 27-46

27-34 CCW Freeze Situation 12 ......................................................................................... 27-47

27-35 CCW Freeze Situation 13 ......................................................................................... 27-47

27-36 CCW Freeze Situation 14 ......................................................................................... 27-47

27-37 . CCW Freeze Situation 15 ....................................................................................... 27-47

27-38 CCW Freeze Situation 16 ......................................................................................... 27-48

27-39 CCW Freeze Situation 17 ......................................................................................... 27-48

27-40 CCW Freeze Situation 18 ......................................................................................... 27-48

27-41 CCW Freeze Situation 19 ......................................................................................... 27-48

27-42 QADC Clock Subsystem Functions ......................................................................... 27-58

27-43 QADC Conversion Queue Operation ....................................................................... 27-60

27-44 Equivalent Analog Input Circuitry ........................................................................... 27-63

27-45 Errors Resulting from Clipping ................................................................................ 27-64

27-46 External Positive Edge Trigger Mode Timing with Pause ....................................... 27-65

27-47 Gated Mode, Single Scan Timing............................................................................. 27-66

27-48 Gated Mode, Continuous Scan Timing..................................................................... 27-67

27-49 Star-Ground at the Point of Power Supply Origin.................................................... 27-68

27-50 Input Signal Subjected to Negative Stress................................................................ 27-69

27-51 Input Signal Subjected to Positive Stress ................................................................. 27-70

27-52 External Multiplexing of Analog Signal Sources ..................................................... 27-72

Title

Page

Number

xxx MCF5282 User’s Manual MOTOROLA