Motorola MC9S12C, MC9S12GC User Manual
MC9S12C Family
Device User Guide
V01.05
Covers also
MC9S12GC Family
DOCUMENT NUMBER
9S12C128DGV1/D
Original Release Date: 25 JAN 2003
Revised: 11 FEBRUARY 2004
Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its
products forany particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in
different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the
Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses,
and reasonableattorney fees arising out of, directly or indirectly,any claim of personal injuryor death associated with such unintended or unauthorizeduse, even if such claim alleges
that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
©Motorola, Inc., 2002
1
Revision History
Device User Guide — 9S12C128DGV1/D V01.05
Version
Number
00.01 25.JAN.03 25.JAN.03 Original Version. Based on C32 user guide version 01.12
00.02 07.FEB.03 07.FEB.03
00.03 25.FEB.03 25.FEB.03
00.04 15.APR.03 15.APR03
00.05 05.MAY.03 05.MAY.03
00.06 21.MAY.03 21.MAY.03
01.00 15.JUL.03 15.JUL03
01.01 12.AUG.03 12.AUG.03 Updated PARTID listing due to C128 ECO revision
01.02 20.NOV.03 20.NOV.03
01.03 27.NOV.03 27.NOV.03
01.04 27.JAN.04 27.JAN.04
01.05 11.FEB.04 11.FEB.04
Revision
Date
Effective
Date
Author Description of Changes
Enhanced PortK description
Part number table revision in preface
QFP112 Emulation pinout correction
Enhanced part number explanation in preface
Reduced pseudo STOP current spec. for C64,C96,C128
Enhanced PortAD signal description
Corrected VDDR description in 2.4.2
Revised pin leakage in electrical parameters
SPI timing parameter table correction
Output drive high value reduced in 3V range
PE[4:2] Pull-Up spec out of reset changed
3V Expansion bus timing parameters not tested in production
Minimum bus frequency specification increased to 0.25MHz.
Parameter classification added to Appendix Table C-2.
IOH changed to 4mA for 3V range.
LVR level defined.for C32. Run IDD changed for C32.
Block guide reference table updated
Added PCB layout guide for Pierce oscillator configuration
IOL parameter updated in 3.3V range
Changed DOC number and CPU DOC reference number
Included separate C32 LVI levels
Changed PortM pull up reset state to enabled.
Added References to the CAN-less GC-Family
No major revision number increment, since silicon functionality is
not changed.
Added VDDX connection in PCB layout figures 8-1.to 8-6
Added Part ID for 2L45J mask set to Part ID table
Table A-4 VDD/VDDPLL min when supplied externally now 2.35V
Reference S12FTS128K1 in Preface (was S12FTS128K)
Reference to CPU Guide corrected to Version2
Corrected flash sector sizes for C-Family devices with >64K Flash
Corrected Preface Table 0-1 16K part listing to GC16 without CAN
Added PPAGE specifications to memory map diagrams
Added flash timing parameters for 1024 byte sector size
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Device User Guide — 9S12C128DGV1/D V01.05
Table of Contents
Section 1 Introduction
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.6 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Section 2 Signal Description
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2.1 Pin Initialization for 48 & 52 Pin LQFP bond-out versions . . . . . . . . . . . . . . . . . . 56
2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.3.3 TEST / VPP — Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.3.4 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin . . . . . . . 58
2.3.6 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 58
2.3.7 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 58
2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.3.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.10 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.11 PE4 / ECLK— Port E I/O Pin [4] / E-Clock Output. . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.12 PE3 / LSTRB — Port E I/O Pin [3] / Low-Byte Strobe (LSTRB). . . . . . . . . . . . . . 60
2.3.13 PE2 / R/W — Port E I/O Pin [2] / Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.14 PE1 / IRQ — Port E input Pin [1] / Maskable Interrupt Pin . . . . . . . . . . . . . . . . . 61
2.3.15 PE0 / XIRQ — Port E input Pin [0] / Non Maskable Interrupt Pin . . . . . . . . . . . . 61
2.3.16 PAD[7:0] / AN[7:0] — Port AD I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.17 PP[7] / KWP[7] — Port P I/O Pin [7]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.18 PP[6] / KWP[6]/ROMCTL — Port P I/O Pin [6] . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.19 PP[5:0] / KWP[5:0] / PW[5:0] — Port P I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . 62
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Device User Guide — 9S12C128DGV1/D V01.05
2.3.20 PJ[7:6] / KWJ[7:6] — Port J I/O Pins [7:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.21 PM5 / SCK — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.22 PM4 / MOSI — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.23 PM3 / SS — Port M I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.24 PM2 / MISO — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.25 PM1 / TXCAN — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.26 PM0 / RXCAN — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.27 PS[3:2] — Port S I/O Pins [3:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.28 PS1 / TXD — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.29 PS0 / RXD — Port S I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.30 PPT[7:5] / IOC[7:5] — Port T I/O Pins [7:5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.31 PT[4:0] / IOC[4:0] / PW[4:0]— Port T I/O Pins [4:0]. . . . . . . . . . . . . . . . . . . . . . . 63
2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers. . . . . . . . . . . . . . . . . . . . . 63
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
63
2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Pins. . . . . . . . . . . . . . . . . . 63
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 64
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 64
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL. . . . . . . . . . . . . . . . . . . . . . . . 64
Section 3 System Clock Description
Section 4 Modes of Operation
4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.4.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.4.2 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.4.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.4.4 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Section 5 Resets and Interrupts
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Device User Guide — 9S12C128DGV1/D V01.05
5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3.1 Reset Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3.2 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Section 6 HCS12 Core Block Description
6.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.1.1 PPAGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.1.2 BDM alternate clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.1.3 Extended Address Range Emulation Implications. . . . . . . . . . . . . . . . . . . . . . . . 71
Section 7 Voltage Regulator (VREG) Block Description
7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.1.1 VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.1.2 VDD1, VDD2, VSS1, VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Section 8 Recommended Printed Circuit Board Layout
Section 9 Clock Reset Generator (CRG) Block Description
9.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Section 10 Oscillator (OSC) Block Description
Section 11 Timer (TIM) Block Description
Section 12 Analog to Digital Converter (ATD) Block Description
12.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.1.1 VRL (voltage reference low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Section 13 Serial Communications Interface (SCI) Block Description
Section 14 Serial Peripheral Interface (SPI) Block Description
Section 15 Flash Block Description
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Device User Guide — 9S12C128DGV1/D V01.05
Section 16 RAM Block Description
Section 17 Pulse Width Modulator (PWM) Block Description
Section 18 MSCAN Block Description
Section 19 Port Integration Module (PIM) Block Description
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.1.2 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 87
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Appendix B Electrical Specifications
B.1 Voltage Regulator Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
B.2 Chip Power-up and LVI/LVR graphical explanation. . . . . . . . . . . . . . . . . . . . . . . . . 96
B.3 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
B.3.1 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
B.3.2 Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
B.4 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
B.4.1 ATD Operating Characteristics In 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
B.4.2 ATD Operating Characteristics In 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . 99
B.4.3 Factors influencing accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
B.4.4 ATD accuracy (5V Range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
B.4.5 ATD accuracy (3.3V Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
B.5 NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
B.5.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
B.5.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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B.6 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
B.6.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
B.6.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
B.6.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
B.7 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
B.8 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Appendix C Electrical Specifications
C.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
C.2 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
C.3 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
C.3.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Appendix D Package Information
D.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
D.2 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
D.3 52-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
D.4 48-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Appendix E Emulation Information
E.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
E.1.1 PK[2:0] / XADDR[16:14]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
E.2 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
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Device User Guide — 9S12C128DGV1/D V01.05
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Device User Guide — 9S12C128DGV1/D V01.05
List of Figures
Figure 0-1 Order Part number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 1-1 MC9S12C-Family Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map . . . . . . 29
Figure 1-3 MC9S12C96 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 1-4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map. . . . . . . . 31
Figure 1-5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map. . . . . . . . 32
Figure 1-6 MC9S12GC16 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . 33
Figure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family . . . . . . . . . . . . . . . . . . . . 52
Figure 2-2 Pin assignments in 52 LQFP for MC9S12C-Family. . . . . . . . . . . . . . . . . . . . 53
Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-Family . . . . . . . . . . . . . . . . . . .54
Figure 2-4 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 2-5 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 2-6 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 2-7 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 8-1 Recommended PCB Layout (48 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 8-2 Recommended PCB Layout (52 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 8-3 Recommended PCB Layout (80 QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator . . . . . . . . . . . . . 77
Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator . . . . . . . . . . . . . 78
Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . 79
Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . . 96
Figure B-2 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure B-3 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure B-4 Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure B-5 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure C-1 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure C-2 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure C-3 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure C-4 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure C-5 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B). . . . . . . . . . . . . . . . 128
Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03) . . . . . . . . . . . . 129
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Device User Guide — 9S12C128DGV1/D V01.05
Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F) . . . . . . 130
Figure 19-1 Pin Assignments in 112-pin LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Dimensions (case no. 841B)133
10
Device User Guide — 9S12C128DGV1/D V01.05
List of Tables
Table 0-2 MC9S12C-Family Package Option Summary . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 0-1 List of MC9S12C and MC9S12GC Family members. . . . . . . . . . . . . . . . . . . . 15
Table 0-3 MC9S12C-Family Part Number Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 0-4 MC9S12GC-Family Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 0-5 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 1-1 Device Register Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
$0000 - $000FMEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) 34
$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) 34
$0018 - $0018 Miscellaneous Peripherals (Device User Guide) 35
$0019 - $0019 VREG3V3 (Voltage Regulator) 35
$0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) 35
$0017 - $0017MMC map 2 of 4 (HCS12 Module Mapping Control) 35
$001A - $001B Miscellaneous Peripherals (Device User Guide) 35
$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, 36
Device User Guide) 36
$001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) 36
$001F - $001F INT map 2 of 2 (HCS12 Interrupt) 36
$0020 - $002F DBG (including BKP) map 1 of 1 (HCS12 Debug) 36
$0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control) 37
$0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) 37
$0034 - $003F CRG (Clock and Reset Generator) 37
$0040 - $006F TIM (Timer 16 Bit 8 Channels) 38
$0070 - $007F Reserved 40
$0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel) 40
$00A0 - $00C7 Reserved 41
$00D0 - $00D7 Reserved 42
$00C8 - $00CF SCI (Asynchronous Serial Interface) 42
$00D8 - $00DF SPI (Serial Peripheral Interface) 42
$00E0 - $00FF PWM (Pulse Width Modulator) 43
$0100 - $010F Flash Control Register 44
$0110 - $013F Reserved 45
$0140 - $017F CAN (Motorola Scalable CAN - MSCAN) 45
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . 46
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Device User Guide — 9S12C128DGV1/D V01.05
$0180 - $023F Reserved 47
$0240 - $027F PIM (Port Interface Module) 47
$0280 - $03FF Reserved space 50
Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 2-2 MC9S12C-Family Power and Ground Connection Summary . . . . . . . . . . . . . 64
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 5-2 Reset Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 6-1 Device Specific Flash PAGE Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 8-1 Recommended External Component Values. . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table A-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table A-3 ESD and Latch-Up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 86
Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table A-7 3.3V I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table A-8 Supply Current Characteristics for MC9S12C32 . . . . . . . . . . . . . . . . . . . . . . . 93
Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128 94
Table B-1 Voltage Regulator Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table B-2 Voltage Regulator - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table B-3 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table B-4 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table B-5 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table B-6 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table B-7 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table B-8 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table B-9 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table B-10 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Table B-11 Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table B-12 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table B-13 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table C-1 Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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Device User Guide — 9S12C128DGV1/D V01.05
Table C-2 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Table C-3 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Table C-4 Expanded Bus Timing Characteristics (5V Range). . . . . . . . . . . . . . . . . . . .124
Table C-5 Expanded Bus Timing Characteristics (3.3V Range) . . . . . . . . . . . . . . . . . .125
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Device User Guide — 9S12C128DGV1/D V01.05
14
Device User Guide — 9S12C128DGV1/D V01.05
Preface
TheDeviceUser Guide provides information about the MC9S12C-Family as well the MC9S12GC-Family
devices made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the
customer documentation. A completeset of device manualsalso includes the HCS12Core User Guide and
all the individual Block User Guides of the implemented modules. In an effort to reduce redundancy all
module specific information is located only in the respective Block User Guide. If applicable, special
implementation details of the module are given in the block description sections of this document.
The C-Family and the GC-Family offer an extensive range of package, temperature and speed options.
The members of the GC-Family do not feature a CAN module.
Table 0-1 shows a feature overview of the MC9S12C and MC9S12GC Family members.
Table 0-2 summarizes the package option and size configuration.
Table 0-3 lists the part number coding based on the package, speed and temperature and preliminary die
options for the C-Family.
Table 0-4 lists the part number coding based on the package, speed and temperature and preliminary die
options for the GC-Family.
Table 0-1 List of MC9S12C and MC9S12GC Family members
Flash RAM Device CAN SCI SPI A/D PWM Timer
128K 4K
96K 4K MC9S12C96 1 1 1 8ch 6ch 8ch
64K 4K
32K 2K
16K 1K MC9S12GC16 — 1 1 8ch 6ch 8ch
MC9S12C128 1 1 1 8ch 6ch 8ch
MC9S12GC128 — 1 1 8ch 6ch 8ch
MC9S12C64 1 1 1 8ch 6ch 8ch
MC9S12GC64 — 1 1 8ch 6ch 8ch
MC9S12C32 1 1 1 8ch 6ch 8ch
MC9S12GC32 — 1 1 8ch 6ch 8ch
Table 0-2 MC9S12C-Family Package Option Summary
1
Package Device Part Number
48LQFP MC9S12C128 MC9S12C128 0L09S M, V, C
52LQFP MC9S12C128 MC9S12C128 0L09S M, V, C 35
80QFP MC9S12C128 MC9S12C128 0L09S M, V, C 60
48LQFP MC9S12C96 MC9S12C96 TBD M, V, C
52LQFP MC9S12C96 MC9S12C96 TBD M, V, C 35
80QFP MC9S12C96 MC9S12C96 TBD M, V, C 60
Mask
set
Options
Temp.
2
Flash RAM
128K 4K
96K 4K
I/O3,
31
31
4
15
Device User Guide — 9S12C128DGV1/D V01.05
y
1
Package Device Part Number
48LQFP MC9S12C64 MC9S12C64 TBD M, V, C
52LQFP MC9S12C64 MC9S12C64 TBD M, V, C 35
80QFP MC9S12C64 MC9S12C64 TBD M, V, C 60
48LQFP MC9S12C32 MC9S12C32 1L45J M, V, C
52LQFP MC9S12C32 MC9S12C32 1L45J M, V, C 35
80QFP MC9S12C32 MC9S12C32 1L45J M, V, C 60
48LQFP MC9S12GC128 MC9S12GC128 0L09S M, V, C
52LQFP MC9S12GC128 MC9S12GC128 0L09S M, V, C 35
80QFP MC9S12GC128 MC9S12GC128 0L09S M, V, C 60
48LQFP MC9S12GC128 MC9S12GC64 TBD M, V, C
52LQFP MC9S12GC128 MC9S12GC64 TBD M, V, C 35
80QFP MC9S12GC128 MC9S12GC64 TBD M, V, C 60
48LQFP MC9S12GC32 MC9S12GC32 1L45J M, V, C
52LQFP MC9S12GC32 MC9S12GC32 1L45J M, V, C 35
80QFP MC9S12GC32 MC9S12GC32 1L45J M, V, C 60
48LQFP MC9S12GC16 MC9S12GC16 1L45J M, V, C
52LQFP MC9S12GC16 MC9S12GC16 1L45J M, V, C 35
80QFP MC9S12GC16 MC9S12GC16 1L45J M, V, C 60
NOTES:
1. Maskset dependent errata can be accessed at
http://e-www.motorola.com/wbapp/sps/site/prod_summary.jsp
2. C: T
3. All C-Family derivatives feature 1 CAN, 1 SCI, 1 SPI, an 8-channel A/D, a 6-channel PWM and an 8
4. I/O is the sum of ports capable to act as digital input or output.
= 85˚C, f = 25MHz. V: TA=105˚C, f = 25MHz. M: TA= 125˚C, f = 25MHz
A
channel timer. The GC-Family members do not have the CAN module
Mask
set
Options
Temp.
2
Flash RAM
64K 4K
32K 2K
128K 4K
64K 4K
32K 2K
16K 2K
I/O3,
31
31
31
31
31
31
4
MC9S12 C32 (P)C FU 25
Temperature Options
C = -40˚C to 85˚C
Speed Option
Package Option
Temperature Option
V = -40˚C to 105˚C
M = -40˚C to 125˚C
Package Options
FU = 80QFP
PB = 52LQFP
Preliminary Option
FA = 48LQFP
Speed Options
Device Title
25 = 25MHz bus
16 = 16MHz bus
Controller Famil
Figure 0-1 Order Part number Coding
Table 0-3 MC9S12C-Family Part Number Coding
Part Number
MC9S12C128CFA16 TBD -40˚C, 85˚C 48LQFP 16MHz C128 die
Mask
set
Temp. Package Speed Description
16
Device User Guide — 9S12C128DGV1/D V01.05
Part Number
MC9S12C128CPB16 TBD -40˚C, 85˚C 52LQFP 16MHz C128 die
MC9S12C128CFU16 TBD -40˚C, 85˚C 80QFP 16MHz C128 die
MC9S12C128VFA16 TBD -40˚C,105˚C 48LQFP 16MHz C128 die
MC9S12C128VPB16 TBD -40˚C,105˚C 52LQFP 16MHz C128 die
MC9S12C128VFU16 TBD -40˚C, 105˚C 80QFP 16MHz C128 die
MC9S12C128MFA16 TBD -40˚C,125˚C 48LQFP 16MHz C128 die
MC9S12C128MPB16 TBD -40˚C,125˚C 52LQFP 16MHz C128 die
MC9S12C128MFU16 TBD -40˚C, 125˚C 80QFP 16MHz C128 die
MC9S12C128CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz C128 die
MC9S12C128CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz C128 die
MC9S12C128CFU25 TBD -40˚C, 85˚C 80QFP 25MHz C128 die
MC9S12C128VFA25 TBD -40˚C,105˚C 48LQFP 25MHz C128 die
MC9S12C128VPB25 TBD -40˚C,105˚C 52LQFP 25MHz C128 die
MC9S12C128VFU25 TBD -40˚C, 105˚C 80QFP 25MHz C128 die
MC9S12C128MFA25 TBD -40˚C,125˚C 48LQFP 25MHz C128 die
MC9S12C128MPB25 TBD -40˚C,125˚C 52LQFP 25MHz C128 die
MC9S12C128MFU25 TBD -40˚C, 125˚C 80QFP 25MHz C128 die
MC9S12C96PCFA16 0L09S -40˚C, 85˚C 48LQFP 16MHz Preliminary C96 using C128 die
MC9S12C96PCPB16 0L09S -40˚C, 85˚C 52LQFP 16MHz Preliminary C96 using C128 die
MC9S12C96PCFU16 0L09S -40˚C, 85˚C 80QFP 16MHz Preliminary C96 using C128 die
MC9S12C96CFA16 TBD -40˚C, 85˚C 48LQFP 16MHz Final C96 using C96 die
MC9S12C96CPB16 TBD -40˚C, 85˚C 52LQFP 16MHz Final C96 using C96 die
MC9S12C96CFU16 TBD -40˚C, 85˚C 80QFP 16MHz Final C96 using C96 die
MC9S12C96PVFA16 0L09S -40˚C, 105˚C 48LQFP 16MHz Preliminary C96 using C128 die
MC9S12C96PVPB16 0L09S -40˚C, 105˚C 52LQFP 16MHz Preliminary C96 using C128 die
MC9S12C96PVFU16 0L09S -40˚C, 105˚C 80QFP 16MHz Preliminary C96 using C128 die
MC9S12C96VFA16 TBD -40˚C,105˚C 48LQFP 16MHz Final C96 using C96 die
MC9S12C96VPB16 TBD -40˚C,105˚C 52LQFP 16MHz Final C96 using C96die
MC9S12C96VFU16 TBD -40˚C, 105˚C 80QFP 16MHz Final C96 using C96 die
MC9S12C96PMFA16 0L09S -40˚C, 125˚C 48LQFP 16MHz Preliminary C96 using C128 die
MC9S12C96PMPB16 0L09S -40˚C, 125˚C 52LQFP 16MHz Preliminary C96 using C128 die
MC9S12C96PMFU16 0L09S -40˚C, 125˚C 80QFP 16MHz Preliminary C96 using C128 die
MC9S12C96MFA16 TBD -40˚C,125˚C 48LQFP 16MHz Final C96 using C96 die
MC9S12C96MPB16 TBD -40˚C,125˚C 52LQFP 16MHz Final C96 using C96 die
MC9S12C96MFU16 TBD -40˚C, 125˚C 80QFP 16MHz Final C96 using C96 die
MC9S12C96PCFA25 0L09S -40˚C, 85˚C 48LQFP 25MHz Preliminary C96 using C128 die
MC9S12C96PCPB25 0L09S -40˚C, 85˚C 52LQFP 25MHz Preliminary C96 using C128 die
MC9S12C96PCFU25 0L09S -40˚C, 85˚C 80QFP 25MHz Preliminary C96 using C128 die
MC9S12C96CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final C96 using C96 die
MC9S12C96CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final C96 using C96 die
MC9S12C96CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final C96 using C96 die
MC9S12C96PVFA25 0L09S -40˚C, 105˚C 48LQFP 25MHz Preliminary C96 using C128 die
MC9S12C96PVPB25 0L09S -40˚C, 105˚C 52LQFP 25MHz Preliminary C96 using C128 die
MC9S12C96PVFU25 0L09S -40˚C, 105˚C 80QFP 25MHz Preliminary C96 using C128 die
Mask
set
Temp. Package Speed Description
17
Device User Guide — 9S12C128DGV1/D V01.05
Part Number
MC9S12C96VFA25 TBD -40˚C,105˚C 48LQFP 25MHz Final C96 using C96 die
MC9S12C96VPB25 TBD -40˚C,105˚C 52LQFP 25MHz Final C96 using C96 die
MC9S12C96VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final C96 using C96 die
MC9S12C96PMFA25 0L09S -40˚C, 125˚C 48LQFP 25MHz Preliminary C96 using C128 die
MC9S12C96PMPB25 0L09S -40˚C, 125˚C 52LQFP 25MHz Preliminary C96 using C128 die
MC9S12C96PMFU25 0L09S -40˚C, 125˚C 80QFP 25MHz Preliminary C96 using C128 die
MC9S12C96MFA25 TBD -40˚C,125˚C 48LQFP 25MHz Final C96 using C96 die
MC9S12C96MPB25 TBD -40˚C,125˚C 52LQFP 25MHz Final C96 using C96 die
MC9S12C96MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final C96 using C96 die
MC9S12C64PCFA16 0L09S -40˚C, 85˚C 48LQFP 16MHz Preliminary C64 using C128 die
MC9S12C64PCPB16 0L09S -40˚C, 85˚C 52LQFP 16MHz Preliminary C64 using C128 die
MC9S12C64PCFU16 0L09S -40˚C, 85˚C 80QFP 16MHz Preliminary C64 using C128 die
MC9S12C64CFA16 TBD -40˚C, 85˚C 48LQFP 16MHz Final C64 using C64 die
MC9S12C64CPB16 TBD -40˚C, 85˚C 52LQFP 16MHz Final C64 using C64 die
MC9S12C64CFU16 TBD -40˚C, 85˚C 80QFP 16MHz Final C64 using C64 die
MC9S12C64PVFA16 0L09S -40˚C, 105˚C 48LQFP 16MHz Preliminary C64 using C128 die
MC9S12C64PVPB16 0L09S -40˚C, 105˚C 52LQFP 16MHz Preliminary C64 using C128 die
MC9S12C64PVFU16 0L09S -40˚C, 105˚C 80QFP 16MHz Preliminary C64 using C128 die
MC9S12C64VFA16 TBD -40˚C,105˚C 48LQFP 16MHz Final C64 using C64 die
MC9S12C64VPB16 TBD -40˚C,105˚C 52LQFP 16MHz Final C64 using C64 die
MC9S12C64VFU16 TBD -40˚C, 105˚C 80QFP 16MHz Final C64 using C64 die
MC9S12C64PMFA16 0L09S -40˚C, 125˚C 48LQFP 16MHz Preliminary C64 using C128 die
MC9S12C64PMPB16 0L09S -40˚C, 125˚C 52LQFP 16MHz Preliminary C64 using C128 die
MC9S12C64PMFU16 0L09S -40˚C, 125˚C 80QFP 16MHz Preliminary C64 using C128 die
MC9S12C64MFA16 TBD -40˚C,125˚C 48LQFP 16MHz Final C64 using C64 die
MC9S12C64MPB16 TBD -40˚C,125˚C 52LQFP 16MHz Final C64 using C64 die
MC9S12C64MFU16 TBD -40˚C, 125˚C 80QFP 16MHz Final C64 using C64 die
MC9S12C64PCFA25 0L09S -40˚C, 85˚C 48LQFP 25MHz Preliminary C64 using C128 die
MC9S12C64PCPB25 0L09S -40˚C, 85˚C 52LQFP 25MHz Preliminary C64 using C128 die
MC9S12C64PCFU25 0L09S -40˚C, 85˚C 80QFP 25MHz PreliminaryC64 using C128 die
MC9S12C64CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final C64 using C64 die
MC9S12C64CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final C64 using C64 die
MC9S12C64CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final C64 using C64 die
MC9S12C64PVFA25 0L09S -40˚C, 105˚C 48LQFP 25MHz Preliminary C64 using C128 die
MC9S12C64PVPB25 0L09S -40˚C, 105˚C 52LQFP 25MHz Preliminary C64 using C128 die
MC9S12C64PVFU25 0L09S -40˚C, 105˚C 80QFP 25MHz Preliminary C64 using C128 die
MC9S12C64VFA25 TBD -40˚C,105˚C 48LQFP 25MHz Final C64 using C64 die
MC9S12C64VPB25 TBD -40˚C,105˚C 52LQFP 25MHz Final C64 using C64 die
MC9S12C64VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final C64 using C64 die
MC9S12C64PMFA25 0L09S -40˚C, 125˚C 48LQFP 25MHz Preliminary C64 using C128 die
MC9S12C64PMPB25 0L09S -40˚C, 125˚C 52LQFP 25MHz Preliminary C64 using C128 die
MC9S12C64PMFU25 0L09S -40˚C, 125˚C 80QFP 25MHz Preliminary C64 using C128 die
MC9S12C64MFA25 TBD -40˚C,125˚C 48LQFP 25MHz Final C64 using C64 die
MC9S12C64MPB25 TBD -40˚C,125˚C 52LQFP 25MHz Final C64 using C64 die
Mask
set
Temp. Package Speed Description
18
Device User Guide — 9S12C128DGV1/D V01.05
Part Number
MC9S12C64MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final C64 using C64 die
MC9S12C32CFA16 1L45J -40˚C, 85˚C 48LQFP 16MHz C32 die
MC9S12C32CPB16 1L45J -40˚C, 85˚C 52LQFP 16MHz C32 die
MC9S12C32CFU16 1L45J -40˚C, 85˚C 80QFP 16MHz C32 die
MC9S12C32VFA16 1L45J -40˚C,105˚C 48LQFP 16MHz C32 die
MC9S12C32VPB16 1L45J -40˚C,105˚C 52LQFP 16MHz C32 die
MC9S12C32VFU16 1L45J -40˚C, 105˚C 80QFP 16MHz C32 die
MC9S12C32MFA16 1L45J -40˚C,125˚C 48LQFP 16MHz C32 die
MC9S12C32MPB16 1L45J -40˚C,125˚C 52LQFP 16MHz C32 die
MC9S12C32MFU16 1L45J -40˚C, 125˚C 80QFP 16MHz C32 die
MC9S12C32CFA25 1L45J -40˚C, 85˚C 48LQFP 25MHz C32 die
MC9S12C32CPB25 1L45J -40˚C, 85˚C 52LQFP 25MHz C32 die
MC9S12C32CFU25 1L45J -40˚C, 85˚C 80QFP 25MHz C32 die
MC9S12C32VFA25 1L45J -40˚C,105˚C 48LQFP 25MHz C32 die
MC9S12C32VPB25 1L45J -40˚C,105˚C 52LQFP 25MHz C32 die
MC9S12C32VFU25 1L45J -40˚C, 105˚C 80QFP 25MHz C32 die
MC9S12C32MFA25 1L45J -40˚C,125˚C 48LQFP 25MHz C32 die
MC9S12C32MPB25 1L45J -40˚C,125˚C 52LQFP 25MHz C32 die
MC9S12C32MFU25 1L45J -40˚C, 125˚C 80QFP 25MHz C32 die
Mask
set
Temp. Package Speed Description
Table 0-4 MC9S12GC-Family Part Number Coding
Part Number
MC9S12GC128PCFA25 0L09S -40˚C, 85˚C 48LQFP 25MHz Preliminary GC128 using C128 die
MC9S12GC128PCPB25 0L09S -40˚C, 85˚C 52LQFP 25MHz Preliminary GC128 using C128 die
MC9S12GC128PCFU25 0L09S -40˚C, 85˚C 80QFP 25MHz Preliminary GC128 using C128 die
MC9S12GC128CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final GC128 using GC128 die
MC9S12GC128CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final GC128 using GC128 die
MC9S12GC128CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final GC128 using GC128 die
MC9S12GC128PVFA25 0L09S -40˚C, 105˚C 48LQFP 25MHz Preliminary GC128 using C128 die
MC9S12GC128PVPB25 0L09S -40˚C, 105˚C 52LQFP 25MHz Preliminary GC128 using C128 die
MC9S12GC128PVFU25 0L09S -40˚C, 105˚C 80QFP 25MHz Preliminary GC128 using C128 die
MC9S12GC128VFA25 TBD -40˚C, 105˚C 48LQFP 25MHz Final GC128 using GC128 die
MC9S12GC128VPB25 TBD -40˚C, 105˚C 52LQFP 25MHz Final GC128 using GC128 die
MC9S12GC128VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final GC128 using GC128 die
MC9S12GC128PMFA25 0L09S -40˚C, 125˚C 48LQFP 25MHz Preliminary GC128 using C128 die
MC9S12GC128PMPB25 0L09S -40˚C, 125˚C 52LQFP 25MHz Preliminary GC128 using C128 die
MC9S12GC128PMFU25 0L09S -40˚C, 125˚C 80QFP 25MHz Preliminary GC128 using C128 die
MC9S12GC128MFA25 TBD -40˚C, 125˚C 48LQFP 25MHz Final GC128 using GC128 die
MC9S12GC128MPB25 TBD -40˚C, 125˚C 52LQFP 25MHz Final GC128 using GC128 die
MC9S12GC128MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final GC128 using GC128 die
MC9S12GC64PCFA25 0L09S -40˚C, 85˚C 48LQFP 25MHz Preliminary GC64 using C128 die
MC9S12GC64PCPB25 0L09S -40˚C, 85˚C 52LQFP 25MHz Preliminary GC64 using C128 die
MC9S12GC64PCFU25 0L09S -40˚C, 85˚C 80QFP 25MHz Preliminary GC64 using C128 die
Mask
set
Temp. Package Speed Description
19
Device User Guide — 9S12C128DGV1/D V01.05
Part Number
MC9S12GC64CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final GC64 using GC64 die
MC9S12GC64CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final GC64 using GC64 die
MC9S12GC64CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final GC64 using GC64 die
MC9S12GC64PVFA25 0L09S -40˚C, 105˚C 48LQFP 25MHz Preliminary GC64 using C128 die
MC9S12GC64PVPB25 0L09S -40˚C, 105˚C 52LQFP 25MHz Preliminary GC64 using C128 die
MC9S12GC64PVFU25 0L09S -40˚C, 105˚C 80QFP 25MHz Preliminary GC64 using C128 die
MC9S12GC64VFA25 TBD -40˚C, 105˚C 48LQFP 25MHz Final GC64 using GC64 die
MC9S12GC64VPB25 TBD -40˚C, 105˚C 52LQFP 25MHz Final GC64 using GC64 die
MC9S12GC64VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final GC64 using GC64 die
MC9S12GC64PMFA25 0L09S -40˚C, 125˚C 48LQFP 25MHz Preliminary GC64 using C128 die
MC9S12GC64PMPB25 0L09S -40˚C, 125˚C 52LQFP 25MHz Preliminary GC64 using C128 die
MC9S12GC64PMFU25 0L09S -40˚C, 125˚C 80QFP 25MHz Preliminary GC64 using C128 die
MC9S12GC64MFA25 TBD -40˚C, 125˚C 48LQFP 25MHz Final GC64 using GC64 die
MC9S12GC64MPB25 TBD -40˚C, 125˚C 52LQFP 25MHz Final GC64 using GC64 die
MC9S12GC64MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final GC64 using GC64 die
MC9S12GC32PCFA25 1L45J -40˚C, 85˚C 48LQFP 25MHz Preliminary GC32 using C32 die
MC9S12GC32PCPB25 1L45J -40˚C, 85˚C 52LQFP 25MHz Preliminary GC32 using C32 die
MC9S12GC32PCFU25 1L45J -40˚C, 85˚C 80QFP 25MHz Preliminary GC32 using C32 die
MC9S12GC32CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final GC32 using GC32 die
MC9S12GC32CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final GC32 using GC32 die
MC9S12GC32CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final GC32 using GC32 die
MC9S12GC32PVFA25 1L45J -40˚C,105˚C 48LQFP 25MHz Preliminary GC32 using C32 die
MC9S12GC32PVPB25 1L45J -40˚C,105˚C 52LQFP 25MHz Preliminary GC32 using C32 die
MC9S12GC32PVFU25 1L45J -40˚C, 105˚C 80QFP 25MHz Preliminary GC32 using C32 die
MC9S12GC32VFA25 TBD -40˚C,105˚C 48LQFP 25MHz Final GC32 using GC32 die
MC9S12GC32VPB25 TBD -40˚C,105˚C 52LQFP 25MHz Final GC32 using GC32 die
MC9S12GC32VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final GC32 using GC32 die
MC9S12GC32PMFA25 1L45J -40˚C,125˚C 48LQFP 25MHz Preliminary GC32 using C32 die
MC9S12GC32PMPB25 1L45J -40˚C,125˚C 52LQFP 25MHz Preliminary GC32 using C32 die
MC9S12GC32PMFU25 1L45J -40˚C, 125˚C 80QFP 25MHz Preliminary GC32 using C32 die
MC9S12GC32MFA25 TBD -40˚C,125˚C 48LQFP 25MHz Final GC32 using GC32 die
MC9S12GC32MPB25 TBD -40˚C,125˚C 52LQFP 25MHz Final GC32 using GC32 die
MC9S12GC32MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final GC32 using GC32 die
MC9S12GC16PCFA25 1L45J -40˚C, 85˚C 48LQFP 25MHz Preliminary GC16 using C32 die
MC9S12GC16PCPB25 1L45J -40˚C, 85˚C 52LQFP 25MHz Preliminary GC16 using C32 die
MC9S12GC16PCFU25 1L45J -40˚C, 85˚C 80QFP 25MHz Preliminary GC16 using C32 die
MC9S12GC16CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final GC16 using GC16 die
MC9S12GC16CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final GC16 using GC16 die
MC9S12GC16CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final GC16 using GC16 die
MC9S12GC16PVFA25 1L45J -40˚C,105˚C 48LQFP 25MHz Preliminary GC16 using C32 die
MC9S12GC16PVPB25 1L45J -40˚C,105˚C 52LQFP 25MHz Preliminary GC16 using C32 die
MC9S12GC16PVFU25 1L45J -40˚C, 105˚C 80QFP 25MHz Preliminary GC16 using C32 die
MC9S12GC16VFA25 TBD -40˚C,105˚C 48LQFP 25MHz Final GC16 using GC16 die
MC9S12GC16VPB25 TBD -40˚C,105˚C 52LQFP 25MHz Final GC16 using GC16 die
Mask
set
Temp. Package Speed Description
20
Device User Guide — 9S12C128DGV1/D V01.05
Part Number
MC9S12GC16VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final GC16 using GC16 die
MC9S12GC16PMFA25 1L45J -40˚C,125˚C 48LQFP 25MHz Preliminary GC16 using C32 die
MC9S12GC16PMPB25 1L45J -40˚C,125˚C 52LQFP 25MHz Preliminary GC16 using C32 die
MC9S12GC16PMFU25 1L45J -40˚C, 125˚C 80QFP 25MHz Preliminary GC16 using C32 die
MC9S12GC16MFA25 TBD -40˚C,125˚C 48LQFP 25MHz Final GC16 using GC16 die
MC9S12GC16MPB25 TBD -40˚C,125˚C 52LQFP 25MHz Final GC16 using GC16 die
MC9S12GC16MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final GC16 using GC16 die
Mask
set
Temp. Package Speed Description
Table 0-5 Document References
User Guide
HCS12 Background Debug (BDM) Block Guide V04 S12BDMV4/D
HCS12 Module Mapping Control (MMC) Block Guide V04 S12MMCV4/D
HCS12 Multiplexed External Bus Interface (MEBI) Block Guide V03 S12MEBIV3/D
Analog To Digital Converter: 10 Bit 8 Channel (ATD_10B8C) Block Guide V02 S12ATD10B8CV2/D
Clock and Reset Generator (CRG) Block Guide V04 S12CRGV4/D
Serial Communications Interface (SCI) Block Guide V02 S12SCIV2/D
Serial Peripheral Interface (SPI) Block Guide V03 S12SPIV3/D
Motorola Scalable CAN (MSCAN) Block Guide
Pulse Width Modulator: 8 bit, 6 channel (PWM_8B6C) Block Guide V01 S12PWM8B6V1/D
Timer: 16 bit, 8 channel (TIM_16B8C) Block Guide V01 S12TIM16B8CV1/D
Port Integration Module (PIM_9C32) Block Guide V01 S12C32PIMV1/D
32Kbyte Flash EEPROM (FTS32K) Block Guide V01 S12FTS32KV1/D
64Kbyte Flash EEPROM (FTS64K) Block Guide V01 S12FTS64KV1/D
128Kbyte Flash EEPROM (FTS128K1) Block Guide V01 S12FTS128K1V1/D
NOTES:
1. For the GC16 refer to the 16K flash, for the C32 and GC32 refer to the 32K flash, for the C64 and GC64 the 64K flash, for
the C96 the 96K flash and C128 the 128K flash document.
2. Not available on the GC-Family members
1
CPU12 Reference Manual V02 S12CPUV2/D
HCS12 Debug (DBG) Block Guide V01 S12DBGV1/D
HCS12 Interrupt (INT) Block Guide V01 S12INTV1/D
Voltage Regulator (VREG) Block Guide V02 S12VREG3V3V2/D
Oscillator (OSC) Block Guide V02 S12OSCV2/D
Version Document Order Number
2
V02 S12MSCANV2/D
Terminology
Acronyms and Abbreviations
New or invented terms, symbols, and notations
21
Device User Guide — 9S12C128DGV1/D V01.05
22
Device User Guide — 9S12C128DGV1/D V01.05
Section 1 Introduction
1.1 Overview
The MC9S12C-Family and the MC9S12GC-Family is a 48/52/80 pin Flash-based Industrial/Automotive
network control MCU family. Members of the MC9S12C-Family and the MC9S12GC-Family deliver the
power and flexibility of our 16 Bit core (CPU12) family to a whole new range of cost and space sensitive,
general purpose Industrial and Automotive network applications. All MC9S12C-Family and
MC9S12GC-Family members are comprised of standard on-chip peripherals including a 16-bit central
processing unit (CPU12), up to 128K bytes of Flash EEPROM, up to 4K bytes of RAM, an asynchronous
serial communications interface (SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer
module (TIM), a 6-channel 8-bit Pulse Width Modulator (PWM), an 8-channel, 10-bit analog-to-digital
converter (ADC). The MC9S12C-Family members also feature a CAN 2.0 A, B software compatible
module (MSCAN12). The MC9S12C-Family as well as the MC9S12GC-Family has full 16-bit data paths
throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to
suit operational requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O
port bits are available with Wake-Up capability from STOP or WAIT mode. The MC9S12C-Family and
the MC9S12GC-Family devices are available in 48, 52 and 80 pin QFP packages, with the 80 Pin version
pin compatible to the HCS12 A, B and D- Family derivatives.
1.2 Features
• 16-bit HCS12 CORE
– HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii.Instruction queue
iv.Enhanced indexed addressing
– MMC (memory map and interface)
– INT (interrupt control)
– BDM (background debug mode)
– DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer)
– MEBI: Multiplexed Expansion Bus Interface (available only in 80 pin package version)
• Wake-up interrupt inputs
– Up to 12-port bits available for wake up interrupt function with digital filtering
• Memory options
– 16K or 32KByte Flash EEPROM (erasable in 512-byte sectors)
64K, 96K or 128KByte Flash EEPROM (erasable in 1024-byte sectors)
23
Device User Guide — 9S12C128DGV1/D V01.05
– 1K, 2K or 4K Byte RAM
• Analog-to-Digital Converters
– One 8-channel module with 10-bit resolution.
– External conversion trigger capability
• Available on MC9S12C-Family:
One 1M bit per second, CAN 2.0 A, B software compatible module
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8x8bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
• Timer Module (TIM)
– 8-Channel Timer
– Each Channel Configurable as either Input Capture or Output Compare
– Simple PWM Mode
– Modulo Reset of Timer Counter
– 16-Bit Pulse Accumulator
– External Event Counting
– Gated Time Accumulation
• 6 PWM channels
– Programmable period and duty cycle
– 8-bit 6-channel or 16-bit 3-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
• Serial interfaces
– One asynchronous serial communications interface (SCI)
– One synchronous serial peripheral interface (SPI)
• CRG (Clock Reset Generator Module)
– Windowed COP watchdog,
– Real time interrupt,
– Clock monitor,
24
Device User Guide — 9S12C128DGV1/D V01.05
– Pierce or low current Colpitts oscillator
– Phase-locked loop clock frequency multiplier
– Limp home mode in absence of external clock
– Low power 0.5 to 16 MHz crystal oscillator reference clock
• Operating frequency
– 32MHz equivalent to 16MHz Bus Speed for single chip
– 32MHz equivalent to 16MHz Bus Speed in expanded bus modes
– Option of 9S12C-Family: 50MHz equivalent to 25MHz Bus Speed
– All 9S12GC-Family Members allow a 50MHz operting frequency.
• Internal 2.5V Regulator
– Supports an input voltage range from 2.97V to 5.5V
– Low power mode capability
– Includes low voltage reset (LVR) circuitry
– Includes low voltage interrupt (LVI) circuitry
• 48-Pin LQFP, 52-Pin LQFP or 80-Pin QFP package
– Up to 58 I/O lines with 5V input and drive capability (80 pin package)
– Up to 2 dedicated 5V input only lines (IRQ, XIRQ)
– 5V 8 A/D converter inputs and 5V I/O
• Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints
– Enhanced DBG12 debug features
1.3 Modes of Operation
User modes (Expanded modes are only available in the 80 pin package version).
• Normal and Emulation Operating Modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
• Special Operating Modes
25
Device User Guide — 9S12C128DGV1/D V01.05
– Special Single-Chip Mode with active Background Debug Mode
– Special Test Mode (Motorola use only)
– Special Peripheral Mode (Motorola use only)
• Low power modes
– Stop Mode
– Pseudo Stop Mode
– Wait Mode
26
1.4 Block Diagram
Figure 1-1 MC9S12C-Family Block Diagram
Device User Guide — 9S12C128DGV1/D V01.05
VSSR
VDDR
VDDX
VSSX
VDD2
VSS2
VDD1
VSS1
BKGD
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
TEST/VPP
Voltage Regulator
16K, 32K, 64K, 96K, 128K Byte Flash
1K, 2K, 4K Byte RAM
MODC
Background
Debug12 Module
Clock and
Reset
PLL
Generation
Module
PTE
DDRE
XIRQ
IRQ
W
R/
LSTRB/TAGLO
ECLK
MODA/IPIPE0
MODB/IPIPE1
NOACC/XCLKS
HCS12
CPU
COP Watchdog
Clock Monitor
Periodic Interrupt
System
Integration
Module
(SIM)
Multiplexed Address/Data Bus
DDRA DDRB
PTA PTB
PA4
PA3
PA2
PA7
PA6
PA5
PA0
PA1
PB7
PB6
PB5
PB4
PB3
ATD
Timer
Module
PWM
Module
SCI
MSCAN is not available on the
9S12GC Family Members
MSCAN
PB1
PB0
SPI
PB2
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
PW0
PW1
PW2
PW3
PW4
PW5
VDDA
VSSA
VRH
VRL
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
MUX
RXD
TXD
RXCAN
TXCAN
MISO
SS
MOSI
SCK
VDDA
VSSA
VRH
VRL
PAD0
PAD1
PAD2
PAD3
PAD4
PTAD
DDRAD
DDRT
DDRP
Keypad Interrupt
DDRJ
Key Int
DDRS
DDRM
PTT
PTP
PTJ
PTS
PTM
PAD5
PAD6
PAD7
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PJ6
PJ7
PS0
PS1
PS2
PS3
PM0
PM1
PM2
PM3
PM4
PM5
Multiplexed
Wide Bus
ADDR12
ADDR11
ADDR13
DATA12
DATA11
DATA13
ADDR10
DATA10
ADDR15
ADDR14
DATA15
DATA14
Internal Logic 2.5V
VDD1,2
VSS1,2
PLL 2.5V
VDDPLL
VSSPLL
ADDR8
ADDR9
DATA8
DAT A9
ADDR4
ADDR3
ADDR2
ADDR1
ADDR7
ADDR6
DAT A7
DAT A6
ADDR5
DATA4
DAT A5
ADDR0
DAT A3
DAT A2
DAT A1
DAT A0
I/O Driver 5V
VDDX
VSSX
A/D Converter 5V
VDDA
VSSA
Voltage Regulator 5V & I/O
VDDR
VSSR
Signals shown in Bold are not available on the 52 or 48 Pin Package
Signals shown in
VRL is bonded internally to VSSA
for 52 and 48 Pin packages
Bold Italic
are available in the 52, but not the 48 Pin Package
27
Device User Guide — 9S12C128DGV1/D V01.05
1.5 Device Memory Map
Table 1-1 shows the device register map of the MC9S12C-Family after reset. The following figures
(Figure 1-2, Figure 1-2, Figure 1-3 and Figure 1-4) illustrate the full device memory map with flash
and RAM.
Table 1-1 Device Register Map Overview
Address Module Size
$000 - $017 CORE (Ports A, B, E, Modes, Inits, Test) 24
$018 Reserved 1
$019 Voltage Regulator (VREG) 1
$01A - $01B Device ID register 2
$01C - $01F CORE (MEMSIZ, IRQ, HPRIO) 4
$020 - $02F CORE (DBG) 16
$030 - $033
$034 - $03F Clock and Reset Generator (CRG) 12
$040 - $06F Standard Timer Module16-bit 8-channels (TIM) 48
$070 - $07F Reserved 16
$080 - $09F Analog to Digital Convert (ATD) 32
$0A0 - $0C7 Reserved 40
$0C8 - $0CF Serial Communications Interface (SCI) 8
$0D0 - $0D7 Reserved 8
$0D8 - $0DF Serial Peripheral Interface (SPI) 8
$0E0 - $0FF Pulse Width Modulator 8-bit 6 channels (PWM) 32
$100 - $10F Flash Control Register 16
$110 - $13F Reserved 48
$140 - $17F
$180 - $23F Reserved 192
$240 - $27F Port Integration Module (PIM) 64
$280 - $3FF Reserved 384
NOTES:
1. External memory paging is not supported on this device (6.1.1 PPAGE).
2. Not available on MC9S12GC-Family Devices
CORE (PPAGE1)
Motorola Scalable CAN (MSCAN)
2
4
64
28
Device User Guide — 9S12C128DGV1/D V01.05
$0000
$0400
$3000
$4000
$8000
$C000
$FF00
$FFFF
VECTORS
NORMAL
SINGLE CHIP
EXT
VECTORS
EXPANDED SPECIAL
VECTORS
SINGLE CHIP
$0000
$03FF
$0000
$3FFF
$3000
$3FFF
$4000
$7FFF
$8000
$BFFF
$C000
$FFFF
$FF00
$FFFF
1K Register Space
Mappable to any 2K Boundary
16K Fixed Flash EEPROM
4K Bytes RAM
Mappable to any 4K Boundary
16K Fixed Flash EEPROM
16K Page Window
8 * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF)
Flash Erase Sector Size is 1024 Bytes
PAGE MAP
$3D
$3E
PPAGE
$3F
Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map
29
Device User Guide — 9S12C128DGV1/D V01.05
$0000
$0400
$3000
$4000
$8000
$C000
$FF00
$FFFF
VECTORS
NORMAL
SINGLE CHIP
EXT
VECTORS
EXPANDED SPECIAL
VECTORS
SINGLE CHIP
$0000
$03FF
$0000
$3FFF
$3000
$3FFF
$4000
$7FFF
$8000
$BFFF
$C000
$FFFF
$FF00
$FFFF
1K Register Space
Mappable to any 2K Boundary
16K Fixed Flash EEPROM
4K Bytes RAM
Mappable to any 4K Boundary
16K Fixed Flash EEPROM
16K Page Window
6 * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
BDM
(If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF)
Flash Erase Sector Size is 1024 Bytes
PAGE MAP
$3D
$3E
PPAGE
$3F
30
Figure 1-3 MC9S12C96 User Configurable Memory Map
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