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MC9S12A256
User Manual
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Motorola MC9S12DT256, MC9S12A256, MC9S12DJ256, MC9S12DG256 User Manual

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MC9S12DT256
Device User Guide
V03.07
Covers also
DOCUMENT NUMBER
9S12DT256DGV3/D
MC9S12A256, MC9S12DJ256
MC9S12DG256,
Original Release Date: 24 March 2003
Revised: 12 October 2005
Motorola, Inc
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,Buyershallindemnify andhold Motorolaand itsofficers, employees,subsidiaries, affiliates,and distributorsharmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly orindirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
1

Revision History

DOCUMENT NUMBER
9S12DT256DGV3/D
Version Number
V03.00
V03.01
V03.02
V03.03
V03.04
V03.05
V03.06
V03.07
Revision
Date
24 March
2003
30 June
2003
24 July
2003
26 July
2003
15 March
2004
4 April
2005
12 Oct
2005
02 Jan
2006
Effective
Date
Author Description of Changes
Initial version for Maskset L91N , based on MC9S12DP256B V02.11.
• added new HCS12 core documentation
• added cumulative program/erase cyclelimitation to Table A-12 for EEPROM
• updated Table 0-2 Document References
• removed cumulative program/erase cycle limitation from Table A-12 for EEPROM
• added LRAE generic load and execute info to section 15
• Added MC9S12DT256 in QFP 80 to Table 0-1
• Added Masksets 0L01Y and 4L91N
• Changed NVM data retention specification
Table A-12
• CorrectedFlashBurst ProgrammingTimeTable A-11,
• NVM Reliability Spec Table A-12,Figure A-2
• CorrectedFlashBurst ProgrammingTimeTable A-11,
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,Buyer shallindemnify andhold Motorolaand itsofficers, employees,subsidiaries, affiliates,and distributorsharmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly orindirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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MC9S12DT256 Device User Guide — 9S12DT256DGV3/D V03.07
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MC9S12DT256 Device User Guide — 9S12DT256DGV3/D V03.074MC9S12DT256 Device User Guide — V03.07
Table of Contents
Section 1 IntroductionMC9S12DT256
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.5 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.7 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Section 2 Signal Description
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.3 TEST — Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.4 VREGEN — Voltage Regulator Enable Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.5 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .57
2.3.7 PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . .57
2.3.8 PAD[14:08] / AN[14:08] — Port AD Input Pins of ATD1 . . . . . . . . . . . . . . . . . . . . . .57
2.3.9 PAD7 / AN07 / ETRIG0 — Port AD Input Pin of ATD0 . . . . . . . . . . . . . . . . . . . . . . .58
2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . .58
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .58
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.16 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.18 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.19 PE1 / IRQ — Port E Input Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.20 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
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MC9S12DT256 Device User Guide — V03.07
2.3.21 PH7 / KWH7 / SS2 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.22 PH6 / KWH6 / SCK2 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.23 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.24 PH4 / KWH4 / MISO2 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.25 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.26 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.27 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.28 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.29 PJ7 / KWJ7 / TXCAN4 / SCL — PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.30 PJ6 / KWJ6 / RXCAN4 / SDA — PORT J I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.31 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.32 PK7 / ECS / ROMONE — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.33 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.34 PM7 / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.35 PM6 / RXCAN4 — Port M I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.36 PM5 / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . .63
2.3.37 PM4 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4. . . . . . . . . . . . . . . . . . . . . .63
2.3.38 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.39 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2. . . . . . . . . . . . . . . . . . . . . .63
2.3.40 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.3.41 PM0 / RXCAN0 / RXB — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.3.42 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.3.43 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.3.44 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.3.45 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.3.46 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.3.47 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.3.48 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.3.49 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.3.50 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.3.51 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.3.52 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.3.53 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.3.54 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.3.55 PS2 / RXD1 — Port S I/O Pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.3.56 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
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MC9S12DT256 Device User Guide — V03.07
2.3.57 PS0 / RXD0 — Port S I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.3.58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers. . . . . . . . . . . . . . . . . . . . . . . .66
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator 66
2.4.3 VDD1, VDD2, VSS1, VSS2 — Core Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .67
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .67
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .67
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL. . . . . . . . . . . . . . . . . . . . . . . . . . .67
2.4.7 VREGEN — On Chip Voltage Regulator Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Section 3 System Clock Description
3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Section 4 Modes of Operation
4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.2 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.4.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.4.2 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.4.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.4.4 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Section 5 Resets and Interrupts
5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Section 6 HCS12 Core Block Description
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6.1 CPU12 Block Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.2 HCS12 Module Mapping Control (MMC) Block Description. . . . . . . . . . . . . . . . . . . . . .79
6.2.1 Device specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . . . .79
6.3.1 Device specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.4 HCS12 Interrupt (INT) Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.5 HCS12 Background Debug (BDM) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.6 HCS12 Breakpoint (BKP) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Section 7 Clock and Reset Generator (CRG) Block Description
7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Section 8 Enhanced Capture Timer (ECT) Block Description
Section 9 Analog to Digital Converter (ATD) Block Description
Section 10 Inter-IC Bus (IIC) Block Description
Section 11 Serial Communications Interface (SCI) Block Description
Section 12 Serial Peripheral Interface (SPI) Block Description
Section 13 J1850 (BDLC) Block Description
Section 14 Pulse Width Modulator (PWM) Block Description
Section 15 Flash EEPROM 256K Block Description
Section 16 EEPROM 4K Block Description
Section 17 RAM Block Description
Section 18 MSCAN Block Description
Section 19 Port Integration Module (PIM) Block Description
Section 20 Voltage Regulator (VREG) Block Description
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MC9S12DT256 Device User Guide — V03.07
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
A.1.2 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
A.2.3 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
A.3 NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
A.3.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
A.3.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
A.8.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Appendix B Package Information
B.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
B.2 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
B.3 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
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List of Figures
Figure 0-1 Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 1-1 MC9S12DT256 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 1-2 MC9S12DT256 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 2-1 Pin Assignments in 112-pin LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 2-2 Pin Assignments in 80-pin QFP for MC9S12DJ256 . . . . . . . . . . . . . . . . . . . . . .53
Figure 2-3 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 2-4 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 2-5 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 2-6 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 20-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator . . . . . . . . . . . . . . .84
Figure 20-2 Recommended PCB Layout for 80QFP Colpitts Oscillator . . . . . . . . . . . . . . . . .85
Figure 20-3 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .86
Figure 20-4 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . . . .87
Figure A-1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure A-2 Typical Endurance vs Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure A-3 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure A-4 Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure A-5 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure A-6 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure A-7 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure A-8 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure A-9 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure A-10 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure B-1 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 128
Figure B-2 80-pin QFP Mechanical Dimensions (case no. 841B). . . . . . . . . . . . . . . . . . . 129
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MC9S12DT256 Device User Guide — V03.07

List of Tables

Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 0-2 Document References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 0-3 Specification Change Summary for Maskset L91N . . . . . . . . . . . . . . . . . . . . . . . .17
Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . .43
Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 2-2 MC9S12DP256 Power and Ground Connection Summary. . . . . . . . . . . . . . . . . .67
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Table A-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Table A-3 ESD and Latch-Up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Table A-10 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Table A-12 NVM Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Table A-13 Voltage Regulator Recommended Load Capacitances . . . . . . . . . . . . . . . . . . .109
Table A-14 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table A-17 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table A-18 Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Table A-19 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Table A-20 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
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MC9S12DT256 Device User Guide — V03.07
Table A-21 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
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MC9S12DT256 Device User Guide — V03.07

Derivative Differences and Document References

Derivative Differences

Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the
compatibility within the MC9S12D-Family refer also to engineering bulletin EB386.

Table 0-1 Derivative Differences

Generic
device
# of CANs 0322
CAN0 — ✓✓✓ CAN1 — ✓ —— CAN4 — ✓✓✓
J1850/BDLC — — ✓ —
Package 112 LQFP/80 QFP 112 LQFP/80 QFP 112 LQFP/80 QFP 112 LQFP/80 QFP
Mask set L91N/L01Y L91N/L01Y L91N/L01Y L91N/L01Y
Temp Options C M, V, C M, V, C M, V, C
Package
Code
Notes
MC9S12A256 MC9S12DT256 MC9S12DJ256 MC9S12DG256
PV/FU PV/FU PV/FU PV/FU
An errata exists
contact Sales
Office
An errata exists
contact Sales
Office
An errata exists
contact Sales
Office
An errata exists
contact Sales
Office
The following figure provides an ordering number example for the MC9S12H-Family devices.
MC9S12 DT256 C FU
Package Option
Temperature Option
Temperature Options
C = -40˚C to 85˚C V = -40˚C to 105˚C M = -40˚C to 125˚C
Device Title
Package Options
Controller Family
FU = 80QFP PV = 112 LQFP

Figure 0-1 Order Partnumber Example

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MC9S12DT256 Device User Guide — V03.07
The following items should be considered when using a derivative (Table 0-1):
• Registers
– Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a
derivative without CAN0.
– Do not write or read CAN1registers (after reset: address range $0180 - $01BF), if using a
derivative without CAN1.
– Do not write or read CAN4 registers (after reset: address range $0280 - $02BF), if using a
derivative without CAN4.
– Do not write or read BDLC registers (after reset: address range $00E8 - $00EF), if using a
derivative without BDLC.
• Interrupts
– Fill the four CAN0 interrupt vectors ($FFB0 - $FFB7) according to your coding policies for
unused interrupts, if using a derivative without CAN0.
– Fill the four CAN1 interrupt vectors ($FFA8 - $FFAF) according to your coding policies for
unused interrupts, if using a derivative without CAN1.
– Fill the four CAN4 interrupt vectors ($FF90 - $FF97) according to your coding policies for
unused interrupts, if using a derivative without CAN4.
– Fill the BDLC interrupt vector ($FFC2, $FFC3) according to your coding policies for unused
interrupts, if using a derivative without BDLC.
• Ports
– The CAN0 pin functionality (TXCAN0, RXCAN0) is not available on port PJ7, PJ6, PM5,
PM4, PM3, PM2, PM1 and PM0, if using a derivative without CAN0.
– The CAN1 pin functionality (TXCAN1, RXCAN1) is not available on port PM3 and PM2, if
using a derivative without CAN1.
– The CAN4 pin functionality (TXCAN4, RXCAN4) is not available on port PJ7, PJ6, PM5,
PM7, PM6, PM5 and PM4, if using a derivative without CAN0.
– The BDLC pin functionality (TXB, RXB) is not available on port PM1 and PM0, if using a
derivative without BDLC.
– Do not write MODRR1 and MODRR0 bits of Module Routing Register (PIM_9DP256 Block
Guide), if using a derivative without CAN0.
– Do not write MODRR3 and MODRR2 bits of Module Routing Register (PIM_9DP256 Block
Guide), if using a derivative without CAN4.

Document References

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MC9S12DT256 Device User Guide — V03.07
The Device Guide provides information about the MC9S12DT256 device made up of standard HCS12 blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block Guides of the implemented modules. In a effort to reduce redundancy all module specific information is located only in the respective Block Guide. If applicable, special implementation details of the module are given in the block description sections of this document.
See Table 0-2 for names and versions of the referenced documents throughout the Device User Guide.

Table 0-2 Document References

User Guide Version Document Order Number
CPU12 Reference Manual V04 CPU12RM/AD
HCS12 Multiplexed External Bus Interface (MEBI) Block Guide V03 S12MEBIV3/D
HCS12 Module Mapping Control (MMC) Block Guide V04 S12MMCV4/D
HCS12 Interrupt (INT) Block Guide V01 S12INTV1/D
HCS12 Background Debug (BDM) Block Guide V04 S12BDMV4/D
HCS12 Breakpoint (BKP) Block Guide V01 S12BKPV1/D
Clock and Reset Generator (CRG) Block User Guide V04 S12CRGV4/D
Enhanced Capture Timer (ECT_16B8C) Block User Guide V01 S12ECT16B8CV1/D
Analog to Digital Converter 10 Bit 8 Channels (ATD_10B8C) Block User Guide V02 S12ATD10B8CV2/D
Inter IC Bus (IIC) Block User Guide V02 S12IICV2/D
Asynchronous Serial Interface (SCI) Block User Guide V02 S12SCIV2/D
Serial Peripheral Interface (SPI) Block User Guide V03 S12SPIV3/D
Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide V01 S12PWM8B8CV1/D
256 K Byte Flash (FTS256K) Block User Guide V03 S12FTS256KV3/D 4K Byte EEPROM (EETS4K) Block User Guide V02 S12EETS4KV2/D
Byte Level Data Link Controller -J1850 (BDLC) Block User Guide V01 S12BDLCV1/D
Motorola Scalable CAN (MSCAN) Block User Guide V02 S12MSCANV2/D
Voltage Regulator (VREG) Block User Guide V01 S12VREGV1/D
Port Integration Module (PIM_9DP256) Block User Guide V03 S12PIM9DP256V3/D
Oscillator (OSC) Block Guide V02 S12OSCV2/D
Table 0-3 shows the Specification Change Summary for Maskset L91N.
Table 0-3 Specification Change Summary for Maskset L91N
Block Spec Change
MCU_9DT256 removed CAN2 and CAN3
HCS12 V1.5
HCS12 V1.5
CRG Maskset includes an additional Pierce Oscillator
The Background Debug Module includes an Acknowledge Protocol (two
additional hardware commands ACK_ENABLE/ACK_DISABLE)
The state of PK7/ROMCTL is latched into ROMON Bit during RESET into
Emulation Mode or Normal Expanded Mode
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MC9S12DT256 Device User Guide — V03.07
Table 0-3 Specification Change Summary for Maskset L91N
Block Spec Change
EETS4K/FTS256K Reliability Specification for Non Volatile Memories
PIM_9DP256 CAN0 can be routed to PORTJ
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MC9S12DT256 Device User Guide — V03.07

Section 1 IntroductionMC9S12DT256

1.1 Overview

The MC9S12DT256 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit(HCS12 CPU), 256K bytes of Flash EEPROM, 12K bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit analog-to-digital converters(ADC),an 8-channel pulse-width modulator(PWM),a digital Byte Data Link Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital I/O lines with interrupt and wakeup capability, three CAN 2.0 A, B software compatible modules (MSCAN12), and an Inter-IC Bus. The MC9S12DT256 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements.

1.2 Features

• HCS12 Core – 16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer’s model identical to M68HC11 iii.Instruction queue
iv.Enhanced indexed addressing – MEBI (Multiplexed External Bus Interface) – MMC (Module Mapping Control) – INT (Interrupt control) – BKP (Breakpoints) – BDM (Background Debug Mode)
• CRG – Low current Colpitts or Pierce oscillator – PLL – COP watchdog – Real time interrupt – Clock Monitor
• 8-bit and 4-bit ports with interrupt functionality – Digital filtering
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MC9S12DT256 Device User Guide — V03.07
– Programmable rising or falling edge trigger
• Memory – 256K Flash EEPROM – 4K byte EEPROM – 12K byte RAM
• Two 8-channel Analog-to-Digital Converters – 10-bit resolution – External conversion trigger capability
• Three 1M bit per second, CAN 2.0 A, B software compatible modules – Five receive and three transmit buffers – Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit – Four separate interrupt channels for Rx, Tx, error and wake-up – Low-pass filter wake-up function – Loop-back for self test operation
• Enhanced Capture Timer – 16-bit main counter with 7-bit prescaler – 8 programmable input capture or output compare channels – Four 8-bit or two 16-bit pulse accumulators
• 8 PWM channels – Programmable period and duty cycle – 8-bit 8-channel or 16-bit 4-channel – Separate control for each pulse width and duty cycle – Center-aligned or left-aligned outputs – Programmable clock select logic with a wide range of frequencies – Fast emergency shutdown input – Usable as interrupt inputs
• Serial interfaces – Two asynchronous Serial Communications Interfaces (SCI) – Three Synchronous Serial Peripheral Interface (SPI)
• Byte Data Link Controller (BDLC) – SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible
for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications
• Inter-IC Bus (IIC)
20
– Compatible with I2C Bus standard – Multi-master operation – Software programmable for one of 256 different serial clock frequencies
• 112-Pin LQFP package – I/O lines with 5V input and drive capability – 5V A/D converter inputs – Operation at 50MHz equivalent to 25MHz Bus Speed – Development support – Single-wire background debug™ mode (BDM) – On-chip hardware breakpoints

1.3 Modes of Operation

User modes
MC9S12DT256 Device User Guide — V03.07
• Normal and Emulation Operating Modes – Normal Single-Chip Mode – Normal Expanded Wide Mode – Normal Expanded Narrow Mode – Emulation Expanded Wide Mode – Emulation Expanded Narrow Mode
• Special Operating Modes – Special Single-Chip Mode with active Background Debug Mode – Special Test Mode (Motorola use only) – Special Peripheral Mode (Motorola use only)
Low power modes
• Stop Mode
• Pseudo Stop Mode
• Wait Mode
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MC9S12DT256 Device User Guide — V03.07

1.4 Block Diagram

Figure 1-1 shows a block diagram of the MC9S12DT256 device.
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MC9S12DT256 Device User Guide — V03.07

Figure 1-1 MC9S12DT256 Block Diagram

VDDR VSSR
VREGEN
VDD1,2
VSS1,2
BKGD
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
RESET
PE0
PE1 PE2 PE3 PE4 PE5 PE6 PE7
TEST
Multiplexed Wide Bus
Multiplexed Narrow Bus
Internal Logic 2.5V
VDD1,2
VSS1,2
PLL 2.5V
VDDPLL
VSSPLL
256K Byte Flash EEPROM
12K Byte RAM
4K Byte EEPROM
Voltage Regulator
Single-wire Background
Debug Module
Clock and Reset
PLL
Generation Module
XIRQ IRQ
W
R/ LSTRB
DDRE
ECLK MODA MODB NOACC/
XCLKS
PTE
Multiplexed Address/Data Bus
DDRA DDRB
PTA PTB
PA4
PA3
PA2
PA1
ADDR11
ADDR10
ADDR9
DATA11
DATA10
DATA9
DATA3
DATA2
DATA1
PA0
ADDR8
DATA8
DATA0
PA7
PA6
PA5
ADDR15
ADDR14
ADDR13
DATA15
DATA14
DATA13
DATA7
DATA6
DATA5
ADDR12
DATA12
DATA4
I/O Driver 5V
VDDX
VSSX
A/D Converter 5V &
Voltage Regulator Reference
VDDA
VSSA
Voltage Regulator 5V & I/O
VDDR VSSR
CPU12
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
System
Integration
Module
(SIM)
PB4
PB6
PB5
ADDR6
ADDR5
DATA6
DATA5
PB3
ADDR4
ADDR3
DATA4
DATA3
PB7
ADDR7
DATA7
PB2
PB1
ADDR2
ADDR1
DATA2
DATA1
ATD0
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Enhanced Capture Timer
SCI0
SCI1
SPI0
BDLC (J1850)
CAN0
PB0
CAN1
ADDR0
CAN4
DATA0
IIC
PWM
SPI1
SPI2
VRH
VRL
VDDA
VSSA
PPAGE
MISO MOSI
SCK
RXB
TXB
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
SDA
SCL
PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
MISO MOSI
SCK
MISO MOSI
SCK
SS
SS
SS
AD0
ATD1
PAD00 PAD01 PAD02
PAD03 PAD04 PAD05 PAD06 PAD07
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
PIX0 PIX1 PIX2 PIX3 PIX4
PIX5
ECS
IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7
RXD
TXD
RXD
TXD
Module to Port Routing
KWJ0 KWJ1 KWJ6 KWJ7
KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7
KWH0 KWH1 KWH2
KWH3 KWH4 KWH5 KWH6 KWH7
VRH
VRL
VDDA
VSSA
DDRK
DDRT
DDRS
DDRM
DDRJ
DDRP
DDRH
AD1
PTK
PTT
PTS
PTM
PTJ
PTP
PTH
VRH VRL VDDA VSSA
PAD08 PAD09 PAD10
PAD11 PAD12 PAD13 PAD14 PAD15
PK0 PK1 PK2 PK3 PK4 PK5 PK7
PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7
PS0 PS1 PS2 PS3
PS4 PS5 PS6 PS7
PM0 PM1 PM2 PM3 PM4 PM5
PM6 PM7
PJ0 PJ1
PJ6 PJ7
PP0 PP1 PP2 PP3 PP4 PP5
PP6
PP7
PH0 PH1
PH2
PH3 PH4 PH5 PH6 PH7
XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19
ECS
Signals shown in Bold are not available on the 80 Pin Package
23
MC9S12DT256 Device User Guide — V03.07

1.5 Device Memory Map

Table1-1andFigure 1-2 showthedevice memory mapofthe MC9S12DT256afterreset. Note thatafter
reset the bottom 1k of the EEPROM ($0000 - $03FF) are hidden by the register space.

Table 1-1 Device Memory Map

Address Module
$0000 - $0017
$0018 - $0019 $001A - $001B $001C - $001F
$0020 - $0027
$0028 - $002F
$0030 - $0033
$0034 - $003F
$0040 - $007F
$0080 - $009F $00A0 - $00C7
$00C8 - $00CF $00D0 - $00D7 $00D8 - $00DF
$00E0 - $00E7
$00E8 - $00EF
$00F0 - $00F7 $00F8 - $00FF
$0100- $010F $0110 - $011B $011C - $011F
$0120 - $013F $0140 - $017F
$0180 - $01BF
$01C0 - $01FF Reserved 64
$0200 - $023F $0240 - $027F Port Integration Module (PIM) 64
$0280 - $02BF
$02C0 - $03FF
$0000 - $0FFF
CORE (Ports A, B, E, Modes, Inits, Test) Reserved Device ID register (PARTID) CORE (MEMSIZ, IRQ, HPRIO) Reserved CORE (Background Debug Mode) CORE (PPAGE, Port K) Clock and Reset Generator (PLL, RTI, COP) Enhanced Capture Timer 16-bit 8 channels Analog to Digital Converter 10-bit 8 channels (ATD0) Pulse Width Modulator 8-bit 8 channels (PWM) Serial Communications Interface (SCI0) Serial Communications Interface (SCI1) Serial Peripheral Interface (SPI0) Inter IC Bus Byte Data Link Controller (BDLC) Serial Peripheral Interface (SPI1) Serial Peripheral Interface (SPI2) Flash Control Register EEPROM Control Register Reserved Analog to Digital Converter 10-bit 8 channels (ATD1) Motorola Scalable Can (CAN0) Motorola Scalable Can (CAN1)
Reserved
Motorola Scalable Can (CAN4) Reserved EEPROM array
Size
(Bytes)
24
12 64 32 40
16 12
32 64 64
64
64
320
4096
2 2 4 8 8 4
8 8 8 8 8 8 8
4
24
MC9S12DT256 Device User Guide — V03.07
Table 1-1 Device Memory Map
Address Module
$1000 - $3FFF
$4000 - $7FFF
$8000 - $BFFF
$C000 - $FFFF
RAM array Fixed Flash EEPROM array
incl. 0.5K, 1K, 2K or 4K Protected Sector at start Flash EEPROM Page Window
Fixed Flash EEPROM array incl. 0.5K, 1K, 2K or 4K Protected Sector at end
and 256 bytes of Vector Space at $FF80 - $FFFF
Size
(Bytes)
12288
16384
16384
16384
25
MC9S12DT256 Device User Guide — V03.07

Figure 1-2 MC9S12DT256 Memory Map

$0000
$0400
$1000
$4000
$8000
EXTERN
$0000
$03FF $0000
$0FFF
$1000
$3FFF
$4000
$7FFF
$8000
REGISTERS
(Mappable to any 2k Block within the first 32K)
4K Bytes EEPROM
(Mappable to any 4K Block)
12K Bytes RAM
(Mappable to any 16K and alignable to top or bottom)
16K Fixed Flash Page $3E = 62
(This is dependant on the state of the ROMHM bit)
16K Page Window 16 x 16K Flash EEPROM pages
$C000
$FF00
$FFFF
VECTORS
EXPANDED*
* Assuming that a ‘0’ was driven onto port K bit 7 during MCU
is reset into normal expanded wide or narrow mode.
VECTORS
NORMAL
SINGLE CHIP
SINGLE CHIP
VECTORS
SPECIAL
$BFFF
$C000
16K Fixed Flash Page $3F = 63
$FFFF $FF00
BDM (if active)
$FFFF
26
MC9S12DT256 Device User Guide — V03.07

1.6 Detailed Register Map

The following tables show the detailed register map of the MC9S12DT256.
$0000 - $000F MEBI map 1 of 3 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
PORTA
PORTB
DDRA
DDRB
Reserved
Reserved
Reserved
Reserved
PORTE
DDRE
PEAR
MODE
PUCR
RDRIV
EBICTL
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0000000
Write:
Read: 00000000
Write:
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Bit 7 65432
Bit 7 6543Bit 2
NOACCE
MODC MODB MODA
PUPKE
RDPK
0
00
00
PIPOE NECLK LSTRE RDWE
PUPEE
RDPE
0
IVIS
00
00
0
PUPBE PUPAE
Bit 1 Bit 0
00
00
EMK EME
RDPB RDPA
ESTR
$0010 - $0014 MMC map 1 of 4 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0010
$0011
INITRM
INITRG
Read:
Write:
Read: 0
Write:
RAM15 RAM14 RAM13 RAM12 RAM11
REG14 REG13 REG12 REG11
00
000
RAMHAL
27
MC9S12DT256 Device User Guide — V03.07
$0010 - $0014 MMC map 1 of 4 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0012
$0013
$0014 Reserved
INITEE
MISC
Read: Write: Read: 0000 Write: Read: 00000000 Write:
EE15 EE14 EE13 EE12 EE11
EXSTR1 EXSTR0 ROMHM ROMON
00
$0015 - $0016 INT map 1 of 2 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0015
$0016
ITCR
ITEST
Read: 0 0 0
Write:
Read:
Write:
INTE INTC INTA INT8 INT6 INT4 INT2 INT0
WRINT ADR3 ADR2 ADR1 ADR0
$0017 - $0017 MMC map 2 of 4 (Core User Guide)
EEON
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0017 Reserved
Read: 00000000
Write:
$0018 - $001B Miscellaneous Peripherals (Device User Guide,Table 1-3)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0018
$0019
$001A
$001B
Reserved
Reserved
PARTIDH
PARTIDL
Read: 00000000
Write:
Read: 00000000
Write:
Read: ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
Write:
Read: ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Write:
$001C - $001D MMC map 3 of 4 (Core and Device User Guide,Table 1-4)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $001C
$001D
MEMSIZ0
MEMSIZ1
Read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0
Write:
Read: rom_sw1 rom_sw0 0000pag_sw1 pag_sw0
Write:
28
MC9S12DT256 Device User Guide — V03.07
$001E - $001E MEBI map 2 of 3 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $001E
INTCR
Read:
Write:
IRQE IRQEN
000000
$001F - $001F INT map 2 of 2 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $001F
HPRIO
Read:
Write:
PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
0
$0020 - $0027 Reserved
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read 00000000
Write:
$0028 - $002F BKP (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0028
$0029
$002A
$002B
$002C
BKPCT0
BKPCT1
BKP0X
BKP0H
BKP0L
Read:
Write:
Read:
Write:
Read: 0 0
Write:
Read:
Write:
Read:
Write:
BKEN BKFULL BKBDM BKTAG
BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW
BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
0000
29
MC9S12DT256 Device User Guide — V03.07
$0028 - $002F BKP (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $002D
$002E
$002F
BKP1X
BKP1H
BKP1L
Read: 0 0
Write:
Read:
Write:
Read:
Write:
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0
$0030 - $0031 MMC map 4 of 4 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0030
$0031
PPAGE
Reserved
Read: 0 0
Write:
Read: 00000000
Write:
PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
$0032 - $0033 MEBI map 3 of 3 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0032
$0033
PORTK
DDRK
Read: Write: Read: Write:
Bit 7 654321Bit 0
Bit 7 654321Bit 0
$0034 - $003F CRG (Clock and Reset Generator)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
SYNR
REFDV CTFLG
TEST ONLY
CRGFLG
CRGINT
CLKSEL
PLLCTL
RTICTL
COPCTL
Read: 0 0
Write:
Read: 0000
Write:
Read: TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0
Write:
Read:
Write:
RTIF PROF
RTIE
PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI
CME PLLON AUTO ACQ
WCOP RSBCK
00
RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
REFDV3 REFDV2 REFDV1 REFDV0
0
000
LOCKIF
LOCKIE
LOCK TRACK
00
0
PRE PCE SCME
CR2 CR1 CR0
SCMIF
SCMIE
SCM
0
30
MC9S12DT256 Device User Guide — V03.07
$0034 - $003F CRG (Clock and Reset Generator)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $003D
$003E
$003F
FORBYP
TEST ONLY
CTCTL
TEST ONLY
ARMCOP
Read:
Write:
Read: TCTL7 TCTL6 TCTL5 TCTL4 TCLT3 TCTL2 TCTL1 TCTL0
Write:
Read: 00000000
Write: Bit 7 654321Bit 0
RTIBYP COPBYP
0
PLLBYP
00
FCM
0
$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0040
$0041
$0042
$0043
$0044
$0045
$0046
$0047
$0048
$0049
$004A
$004B
$004C
$004D
$004E
$004F
$0050
$0051
$0052
TIOS
CFORC
OC7M
OC7D
TCNT (hi)
TCNT (lo)
TSCR1
TTOV
TCTL1
TCTL2
TCTL3
TCTL4
TIE
TSCR2
TFLG1
TFLG2
TC0 (hi)
TC0 (lo)
TC1 (hi)
Read:
Write:
Read: 00000000
Write: FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
Read:
Write:
Read:
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read: Bit 7 654321Bit 0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
TEN TSWAI TSFRZ TFFCA
TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4
OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
C7I C6I C5I C4I C3I C2I C1I C0I
TOI
C7F C6F C5F C4F C3F C2F C1F C0F
TOF
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
000
0000000
0000
TCRE PR2 PR1 PR0
31
MC9S12DT256 Device User Guide — V03.07
$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0053
$0054
$0055
$0056
$0057
$0058
$0059
$005A
$005B
$005C
$005D
$005E
$005F
$0060
$0061
$0062
$0063
$0064
$0065
$0066
$0067
$0068
$0069
$006A
$006B
TC1 (lo)
TC2 (hi)
TC2 (lo)
TC3 (hi)
TC3 (lo)
TC4 (hi)
TC4 (lo)
TC5 (hi)
TC5 (lo)
TC6 (hi)
TC6 (lo)
TC7 (hi)
TC7 (lo)
PACTL
PAFLG
PACN3 (hi)
PACN2 (lo)
PACN1 (hi)
PACN0 (lo)
MCCTL
MCFLG
ICPAR
DLYCT
ICOVW
ICSYS
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0
Write:
Read: 000000
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write: ICLAT FLMC
Read:
Write:
Read: 0000
Write:
Read: 000000
Write:
Read:
Write:
Read:
Write:
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
PAOVF PAIF
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Bit 7 654321Bit 0
MCZI MODMC RDMCL
MCZF
NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0
SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ
0 0 0 POLF3 POLF2 POLF1 POLF0
00
PA3EN PA2EN PA1EN PA0EN
MCEN MCPR1 MCPR0
DLY1 DLY0
32
MC9S12DT256 Device User Guide — V03.07
$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $006C
$006D
$006E
$006F
$0070
$0071
$0072
$0073
$0074
$0075
$0076
$0077
$0078
$0079
$007A
$007B
$007C
$007D
$007E
$007F
Reserved
TIMTST
Test Only
Reserved
Reserved
PBCTL
PBFLG
PA3H
PA2H
PA1H
PA0H
MCCNT (hi)
MCCNT (lo)
TC0H (hi)
TC0H (lo)
TC1H (hi)
TC1H (lo)
TC2H (hi)
TC2H (lo)
TC3H (hi)
TC3H (lo)
Read:
Write:
Read: 000000
Write:
Read:
Write:
Read:
Write:
Read: 0
Write:
Read: 000000
Write:
Read: Bit 7 654321Bit 0
Write:
Read: Bit 7 654321Bit 0
Write:
Read: Bit 7 654321Bit 0
Write:
Read: Bit 7 654321Bit 0
Write:
Read:
Write:
Read:
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read: Bit 7 654321Bit 0
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read: Bit 7 654321Bit 0
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read: Bit 7 654321Bit 0
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read: Bit 7 654321Bit 0
Write:
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
PBEN
0000
TCBYP
PBOVI
PBOVF
0
0
0
$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0080
$0081
ATD0CTL0
ATD0CTL1
Read: 00000000
Write:
Read: 00000000
Write:
33
MC9S12DT256 Device User Guide — V03.07
$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0082
$0083
$0084
$0085
$0086
$0087
$0088
$0089
$008A
$008B
$008C
$008D
$008E
$008F
$0090
$0091
$0092
$0093
$0094
$0095
$0096
$0097
$0098
$0099
$009A
ATD0CTL2
ATD0CTL3
ATD0CTL4
ATD0CTL5
ATD0STAT0
Reserved
ATD0TEST0
ATD0TEST1
Reserved
ATD0STAT1
Reserved
ATD0DIEN
Reserved
PORTAD0
ATD0DR0H
ATD0DR0L
ATD0DR1H
ATD0DR1L
ATD0DR2H
ATD0DR2L
ATD0DR3H
ATD0DR3L
ATD0DR4H
ATD0DR4L
ATD0DR5H
Read:
Write:
Read: 0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 0000000
Write:
Read: 00000000
Write:
Read: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
Write:
Read: 00000000
Write:
Read:
Write:
Read: 00000000
Write:
Read: Bit7 654321BIT 0
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
ADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE
S8C S4C S2C S1C FIFO FRZ1 FRZ0
SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
DJM DSGN SCAN MULT
SCF
Bit 7 654321Bit 0
0
ETORF FIFOR
0
0 CC2 CC1 CC0
CC CB CA
ASCIF
SC
34
MC9S12DT256 Device User Guide — V03.07
$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $009B
$009C
$009D
$009E
$009F
ATD0DR5L
ATD0DR6H
ATD0DR6L
ATD0DR7H
ATD0DR7L
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $00A0
$00A1
$00A2
$00A3
$00A4
$00A5
$00A6
$00A7
$00A8
$00A9
$00AA
$00AB
$00AC
$00AD
$00AE
$00AF
$00B0
PWME
PWMPOL
PWMCLK
PWMPRCLK
PWMCAE
PWMCTL PWMTST
Test Only
PWMPRSC
PWMSCLA
PWMSCLB
PWMSCNTA
PWMSCNTB
PWMCNT0
PWMCNT1
PWMCNT2
PWMCNT3
PWMCNT4
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0
Write:
Read:
Write:
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read:
Write:
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
PCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
PCKB2 PCKB1 PCKB0
CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
CON67 CON45 CON23 CON01 PSWAI PFRZ
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
0
PCKA2 PCKA1 PCKA0
00
35
MC9S12DT256 Device User Guide — V03.07
$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $00B1
$00B2
$00B3
$00B4
$00B5
$00B6
$00B7
$00B8
$00B9
$00BA
$00BB
$00BC
$00BD
$00BE
$00BF
$00C0
$00C1
$00C2
$00C3
$00C4
$00C5
$00C6
$00C7
PWMCNT5
PWMCNT6
PWMCNT7
PWMPER0
PWMPER1
PWMPER2
PWMPER3
PWMPER4
PWMPER5
PWMPER6
PWMPER7
PWMDTY0
PWMDTY1
PWMDTY2
PWMDTY3
PWMDTY4
PWMDTY5
PWMDTY6
PWMDTY7
PWMSDN
Reserved
Reserved
Reserved
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
PWMIF PWMIE
PWMRS
TRT
PWMLVL
0
PWM7IN
PWM7INLPWM7E
NA
36
MC9S12DT256 Device User Guide — V03.07
$00C8 - $00CF SCI0 (Asynchronous Serial Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $00C8
$00C9
$00CA
$00CB
$00CC
$00CD
$00CE
$00CF
SCI0BDH
SCI0BDL
SCI0CR1
SCI0CR2
SCI0SR1
SCI0SR2
SCI0DRH
SCI0DRL
Read: 0 0 0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: TDRE TC RDRF IDLE OR NF FE PF
Write:
Read: 00000
Write:
Read: R8
Write:
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
LOOPS SCISWAI RSRC M WAKE ILT PE PT
TIE TCIE RIE ILIE TE RE RWU SBK
T8
000000
SBR12 SBR11 SBR10 SBR9 SBR8
BRK13 TXDIR
RAF
$00D0 - $00D7 SCI1 (Asynchronous Serial Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $00D0
$00D1
$00D2
$00D3
$00D4
$00D5
$00D6
$00D7
SCI1BDH
SCI1BDL
SCI1CR1
SCI1CR2
SCI1SR1
SCI1SR2
SCI1DRH
SCI1DRL
Read: 0 0 0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: TDRE TC RDRF IDLE OR NF FE PF
Write:
Read: 00000
Write:
Read: R8
Write:
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
LOOPS SCISWAI RSRC M WAKE ILT PE PT
TIE TCIE RIE ILIE TE RE RWU SBK
T8
000000
SBR12 SBR11 SBR10 SBR9 SBR8
BRK13 TXDIR
RAF
$00D8 - $00DF SPI0 (Serial Peripheral Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $00D8
$00D9
$00DA
$00DB
SPI0CR1
SPI0CR2
SPI0BR
SPI0SR
Read:
Write:
Read: 0 0 0
Write:
Read: 0
Write:
Read: SPIF 0 SPTEF MODF 0000
Write:
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
MODFEN BIDIROE
SPPR2 SPPR1 SPPR0
0
0
SPISWAI SPC0
SPR2 SPR1 SPR0
37
MC9S12DT256 Device User Guide — V03.07
$00D8 - $00DF SPI0 (Serial Peripheral Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $00DC
$00DD
$00DE
$00DF
Reserved
SPI0DR
Reserved
Reserved
Read: 00000000
Write:
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Bit7 654321Bit0
$00E0 - $00E7 IIC (Inter IC Bus)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $00E0
$00E1
$00E2
$00E3
$00E4
$00E5
$00E6
$00E7
IBAD
IBFD
IBCR
IBSR
IBDR
Reserved
Reserved
Reserved
Read:
Write:
Read:
Write:
Read:
Write: RSTA
Read: TCF IAAS IBB
Write:
Read:
Write:
Read: 0 0 0 0 0 0 0 0
Write:
Read: 00000000
Write:
Read: 00000000
Write:
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0
IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
IBEN IBIE MS/
D7 D6 D5 D4 D3 D2 D1 D 0
SL TX/RX TXAK
IBAL
0SRW
00
IBIF
IBSWAI
RXAK
$00E8 - $00EF BDLC (Bytelevel Data Link Controller J1850)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
38
$00E8
$00E9
$00EA
$00EB
$00EC
$00ED
$00EE
$00EF
DLCBCR1
DLCBSVR
DLCBCR2
DLCBDR
DLCBARD
DLCBRSR
DLCSCR
DLCBSTAT
Read:
Write:
Read: 0 0 I3 I2 I1 I0 0 0
Write:
Read:
Write:
Read:
Write:
Read: 0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
IMSG CLKS
SMRST DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0
D7 D6 D5 D4 D3 D2 D1 D0
RXPOL
0 0
0 0 0
0 0 0 0 0 0 0 IDLE
0000
00
R5 R4 R3 R2 R1 R0
BDLCE
BO3 BO2 BO1 BO0
0 0 0 0
IE WCM
MC9S12DT256 Device User Guide — V03.07
$00F0 - $00F7 SPI1 (Serial Peripheral Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $00F0
$00F1
$00F2
$00F3
$00F4
$00F5
$00F6
$00F7
SPI1CR1
SPI1CR2
SPI1BR
SPI1SR
Reserved
SPI1DR
Reserved
Reserved
Read:
Write:
Read: 0 0 0
Write:
Read: 0
Write:
Read: SPIF 0 SPTEF MODF 0000
Write:
Read: 00000000
Write:
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
MODFEN BIDIROE
SPPR2 SPPR1 SPPR0
Bit7 654321Bit0
0
0
SPISWAI SPC0
SPR2 SPR1 SPR0
$00F8 - $00FF SPI2 (Serial Peripheral Interface)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $00F8
$00F9
$00FA
$00FB
$00FC
$00FD
$00FE
$00FF
SPI2CR1
SPI2CR2
SPI2BR
SPI2SR
Reserved
SPI2DR
Reserved
Reserved
Read:
Write:
Read: 0 0 0
Write:
Read: 0
Write:
Read: SPIF 0 SPTEF MODF 0000
Write:
Read: 00000000
Write:
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
MODFEN BIDIROE
SPPR2 SPPR1 SPPR0
Bit7 654321Bit0
0
0
SPISWAI SPC0
SPR2 SPR1 SPR0
$0100 - $010F Flash Control Register (fts256k)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0100
$0101
$0102
$0103
FCLKDIV
FSEC
FTSTMOD
FCNFG
Read: FDIVLD
Write:
Read: KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0
Write:
Read:
Write:
Read:
Write:
0 0 0 WRALL
CBEIE CCIE KEYACC
PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
000
000
BKSEL1 BKSEL0
0
39
MC9S12DT256 Device User Guide — V03.07
$0100 - $010F Flash Control Register (fts256k)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0104
$0105
$0106
$0107
$0108
$0109
$010A
$010B
$010C
$010D
$010E
$010F
FPROT
FSTAT
FCMD
Reserved for
Factory Test
FADDRHI
FADDRLO
FDATAHI
FDATALO
Reserved
Reserved
Reserved
Reserved
Read:
FPOPEN NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0
Write:
Read:
Write:
Read: 0
Write:
Read: 00000000
Write:
Read: 0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
CBEIF
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
CCIF
CMDB6 CMDB5
Bit 14 13 12 11 10 9 Bit 8
PVIOL ACCERR
00
0
BLANK
CMDB2
00
0
CMDB0
$0110 - $011B EEPROM Control Register (eets4k)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0110
$0111
$0112
$0113
$0114
$0115
$0116
$0117
$0118
ECLKDIV
Reserved
Reserved for
Factory Test
ECNFG
EPROT
ESTAT
ECMD
Reserved for
Factory Test
EADDRHI
Read: EDIVLD
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0
Write:
Read: 00000000
Write:
Read: 00000
Write:
CBEIE CCIE
EPOPEN
CBEIF
PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0
000000
NV6 NV5 NV4
CCIF
CMDB6 CMDB5
PVIOL ACCERR
00
EPDIS EP2 EP1 EP0
0
BLANK
CMDB2
10 9 Bit 8
00
0
CMDB0
40
MC9S12DT256 Device User Guide — V03.07
$0110 - $011B EEPROM Control Register (eets4k)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0119
$011A
$011B
EADDRLO
EDATAHI
EDATALO
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
$011C - $011F Reserved for RAM Control Register
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $011C
$011D
$011E
$011F
Reserved
Reserved
Reserved
Reserved
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
$0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0120
$0121
$0122
$0123
$0124
$0125
$0126
$0127
$0128
$0129
$012A
$012B
$012C
ATD1CTL0
ATD1CTL1
ATD1CTL2
ATD1CTL3
ATD1CTL4
ATD1CTL5
ATD1STAT0
Reserved
ATD1TEST0
ATD1TEST1
Reserved
ATD1STAT1
Reserved
Read: 00000000
Write:
Read: 00000000
Write:
Read:
Write:
Read: 0
Write:
Read:
Write:
Read:
Write:
Read: SCF 0 ETORF FIFOR 0 CC2 CC1 CC0
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000
Write:
Read: 00000000
Write:
Read: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
Write:
Read: 00000000
Write:
ADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE
S8C S4C S2C S1C FIFO FRZ1 FRZ0
SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
DJM DSGN SCAN MULT
0
CC CB CA
0
0
ASCIF
SC
41
MC9S12DT256 Device User Guide — V03.07
$0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $012D
$012E
$012F
$0130
$0131
$0132
$0133
$0134
$0135
$0136
$0137
$0138
$0139
$013A
$013B
$013C
$013D
$013E
$013F
ATD1DIEN
Reserved
PORTAD1
ATD1DR0H
ATD1DR0L
ATD1DR1H
ATD1DR1L
ATD1DR2H
ATD1DR2L
ATD1DR3H
ATD1DR3L
ATD1DR4H
ATD1DR4L
ATD1DR5H
ATD1DR5L
ATD1DR6H
ATD1DR6L
ATD1DR7H
ATD1DR7L
Read:
Write:
Read: 00000000
Write:
Read: Bit7 654321BIT 0
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Bit 7 654321Bit 0
$0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
42
$0140
$0141
$0142
CAN0CTL0
CAN0CTL1
CAN0BTR0
Read:
Write:
Read:
Write:
Read:
Write:
RXFRM
CANE CLKSRC LOOPB LISTEN
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
RXACT
CSWAI
SYNCH
TIME WUPE SLPRQ INITRQ
0
WUPM
SLPAK INITAK
MC9S12DT256 Device User Guide — V03.07
$0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0143
$0144
$0145
$0146
$0147
$0148
$0149
$014A
$014B
$014C
$014D
$014E
$014F $0150 -
$0153 $0154 -
$0157 $0158 -
$015B $015C -
$015F $0160 -
$016F $0170 -
$017F
CAN0BTR1
CAN0RFLG
CAN0RIER
CAN0TFLG
CAN0TIER
CAN0TARQ
CAN0TAAK
CAN0TBSEL
CAN0IDAC
Reserved
Reserved
CAN0RXERR
CAN0TXERR
CAN0IDAR0 -
CAN0IDAR3
CAN0IDMR0 -
CAN0IDMR3
CAN0IDAR4 -
CAN0IDAR7
CAN0IDMR4 -
CAN0IDMR7
CAN0RXFG
CAN0TXFG
Read:
Write:
Read:
Write:
Read:
Write:
Read: 00000
Write:
Read: 00000
Write:
Read: 00000
Write:
Read: 00000ABTAK2ABTAK1ABTAK0
Write:
Read: 00000
Write:
Read: 0 0
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: FOREGROUND RECEIVE BUFFER see Table 1-2
Write:
Read:
Write:
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
WUPIF CSCIF
WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
RSTAT1 RSTAT0 TSTAT1 TSTAT0
TXE2 TXE1 TXE0
TXEIE2 TXEIE1 TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0
TX2 TX1 TX0
IDAM1 IDAM0
FOREGROUND TRANSMIT BUFFER see Table 1-2
0 IDHIT2 IDHIT1 IDHIT0
OVRIF RXF

Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Extended ID Read: ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
$xxx0
$xxx1
Standard ID Read: ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
CANxRIDR0 Write:
Extended ID Read: ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15
Standard ID Read: ID2 ID1 ID0 RTR IDE=0
CANxRIDR1 Write:
43
MC9S12DT256 Device User Guide — V03.07
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Extended ID Read: ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
$xxx2
$xxx3
$xxx4­$xxxB
$xxxC CANRxDLR
$xxxD Reserved
$xxxE CANxRTSRH
$xxxF CANxRTSRL
$xx10
$xx10
$xx12
$xx13
$xx14­$xx1B
$xx1C CANxTDLR
$xx1D CONxTTBPR
$xx1E CANxTTSRH
$xx1F CANxTTSRL
Standard ID Read:
CANxRIDR2 Write:
Extended ID Read: ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
Standard ID Read:
CANxRIDR3 Write:
CANxRDSR0 -
CANxRDSR7
Extended ID Read: CANxTIDR0 Write:
Standard ID Read:
Extended ID Read: CANxTIDR1 Write:
Standard ID Read:
Extended ID Read: CANxTIDR2 Write:
Standard ID Read:
Extended ID Read: CANxTIDR3 Write:
Standard ID Read:
CANxTDSR0 -
CANxTDSR7
Read: DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write:
Read:
Write:
Read:
Write:
Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
Write:
Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
Write:
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
Write:
Write:
Write:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
Write:
Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
Write:
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15
ID2 ID1 ID0 RTR IDE=0
ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0
DLC3 DLC2 DLC1 DLC0
DLC3 DLC2 DLC1 DLC0
44
MC9S12DT256 Device User Guide — V03.07
$0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0180
$0181
$0182
$0183
$0184
$0185
$0186
$0187
$0188
$0189
$018A
$018B
$018C
$018D
$018E
$018F
$0190
$0191
$0192
$0193
$0194
$0195
$0196
$0197
$0198
CAN1CTL0
CAN1CTL1
CAN1BTR0
CAN1BTR1
CAN1RFLG
CAN1RIER
CAN1TFLG
CAN1TIER
CAN1TARQ
CAN1TAAK
CAN1TBSEL
CAN1IDAC
Reserved
Reserved
CAN1RXERR
CAN1TXERR
CAN1IDAR0
CAN1IDAR1
CAN1IDAR2
CAN1IDAR3
CAN1IDMR0
CAN1IDMR1
CAN1IDMR2
CAN1IDMR3
CAN1IDAR4
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 00000
Write:
Read: 00000
Write:
Read: 00000
Write:
Read: 00000ABTAK2ABTAK1ABTAK0
Write:
Read: 00000
Write:
Read: 0 0
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
RXFRM
CANE CLKSRC LOOPB LISTEN
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
WUPIF CSCIF
WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
RXACT
CSWAI
RSTAT1 RSTAT0 TSTAT1 TSTAT0
IDAM1 IDAM0
SYNCH
TIME WUPE SLPRQ INITRQ
0
0 IDHIT2 IDHIT1 IDHIT0
WUPM
TXE2 TXE1 TXE0
TXEIE2 TXEIE1 TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0
TX2 TX1 TX0
SLPAK INITAK
OVRIF RXF
45
MC9S12DT256 Device User Guide — V03.07
$0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0199
$019A
$019B
$019C
$019D
$019E
$019F $01A0 -
$01AF $01B0 -
$01BF
CAN1IDAR5
CAN1IDAR6
CAN1IDAR7
CAN1IDMR4
CAN1IDMR5
CAN1IDMR6
CAN1IDMR7
CAN1RXFG
CAN1TXFG
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: FOREGROUND RECEIVE BUFFER see Table 1-2
Write:
Read:
Write:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
FOREGROUND TRANSMIT BUFFER see Table 1-2
$0240 - $027F PIM (Port Integration Module PIM_9DP256)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0240
$0241
$0242
$0243
$0244
$0245
$0246
$0247
$0248
$0249
$024A
$024B
$024C
PTT
PTIT
DDRT
RDRT
PERT
PPST
Reserved
Reserved
PTS
PTIS
DDRS
RDRS
PERS
Read:
Write:
Read: PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read:
Write:
Read: PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0
DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0
46
MC9S12DT256 Device User Guide — V03.07
$0240 - $027F PIM (Port Integration Module PIM_9DP256)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $024D
$024E
$024F
$0250
$0251
$0252
$0253
$0254
$0255
$0256
$0257
$0258
$0259
$025A
$025B
$025C
$025D
$025E
$025F
$0260
$0261
$0262
$0263
$0264
$0265
PPSS
WOMS
Reserved
PTM
PTIM
DDRM
RDRM
PERM
PPSM
WOMM
MODRR
PTP
PTIP
DDRP
RDRP
PERP
PPSP
PIEP
PIFP
PTH
PTIH
DDRH
RDRH
PERH
PPSH
Read:
Write:
Read:
Write:
Read: 00000000
Write:
Read:
Write:
Read: PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0
Write:
Read:
Write:
Read: PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0
WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0
DDRM7 DDRM7 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0
PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSS0
PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0
DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0
PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0
PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0
47
MC9S12DT256 Device User Guide — V03.07
$0240 - $027F PIM (Port Integration Module PIM_9DP256)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0266
$0267
$0268
$0269
$026A
$026B
$026C
$026D
$026E
$026F $0270 -
$027F
PIEH
PIFH
PTJ
PTIJ
DDRJ
RDRJ
PERJ
PPSJ
PIEJ
PIFJ
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read: PTIJ7 PTIJ6 0000PTIJ1 PTIJ0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0
PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0
PTJ7 PTJ6
DDRJ7 DDRJ7
RDRJ7 RDRJ6
PERJ7 PERJ6
PPSJ7 PPSJ6
PIEJ7 PIEJ6
PIFJ7 PIFJ6
0000
0000
0000
0000
0000
0000
0000
DDRJ1 DDRJ0
RDRJ1 RDRJ0
PERJ1 PERJ0
PPSJ1 PPSJ0
PTJ1 PTJ0
PIEJ1 PIEJ0
PIFJ1 PIFJ0
$0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0280
$0281
$0282
$0283
$0284
$0285
$0286
$0287
$0288
$0289
$028A
$028B
CAN4CTL0
CAN4CTL1
CAN4BTR0
CAN4BTR1
CAN4RFLG
CAN4RIER
CAN4TFLG
CAN4TIER
CAN4TARQ
CAN4TAAK
CAN4TBSEL
CAN4IDAC
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 00000
Write:
Read: 00000
Write:
Read: 00000
Write:
Read: 00000ABTAK2ABTAK1ABTAK0
Write:
Read: 00000
Write:
Read: 0 0
Write:
RXFRM
CANE CLKSRC LOOPB LISTEN
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
WUPIF CSCIF
WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
RXACT
CSWAI
RSTAT1 RSTAT0 TSTAT1 TSTAT0
IDAM1 IDAM0
SYNCH
TIME WUPE SLPRQ INITRQ
0
0 IDHIT2 IDHIT1 IDHIT0
WUPM
TXE2 TXE1 TXE0
TXEIE2 TXEIE1 TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0
TX2 TX1 TX0
SLPAK INITAK
OVRIF RXF
48
MC9S12DT256 Device User Guide — V03.07
$0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $028C
$028D
$028E
$028F
$0290
$0291
$0292
$0293
$0294
$0295
$0296
$0297
$0298
$0299
$029A
$029B
$029C
$029D
$029E
$029F $02A0 -
$02AF $02B0 -
$02BF
Reserved
Reserved
CAN4RXERR
CAN4TXERR
CAN4IDAR0
CAN4IDAR1
CAN4IDAR2
CAN4IDAR3
CAN4IDMR0
CAN4IDMR1
CAN4IDMR2
CAN4IDMR3
CAN4IDAR4
CAN4IDAR5
CAN4IDAR6
CAN4IDAR7
CAN4IDMR4
CAN4IDMR5
CAN4IDMR6
CAN4IDMR7
CAN4RXFG
CAN4TXFG
Read: 00000000
Write:
Read: 00000000
Write:
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: FOREGROUND RECEIVE BUFFER see Table 1-2
Write:
Read:
Write:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
FOREGROUND TRANSMIT BUFFER see Table 1-2
49
MC9S12DT256 Device User Guide — V03.07
$02C0 - $03FF Reserved space
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $02C0
- $03FF
Reserved
Read: 00000000
Write:

1.7 Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a uniquepartIDforeachrevisionof the chip. Table 1-3showstheassigned part ID number.

Table 1-3 Assigned Part ID Numbers

Device Mask Set Number
MC9S12DT256 0L91N MC9S12DT256 1L91N $0031
MC9S12DT256 3L91N $0032 MC9S12DT256 4L91N $0034 MC9S12DT256 0L01Y $0033
NOTES:
1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor - non full - mask set revision
Part ID
1
$0030
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to section Module Mapping and Control (MMC) of HCS12 Core User Guide for further details.

Table 1-4 Memory size registers

Register name Value
MEMSIZ0 MEMSIZ1
$25 $81
50
MC9S12DT256 Device User Guide — V03.07

Section 2 Signal Description

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the Block User Guides of the individual IP blocks on the device.

2.1 Device Pinout

The MC9S12DT256/MC9S12DJ256/MC9S12DG256 and MC9S12A256 is available in a 112-pin low profile quad flat pack (LQFP) andMC9S12DJ256/MC9S12DG256andMC9S12A256is also available in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 2-1 and Figure 2-2 show the pin assignments.
51
MC9S12DT256 Device User Guide — V03.07
PP4/KWP4/PWM4/MISO2
PP5/KPW5/PWM5/MOSI2
PP6/KWP6/PWM6/SS2
PP7/KWP7/PWM7/SCK2
PK7/ECS
VDDX
VSSX
PM0/RXCAN0/RXB
PM1/TXCAN0/TXB
PM2/RXCAN1/RXCAN0/MISO0
PM3/TXCAN1/TXCAN0/SS0
PM4/RXCAN0/RXCAN4/MOSI0
PM5/TXCAN0/TXCAN4/SCK0
PJ6/KWJ6/RXCAN4/SDA
PJ7/KWJ7/TXCAN4/SCL
VREGEN
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
PM6/RXCAN4
PM7/TXCAN4
VSSA
VRL
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0
XADDR17/PK3
XADDR16/PK2
XADDR15/PK1
XADDR14/PK0
IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3
VDD1
VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7
XADDR19/PK5
XADDR18/PK4
KWJ1/PJ1
KWJ0/PJ0
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
112
111
110
109
108
107
106
105
104
103
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
293031323334353637383940414243444546474849505152535455
102
MC9S12DT256/MC9S12A256/
MC9S12DJ256/MC9S12DG256
999897969594939291908988878685
101
100
84
VRH
83
VDDA
82
PAD15/AN15/ETRIG1
81
PAD07/AN07/ETRIG0
80
PAD14/AN14
79
PAD06/AN06
78
PAD13/AN13
77
PAD05/AN05
76
PAD12/AN12
75
PAD04/AN04
74
PAD11/AN11
73
PAD03/AN03
72
PAD10/AN10
71
PAD02/AN02
70
PAD09/AN09
69
PAD01/AN01
68
PAD08/AN08
67
PAD00/AN00
66
VSS2
65
VDD2
64
PA7/ADDR15/DATA15
63
PA6/ADDR14/DATA14
62
PA5/ADDR13/DATA13
61
PA4/ADDR12/DATA12
60
PA3/ADDR11/DATA11
59
PA2/ADDR10/DATA10
58
PA1/ADDR9/DATA9
57
PA0/ADDR8/DATA8
56
52
XFC
XTAL
EXTAL
VSSPLL
TEST
SS1/KWH3/PH3
SCK1/KWH2/PH2
MOSI1/KWH1/PH1
MISO1/KWH0/PH0
LSTRB/TAGLO/PE3
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
SS2/KWH7/PH7
SCK2/KWH6/PH6
ADDR7/DATA7/PB7
MOSI2/KWH5/PH5
ECLK/PE4
MODA/IPIPE0/PE5
MISO2/KWH4/PH4
MODB/IPIPE1/PE6
XCLKS/NOACC/PE7
VSSR
VDDR
RESET
VDDPLL
Signals shown in Bold are not available on the 80 Pin Package

Figure 2-1 Pin Assignments in 112-pin LQFP

IRQ/PE1
R/W/PE2
XIRQ/PE0
PP4/KWP4/PWM4/MISO2
PP5/KWP5/PWM5/MOSI2
PP7/KWP7/PWM7/SCK2
VDDX
VSSX
PM0/RXCAN0/RXB
PM1/TXCAN0/TXB
PM2/RXCAN1/RXCAN0/MISO0
MC9S12DT256 Device User Guide — V03.07
PM3/TXCAN1/TXCAN0/SS0
PM4/RXCAN0/RXCAN4/MOSI0
PM5/TXCAN0/TXCAN4/SCK0
PJ6/KWJ6/RXCAN4/SDA
PJ7/KWJ7/TXCAN4/SCL
VREGEN
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
VSSA
VRL
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0
MODC/
IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3
VDD1
VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7
TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
80797877767574737271706968676665646362
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
21222324252627282930313233343536373839
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
XCLKS/NOACC/PE7
MC9S12DJ256
80 QFP
VSSR
VDDR
ECLK/PE4
MODA/IPIPE0/PE5
MODB/IPIPE1/PE6
RESET
VDDPLL
XFC
EXTAL
VSSPLL
XTAL
TEST
IRQ/PE1
R/W/PE2
LSTRB/TAGLO/PE3
61
60
VRH
59
VDDA
58
PAD07/AN07/ETRIG0
57
PAD06/AN06
56
PAD05/AN05
55
PAD04/AN04
54
PAD03/AN03
53
PAD02/AN02
52
PAD01/AN01
51
PAD00/AN00
50
VSS2
49
VDD2
48
PA7/ADDR15/DATA15
47
PA6/ADDR14/DATA14
46
PA5/ADDR13/DATA13
45
PA4/ADDR12/DATA12
44
PA3/ADDR11/DATA11
43
PA2/ADDR10/DATA10
42
PA1/ADDR9/DATA9
41
PA0/ADDR8/DATA8
40
XIRQ/PE0

Figure 2-2 Pin Assignments in 80-pin QFP for MC9S12DJ256

2.2 Signal Properties Summary

Table 2-1summarizes the pin functionality. Signalsshownin bold are not available in the 80 pin package.

Table 2-1 Signal Properties

53
MC9S12DT256 Device User Guide — V03.07
Internal Pull
Pin Name
Funct. 1
EXTAL — — — — VDDPLL NA NA
XTAL — — — — VDDPLL NA NA
RESET — — — — VDDR
TEST — — — — N.A. NA NA Test Input
VREGEN — — — — VDDX NA NA
XFC — — — — VDDPLL NA NA
BKGD
PAD[15] AN1[7] ETRIG1 — — VDDA
PAD[14:8] AN1[6:0] — — — VDDA
PAD[7] AN0[7] ETRIG0 — — VDDA
PAD[6:0] AN0[6:0] — — — VDDA
PA[7:0]
PB[7:0]
PE7 NOACC
PE6 IPIPE1 MODB — — VDDR
PE5 IPIPE0 MODA — — VDDR
PE4 ECLK — — — VDDR PE3 PE2 R/ PE1 PE0
PH7 KWH7 SS2 — — VDDR
PH6 KWH6 SCK2 — — VDDR
PH5 KWH5 MOSI2 — — VDDR
Pin Name
Funct. 2
TAGHI MODC — — VDDR
ADDR[15:8]/
DATA[15:8]
ADDR[7:0]/
DATA[7:0]
LSTRB TAGLO — — VDDR
W — — — VDDR
IRQ — — — VDDR PUCR Up
XIRQ — — — VDDR PUCR Up
Pin Name
Funct. 3
— — — VDDR
— — — VDDR
XCLKS — — VDDR
Pin Name
Funct. 4
Pin Name
Funct. 5
Power
Supply
Resistor
CTRL
None None External Reset
Always
Up
None None
None None
None None
None None
PUCR Disabled Port A I/O, Multiplexed Address/Data
PUCR Disabled Port B I/O, Multiplexed Address/Data PUCR Up Port E I/O, Access, Clock Select
While
While RESET
PUCR Up Port E I/O, Bus Clock Output PUCR Up Port E I/O, Byte Strobe, Tag Low PUCR Up Port E I/O, R/
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
Reset
State
Oscillator Pins
Voltage Regulator Enable Input PLL Loop Filter
Up
RESET
pin is low:
Down
pin is low:
Down
Disabled Port H I/O, Interrupt,
Disabled Port H I/O, Interrupt, SCK of SPI2
Disabled Port H I/O, Interrupt, MOSI of SPI2
Background Debug, Tag High, Mode Input
Port AD Input, Analog Input AN7 of ATD1, External Trigger Input of
ATD1 Port AD Inputs, Analog Inputs
AN[6:0] of ATD1
Port AD Input, Analog Input AN7 of ATD0, External Trigger Input of ATD0
Port AD Inputs, Analog Inputs AN[6:0] of ATD0
Port E I/O, Pipe Status, Mode Input
Port E I/O, Pipe Status, Mode Input
Port E Input, Maskable Interrupt Port E Input, Non Maskable Interrupt
Description
W in expanded modes
SS of SPI2
54
Pin Name
Funct. 1
PH4 KWH4 MISO2 — — VDDR
PH3 KWH3
PH2 KWH2 SCK1 — — VDDR
PH1 KWH1 MOSI1 — — VDDR
PH0 KWH0 MISO1 — — VDDR
PJ7 KWJ7 TXCAN4 SCL TXCAN0 VDDX
PJ6 KWJ6 RXCAN4 SDA RXCAN0 VDDX
PJ[1:0] KWJ[1:0] — — — VDDX
PK7 ECS ROMONE — — VDDX
PK[5:0]
PM7 TXCAN4 — — — VDDX
PM6 RXCAN4 — — — VDDX
PM5 TXCAN0 TXCAN4 SCK0 — VDDX
PM4 RXCAN0 RXCAN4 MOSI0 — VDDX
PM3 TXCAN1 TXCAN0 —
PM2 RXCAN1 RXCAN0 — MISO0 VDDX
PM1 TXCAN0 TXB — — VDDX
PM0 RXCAN0 RXB — — VDDX
PP7 KWP7 PWM7 SCK2 — VDDX
PP6 KWP6 PWM6
PP5 KWP5 PWM5 MOSI2 — VDDX
Pin Name
Funct. 2
XADDR
[19:14]
Pin Name
Funct. 3
SS1 — — VDDR
— — — VDDX
Pin Name
Funct. 4
SS2 — VDDX
Pin Name
Funct. 5
SS0 VDDX
Power
Supply
MC9S12DT256 Device User Guide — V03.07
Internal Pull
Resistor
CTRL
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERJ/
PPSJ
PERJ/
PPSJ
PERJ/
PSJ
PUCR Up
PUCR Up Port K I/O, Extended Addresses
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
Reset
State
Disabled Port H I/O, Interrupt, MISO of SPI2
Disabled Port H I/O, Interrupt,
Disabled Port H I/O, Interrupt, SCK of SPI1
Disabled Port H I/O, Interrupt, MOSI of SPI1
Disabled Port H I/O, Interrupt, MISO of SPI1
Up
Up
Up Port J I/O, Interrupts
Disabled Port M I/O, TX of CAN4
Disabled Port M I/O RX of CAN4
Disabled
Disabled
Disabled
Disabled
Disabled Port M I/O, TX of CAN0, TX of BDLC
Disabled Port MI/O, RX of CAN0, RX ofBDLC
Disabled
Disabled
Disabled
Port J I/O, Interrupt, TX of CAN4, SCL of IIC, TX of CAN0
Port J I/O, Interrupt, RX of CAN4, SDA of IIC, RX of CAN0
Port K I/O, Emulation Chip Select, ROM On Enable
Port M I/OCAN0, CAN4, SCK of SPI0
Port M I/O, CAN0, CAN4, MOSI of SPI0
Port M I/O, TX of CAN1, CAN0, of SPI0
Port M I/O, RX of CAN1, CAN0, MISO of SPI0
Port P I/O, Interrupt, Channel 7 of PWM, SCK of SPI2
Port P I/O, Interrupt, Channel 6 of PWM,
Port P I/O, Interrupt, Channel 5 of PWM, MOSI of SPI2
Description
SS of SPI1
SS of SPI2
SS
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MC9S12DT256 Device User Guide — V03.07
Pin Name
Funct. 1
PP4 KWP4 PWM4 MISO2 — VDDX
PP3 KWP3 PWM3
PP2 KWP2 PWM2 SCK1 — VDDX
PP1 KWP1 PWM1 MOSI1 — VDDX
PP0 KWP0 PWM0 MISO1 — VDDX
PS7
PS6 SCK0 — — — VDDX
PS5 MOSI0 — — — VDDX
PS4 MISO0 ———VDDX
PS3 TXD1 — — — VDDX
PS2 RXD1 — — — VDDX
PS1 TXD0 — — — VDDX
PS0 RXD0 — — — VDDX
PT[7:0] IOC[7:0] — — — VDDX
Pin Name
Funct. 2
SS0 — — — VDDX
Pin Name
Funct. 3
Pin Name
Funct. 4
SS1 — VDDX
Pin Name
Funct. 5
Power
Supply
Internal Pull
Resistor
CTRL
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERT/
PPST
Reset
State
Disabled
Disabled
Disabled
Disabled
Disabled
Up Port S I/O,
Up Port S I/O, SCK of SPI0
Up Port S I/O, MOSI of SPI0
Up Port S I/O, MISO of SPI0
Up Port S I/O, TXD of SCI1
Up Port S I/O, RXD of SCI1
Up Port S I/O, TXD of SCI0
Up Port S I/O, RXD of SCI0
Disabled Port T I/O, Timer channels
Port P I/O, Interrupt, Channel 4 of PWM, MISO2 of SPI2
Port P I/O, Interrupt, Channel 3 of PWM,
Port P I/O, Interrupt, Channel 2 of PWM, SCK of SPI1
Port P I/O, Interrupt, Channel 1 of PWM, MOSI of SPI1
Port P I/O, Interrupt, Channel 0 of PWM, MISO2 of SPI1
Description
SS of SPI1
SS of SPI0

2.3 Detailed Signal Descriptions

2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL andXTALare the crystal driver and externalclockpins.On reset all the device clocksarederived from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset.
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2.3.3 TEST — Test Pin
This input only pin is reserved for test.
NOTE: The TEST pin must be tied to VSS in all applications.
2.3.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
2.3.5 XFC — PLL Loop Filter Pin
PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC
R
MCU
0
C
S
C
P
VDDPLLVDDPLL

Figure 2-3 PLL Loop Filter Connections

2.3.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of
RESET. This pin has a permanently enabled pull-up device.
2.3.7 PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1
PAD15 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD1. It can act as an external trigger input for the ATD1.
2.3.8 PAD[14:08] / AN[14:08] — Port AD Input Pins of ATD1
PAD14 - PAD08 are general purpose input pins and analog inputs AN[6:0] of the analog to digital converter ATD1.
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2.3.9 PAD7 / AN07 / ETRIG0 — Port AD Input Pin of ATD0
PAD7 is a general purpose input pin andanalog input AN7 of the analog to digital converter ATD0. Itcan act as an external trigger input for the ATD0.
2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0
PAD06 - PAD00 are general purpose input pins and analog inputs AN[6:0] of the analog to digital converter ATD0.
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal will assert when the CPU is not using the bus.The crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator. If input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL.
.
XCLKS is an input signal which controls whether a
RESET. If
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Figure 2-4 Colpitts Oscillator Connections (PE7=1)

EXTAL
CDC*
MCU
XTAL
* Due to the nature of a translated ground Colpitts oscillator a
DC voltage bias is applied to the crystal
.Please contact the crystal manufacturer for crystal DC
C
1
Crystal or
ceramic resonator
C
2
VSSPLL

Figure 2-5 Pierce Oscillator Connections (PE7=0)

EXTAL
C
1
MCU
XTAL
* Rs can be zero (shorted) when use with higher frequency crystals.
Refer to manufacturer’s data.
R
B
*
R
S
Crystal or
ceramic resonator
C
2
VSSPLL
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Figure 2-6 External Clock Connections (PE7=0)

MCU
EXTAL
XTAL
not connected
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
(VDDPLL-Level)
2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of
RESET. This pin is shared with the
instruction queue tracking signalIPIPE1.Thispinis an input with a pull-down device which is only active
RESET is low.
when
2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of
RESET. This pin is shared with the
instruction queue tracking signalIPIPE0.Thispinis an input with a pull-down device which is only active
RESET is low.
when
2.3.16 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference.
2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
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2.3.18 PE2 / R/W—Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the read/write output signal for the external bus. It indicates the direction of data on the external bus.
2.3.19 PE1 / IRQ — Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.20 PE0 / XIRQ — Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.21 PH7 / KWH7 / SS2 — Port H I/O Pin 7
PH7isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU to exit STOP or WAIT mode. It can be configured as slave select pin 2 (SPI2).
SS of the Serial Peripheral Interface
2.3.22 PH6 / KWH6 / SCK2 — Port H I/O Pin 6
PH6isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU toexitSTOP or WAIT mode.It can be configuredas serial clock pinSCKof the SerialPeripheralInterface 2 (SPI2).
2.3.23 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5
PH5isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2).
2.3.24 PH4 / KWH4 / MISO2 — Port H I/O Pin 2
PH4isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2).
2.3.25 PH3 / KWH3 / SS1 — Port H I/O Pin 3
PH3isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU to exit STOP or WAIT mode. It can be configured as slave select pin 1 (SPI1).
SS of the Serial Peripheral Interface
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2.3.26 PH2 / KWH2 / SCK1 — Port H I/O Pin 2
PH2isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU toexitSTOP or WAITmode.It can beconfigured as serial clockpin SCK 1 (SPI1).
oftheSerial Peripheral Interface
2.3.27 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1
PH1isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI
of the Serial Peripheral Interface 1 (SPI1).
2.3.28 PH0 / KWH0 / MISO1 — Port H I/O Pin 0
PH0isa general purpose inputor output pin. Itcan be configured togeneratean interrupt causingtheMCU to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO
of the Serial Peripheral Interface 1 (SPI1).
2.3.29 PJ7 / KWJ7 / TXCAN4 / SCL — PORT J I/O Pin 7
PJ7 is a generalpurposeinputoroutput pin. It can be configured to generate an interrupt causing theMCU to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable Controller Area Network controller 4 (CAN4) or the serial clock pin SCL of the IIC module.
2.3.30 PJ6 / KWJ6 / RXCAN4 / SDA — PORT J I/O Pin 6
PJ6 is a generalpurposeinputoroutput pin. It can be configured to generate an interrupt causing theMCU to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Motorola Scalable Controller Area Network controller 4 (CAN4) or the serial data pin SDA of the IIC module.
2.3.31 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0]
PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode .
2.3.32 PK7 / ECS / ROMONE — Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used as the emulation chip select output ( operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMONE). At the rising edge of
RESET, the state of this pin is latched to the ROMON bit.
ECS). During MCU normal expanded wide and narrow modes of
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2.3.33 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins provide the expanded address XADDR[19:14] for the external bus.
2.3.34 PM7 / TXCAN4 — Port M I/O Pin 7
PM7 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 4 (CAN4 ).
2.3.35 PM6 / RXCAN4 — Port M I/O Pin 6
PM6 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 4 (CAN4).
2.3.36 PM5 / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.37 PM4 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 0 or 4 ( CAN0 or CAN4). It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI Peripheral Interface 0 (SPI0).
for the Serial
2.3.38 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the slave select pin
SS of the Serial Peripheral Interface 0 (SPI0).
2.3.39 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the master input (during master mode) or slave output pin (during slave mode) MISO Peripheral Interface 0 (SPI0).
for the Serial
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2.3.40 PM1 / TXCAN0 / TXB — Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0). It can be configured as the transmit pin TXB of the BDLC.
2.3.41 PM0 / RXCAN0 / RXB — Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0). It can be configured as the receive pin RXB of the BDLC.
2.3.42 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7
PP7 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2).
2.3.43 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6
PP6 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. It can be configured as slave select pin
SS of the Serial Peripheral Interface 2 (SPI2).
2.3.44 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5
PP5 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2).
2.3.45 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4
PP4 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2).
2.3.46 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3
PP3 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It can be configured as slave select pin
SS of the Serial Peripheral Interface 1 (SPI1).
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2.3.47 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2
PP2 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.48 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1
PP1 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
2.3.49 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0
PP0 isageneral purpose input or outputpin.Itcan be configured to generateaninterrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
2.3.50 PS7 / SS0 — Port S I/O Pin 7
PS6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.3.51 PS6 / SCK0 — Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.52 PS5 / MOSI0 — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.53 PS4 / MISO0 — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.54 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 1 (SCI1).
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2.3.55 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1).
2.3.56 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 0 (SCI0).
2.3.57 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 0 (SCI0).
2.3.58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).

2.4 Power Supply Pins

MC9S12DT256 power and ground pins are described below.
NOTE: All VSS pins must be connected together in the application.
2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demandsonthepower supply, use bypass capacitors withhigh-frequencycharacteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
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2.4.3 VDD1, VDD2, VSS1, VSS2 — Core Power Pins
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VREGEN is tied to ground.
NOTE: No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital converter. It also provides the reference for the internal voltage regulator. This allows the supply voltage to the ATD and the reference voltage to be bypassed independently.
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by the internal voltage regulator.
NOTE: No load allowed except for bypass capacitors.

Table 2-2 MC9S12DP256 Power and Ground Connection Summary

Mnemonic
V
DD1, 2
V
SS1, 2
V
DDR
V
SSR
V
DDX
V
SSX
V
DDA
V
SSA
V
RL
V
RH
Pin Number
112-pin QFP
13, 65 2.5 V 14, 66 0V
41 5.0 V
40 0 V 107 5.0 V 106 0 V
83 5.0 V Operating voltage and ground for the analog-to-digital
86 0 V
85 0 V
84 5.0 V
Nominal
Voltage
Description
Internal power and ground generated by internal regulator
External power and ground, supply to pin drivers and internal
voltage regulator.
External power and ground, supply to pin drivers.
converters and the reference for the internal voltageregulator, allows the supply voltage to the A/D to be bypassed independently.
Reference voltages for the analog-to-digital converter.
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Mnemonic
V
DDPLL
V
SSPLL
VREGEN 97 5V Internal Voltage Regulator enable/disable
Pin Number
112-pin QFP
43 2.5 V Provides operating voltage and ground for the Phased-Locked
45 0 V
Nominal
Voltage
Description
Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator.
2.4.7 VREGEN — On Chip Voltage Regulator Enable
Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be supplied externally.
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Section 3 System Clock Description

3.1 Overview

The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide for details on clock generation.
BDM
S12_CORE
core clock
Flash
RAM
EXTAL
XTAL
CRG
bus clock
oscillator clock

Figure 3-1 Clock Connections

EEPROM
ECT
ATD0, 1
PWM
SCI0, SCI1
SPI0, 1, 2
CAN0, 1, 2, 3, 4
IIC
BDLC
PIM
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Section 4 Modes of Operation

4.1 Overview

Eight possible modes determine the operating configuration of the MC9S12DT256. Each mode has an associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.

4.2 Chip Configuration Summary

The operatingmode out of resetisdetermined by the statesof the MODC, MODB,andMODA pins during reset (Table4-1).TheMODC,MODB, and MODA bits intheMODE register show the currentoperating modeandprovide limited modeswitchingduring operation. Thestates of theMODC,MODB, and MODA pinsarelatched into thesebitson the risingedge of theresetsignal. The ROMCTLsignalallows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.

Table 4-1 Mode Selection

BKGD =
MODC
000X1
001
010X0
011
100X1
101
110X1
111
PE6 =
MODB
PE5 =
MODA
PK7 =
ROMCTL
01 10
01 10
00 11
00 11
ROMON
Bit
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active.
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause
bus conflicts (must not be used)
Normal Expanded Wide, BDM allowed
For further explanation on the modes refer to the Core User Guide.
Mode Description

Table 4-2 Clock Selection Based on PE7

PE7 = XCLKS Description
1
Colpitts Oscillator selected
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Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS Description
0
Pierce Oscillator/external clock selected

Table 4-3 Voltage Regulator VREGEN

VREGEN Description
1
0
Internal Voltage Regulator enabled Internal Voltage Regulator disabled, VDD1,2 and
VDDPLL must be supplied externally with 2.5V

4.3 Security

The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows:
• Protection of the contents of FLASH,
• Protection of the contents of EEPROM,
• Operation in single-chip mode,
• Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example would be user’s code that dumps the contents of theinternal program. This code would defeat the purpose of security. At the same time theuser may also wish to put a back door inthe user’s program. An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array. Check the Flash Block User Guide for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode
This will bethemostcommon usage of the secured part. Everything will appear thesameasif the part was not secured with the exception of BDM operation. The BDM operation will be blocked.
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4.3.2.2 Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be done through an external program in expanded mode.
Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program completes,theuser can eraseandprogram the FLASHsecurity bits totheunsecured state. Thisisgenerally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again.

4.4 Low Power Modes

The microcontroller features three main low power modes. Consult the respective Block User Guide for information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of information about the clock system is the Clock and Reset Generator User Guide (CRG).
4.4.1 Stop
Executing the CPU STOP instruction stops all clocks andthe oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the full STOP mode, but the wake up time from this mode is significantly shorter.
4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions.Theinternal CPU signals(addressand databus) willbe fully static.Allperipherals stay active. For further power consumption the peripherals can individually turn off their local clocks.
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4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power.
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Section 5 Resets and Interrupts

5.1 Overview

Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and interrupts.

5.2 Vectors

5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.

Table 5-1 Interrupt Vector Locations

Vector Address Interrupt Source
$FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFF0, $FFF1 $FFEE, $FFEF $FFEC, $FFED $FFEA, $FFEB $FFE8, $FFE9 $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFDE, $FFDF $FFDC, $FFDD $FFDA, $FFDB $FFD8, $FFD9
$FFD6, $FFD7
$FFD4, $FFD5 $FFD2, $FFD3
Clock Monitor fail reset None PLLCTL (CME, SCME) –
Unimplemented instruction trap None None –
Enhanced Capture Timer channel 0 I-Bit TIE (C0I) $EE Enhanced Capture Timer channel 1 I-Bit TIE (C1I) $EC Enhanced Capture Timer channel 2 I-Bit TIE (C2I) $EA Enhanced Capture Timer channel 3 I-Bit TIE (C3I) $E8 Enhanced Capture Timer channel 4 I-Bit TIE (C4I) $E6 Enhanced Capture Timer channel 5 I-Bit TIE (C5I) $E4 Enhanced Capture Timer channel 6 I-Bit TIE (C6I) $E2 Enhanced Capture Timer channel 7 I-Bit TIE (C7I) $E0
Enhanced Capture Timer overflow I-Bit TSRC2 (TOF) $DE
Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC Pulse accumulator input edge I-Bit PACTL (PAI) $DA
Reset None None –
COP failure reset None COP rate select –
SWI None None –
XIRQ X-Bit None –
IRQ I-Bit IRQCR (IRQEN) $F2
Real Time Interrupt I-Bit CRGINT (RTIE) $F0
SPI0 I-Bit SP0CR1 (SPIE, SPTIE) $D8 SCI0 I-Bit
SCI1 I-Bit
ATD0 I-Bit ATD0CTL2 (ASCIE) $D2
CCR
Mask
Local Enable
SC0CR2
(TIE, TCIE, RIE, ILIE)
SC1CR2
(TIE, TCIE, RIE, ILIE)
HPRIO Value
to Elevate
$D6
$D4
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$FFD0, $FFD1 $FFCE, $FFCF $FFCC, $FFCD $FFCA, $FFCB $FFC8, $FFC9 $FFC6, $FFC7 $FFC4, $FFC5 $FFC2, $FFC3 $FFC0, $FFC1 $FFBE, $FFBF $FFBC, $FFBD $FFBA, $FFBB $FFB8, $FFB9 $FFB6, $FFB7 $FFB4, $FFB5 $FFB2, $FFB3 $FFB0, $FFB1 $FFAE, $FFAF $FFAC, $FFAD $FFAA, $FFAB $FFA8, $FFA9
ATD1 I-Bit ATD1CTL2 (ASCIE) $D0 Port J I-Bit PTJIF (PTJIE) $CE
Port H I-Bit PTHIF(PTHIE) $CC
Modulus Down Counter underflow I-Bit MCCTL(MCZI) $CA
Pulse Accumulator B Overflow I-Bit PBCTL(PBOVI) $C8
CRG PLL lock I-Bit CRGINT(LOCKIE) $C6
CRG Self Clock Mode I-Bit CRGINT (SCMIE) $C4
BDLC I-Bit DLCBCR1(IE) $C2
IIC Bus I-Bit IBCR (IBIE) $C0
SPI1 I-Bit SP1CR1 (SPIE, SPTIE) $BE SPI2 I-Bit SP2CR1 (SPIE, SPTIE) $BC
EEPROM I-Bit ECNFG (CCIE, CBEIE) $BA
FLASH I-Bit FCNFG (CCIE, CBEIE) $B8
CAN0 wake-up I-Bit CAN0RIER (WUPIE) $B6
CAN0 errors I-Bit CAN0RIER (CSCIE, OVRIE) $B4
CAN0 receive I-Bit CAN0RIER (RXFIE) $B2
CAN0 transmit I-Bit CAN0TIER (TXEIE2-TXEIE0) $B0
CAN1 wake-up I-Bit CAN1RIER (WUPIE) $AE
CAN1 errors I-Bit CAN1RIER (CSCIE, OVRIE) $AC
CAN1 receive I-Bit CAN1RIER (RXFIE) $AA
CAN1 transmit I-Bit CAN1TIER (TXEIE2-TXEIE0) $A8 $FFA6, $FFA7 $FFA4, $FFA5 $FFA2, $FFA3 $FFA0, $FFA1 $FF9E, $FF9F $FF9C, $FF9D $FF9A, $FF9B $FF98, $FF99 $FF96, $FF97 $FF94, $FF95 $FF92, $FF93 $FF90, $FF91 $FF8E, $FF8F $FF8C, $FF8D
$FF80 to $FF8B
Reserved
CAN4 wake-up I-Bit CAN4RIER (WUPIE) $96
CAN4 errors I-Bit CAN4RIER (CSCIE, OVRIE) $94
CAN4 receive I-Bit CAN4RIER (RXFIE) $92
CAN4 transmit I-Bit CAN4TIER (TXEIE2-TXEIE0) $90
Port P Interrupt I-Bit PTPIF (PTPIE) $8E
PWM Emergency Shutdown I-Bit PWMSDN (PWMIE) $8C
Reserved
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5.3 Effects of Reset

When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states.
5.3.1 I/O pins
Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A, B, E and K out of reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
NOTE: For devices assembled in 80-pin QFP packages all non-bonded out pins should be
configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 2-1 for affected pins.
5.3.2 Memory
Refer to Table 1-1 for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset.
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Section 6 HCS12 Core Block Description

6.1 CPU12 Block Description

Consult the CPU12 Reference Manual for information on the CPU. When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock Periods.

6.2 HCS12 Module Mapping Control (MMC) Block Description

Consult the MMC Block User Guide for information on the Module Mapping Control Block.
6.2.1 Device specific information
• INITEE
– Reset state: $01 – Bits EE11-EE15 are writeable once in Normal and Emulation Mode
• PPAGE
– Reset state : $00 – Register is writeable anytime in all modes

6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block Description

Consult the MEBI Block Guide for information on Multiplexed External Bus Interface.
6.3.1 Device specific information
• PUCR
– Reset State : $90

6.4 HCS12 Interrupt (INT) Block description

Consult the INT Block guide for information on HCS12 Interrupt block.

6.5 HCS12 Background Debug (BDM) Block Description

Consult the BDM Block guide for information on HCS12 Background Debug block
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6.6 HCS12 Breakpoint (BKP) Block Description

Consult the BKP Block guide for information on HCS12 breakpoint block

Section 7 Clock and Reset Generator (CRG) Block Description

Consult the CRG Block User Guide for information about the Clock and Reset Generator module.

7.1 Device-specific information

7.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7).

Section 8 Enhanced Capture Timer (ECT) Block Description

Consult the ECT_16B8C Block User Guide for information about the Enhanced Capture Timer module When the ECT_16B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.

Section 9 Analog to Digital Converter (ATD) Block Description

There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DT256. Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter module.When the ATD_10B8C Block Guidereferstofreezemode this is equivalent to active BDM mode.

Section 10 Inter-IC Bus (IIC) Block Description

Consult the IIC Block User Guide for information about the Inter-IC Bus module.

Section 11 Serial Communications Interface (SCI) Block Description

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There are two Serial Communications Interfaces (SCI1 and SCI0) implemented on the MC9S12DT256 device. Consult the SCI Block User Guide for information about each Serial Communications Interface module.

Section 12 Serial Peripheral Interface (SPI) Block Description

There are three Serial Peripheral Interfaces(SPI2, SPI1 and SPI0) implemented on MC9S12DT256. Consult the SPI Block User Guide for information about each Serial Peripheral Interface module.

Section 13 J1850 (BDLC) Block Description

Consult the BDLC Block User Guide for information about the J1850 module.

Section 14 Pulse Width Modulator (PWM) Block Description

Consult the PWM_8B8C Block User Guide for information about the Pulse Width Modulator module. When the PWM _8B8CBlock Guide refers to freeze mode this is equivalent to active BDM mode

Section 15 Flash EEPROM 256K Block Description

The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will be programmed into the flash memory of this device during manufacture. This LRAE program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using CAN or SCI after it is assembled on the PCB. Use of the LRAE program is at the discretion of the end user and, if not required, it must simply be erased prior to flash programming. For more details of the S12 LRAE and its implementation, please see the S12 LREA Application Note (AN2546/D).
It isplanned that most HC9S12devicesmanufactured after Q1 of2004 will be shippedwiththe S12 LRAE programmed in theFlash.Exact details of the changeover (i.e. blank toprogrammed)for each product will be communicated in advance via GPCN and will be traceable by the customer via datecode marking on the device.
Please contact Motorola SPS Sales if you have any additional questions. Consult the FTS256K Block User Guide for information about the flash module.

Section 16 EEPROM 4K Block Description

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Consult the EETS4K Block User Guide for information about the EEPROM module.

Section 17 RAM Block Description

This module supports single-cycle misaligned word accesses.

Section 18 MSCAN Block Description

There are three MSCAN modules (CAN4, CAN1 and CAN0) implemented on the MC9S12DT256. Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module.

Section 19 Port Integration Module (PIM) Block Description

Consult the PIM_9DP256 Block User Guide for information about the Port Integration Module.

Section 20 Voltage Regulator (VREG) Block Description

Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
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Component Purpose Type Value
C1 VDD1 filter cap ceramic X7R 100 .. 220nF C2 VDD2 filter cap ceramic X7R 100 .. 220nF C3 VDDA filter cap ceramic X7R 100nF C4 VDDR filter cap X7R/tantalum >=100nF C5 VDDPLL filter cap ceramic X7R 100nF C6 VDDX filter cap X7R/tantalum >=100nF C7 OSC load cap C8 OSC load cap
C9 / C
S
C10 / C
C11 / C
R2 / R R3 / R
P
DC
R1 / R PLL loop filter res See PLL Specification chapter
B
S
Q1 Quartz
PLL loop filter cap PLL loop filter cap
DC cutoff cap
See PLL specification chapter
Colpitts mode only, if recommended by
quartz manufacturer
Pierce mode only
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed:
• Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 – C6).
• Central point of the ground star should be the VSSR pin.
• Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
• VSSPLL must be directly connected to VSSR.
• Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.
• Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
• Central power input should be fed in at the VDDA/VSSA pins.
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Figure 20-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator

C1
VDD1
VSS1
VDDX
C6
VSSX
VREGEN
VSSA
C3
VDDA
VSS2
C2
VDD2
84
VSSR
VDDR
C4
C9
R1
C5
C10
C11
VSSPLL VDDPLL
C8
C7
Q1
MC9S12DT256 Device User Guide — V03.07

Figure 20-2 Recommended PCB Layout for 80QFP Colpitts Oscillator

VDDX
C6
VSSX
VREGEN
VSSA
C3
VDDA
C1
VDD1
VSS1
VSSR
VDDR
C4
C9
R1
C5
C10
C8
C11
VSSPLL
VDDPLL
VSS2
C2
VDD2
C7
Q1
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Figure 20-3 Recommended PCB Layout for 112LQFP Pierce Oscillator

C1
VDD1
VSS1
VDDX
C6
VSSX
VREGEN
VSSA
C3
VDDA
VSS2
C2
VDD2
VSSR
VDDR
VDDPLL
C4
C9
R1
C5
C10
C8
R2
Q1
R3
VSSPLL
C7
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Figure 20-4 Recommended PCB Layout for 80QFP Pierce Oscillator

VDDX
C6
VSSX
VDD1
C1
VSS1
VREGEN
VSSA
C3
VDDA
VSS2
C2
VDD2
VSSR
VDDR
C4
C9
R1
C5
C10
R2
Q1
C8
VSSPLL
VDDPLL
VSSPLL
R3
C7
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Appendix A Electrical Characteristics

A.1 General

NOTE: The electrical characteristics given in this section are preliminary and should be
used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice.
This supplement containsthemost accurate electrical information for the MC9S12DT256 microcontroller availableatthe time ofpublication. The informationshould be consideredPRELIMINARYand issubject to change.
This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate.
NOTE: This classification is shown in the column labeled “C” in the parameter tables
where appropriate.
P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations.
T:
Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category.
D:
Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12DT256 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL as well as the digital core.
The VDDA, VSSA pairsuppliestheA/D converter and the resistor ladder of the internal voltage regulator.
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The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator.
VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL.
VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.
NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5
is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 5V I/O pins
Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently.
A.1.3.2 Analog Reference
This group is made up by the VRH and VRL pins.
A.1.3.3 Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL.
A.1.3.4 TEST
This pin is used for production testing only.
A.1.3.5 VREGEN
This pin is used to enable the on chip voltage regulator.
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A.1.4 Current Injection
MC9S12DT256 Device User Guide — V03.07
Power supply must maintain regulation within operating V operating maximum current conditions. If positive injection current (V
or VDD range during instantaneous and
DD5
in
>V
) is greater than I
DD5
DD5
, the injection current may flowoutofVDD5and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either V

Table A-1 Absolute Maximum Ratings

Num Rating Symbol Min Max Unit
SS5
or V
DD5
1
).
1 I/O, Regulator and Analog Supply Voltage 2
Digital Logic Supply Voltage
3
PLL Supply Voltage 4 Voltage difference VDDX to VDDR and VDDA 5 Voltage difference VSSX to VSSR and VSSA 6 Digital I/O Input Voltage 7 Analog Reference 8 XFC, EXTAL, XTAL inputs 9 TEST input
Instantaneous Maximum Current
10
Single pin limit for all digital I/O pins
Instantaneous Maximum Current
11
Single pin limit for XFC, EXTAL, XTAL
Instantaneous Maximum Current
12
Single pin limit for TEST
13 Storage Temperature Range
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
2
2
3
4
5
V
DD5
V
DD
V
DDPLL
∆
VDDX
∆
VSSX
V
V
RH,VRL
V
ILV
V
TEST
I
I
DL
I
DT
T
stg
-0.3 6.0 V
-0.3 3.0 V
-0.3 3.0 V
-0.3 0.3 V
-0.3 0.3 V
IN
D
-0.3 6.0 V
-0.3 6.0 V
-0.3 3.0 V
-0.3 10.0 V
-25 +25 mA
-25 +25 mA
-0.25 0 mA
– 65 155 °C
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2. The device contains an internal voltage regulator to generatethe logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to V
4. Those pins are internally clamped to V
5. This pin is clamped low to V
SSR
SSPLL
, but not clamped high. This pin must be tied low in applications.
SSX
and V
and V
DDPLL
DDX
.
, V
SSR
and V
DDR
or V
SSA
and V
DDA
.
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as afailure if after exposure to ESD pulses the device nolonger meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.

Table A-2 ESD and Latch-up Test Conditions

Model Description Symbol Value Unit
Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF
Human Body
Machine
Latch-up
Number of Pulse per pin positive negative
Series Resistance R1 0 Ohm Storage Capacitance C 200 pF Number of Pulse per pin
positive negative
Minimum input voltage limit -2.5 V Maximum input voltage limit 7.5 V
-
-
­3 3
­3 3

Table A-3 ESD and Latch-Up Protection Characteristics

Num C Rating Symbol Min Max Unit
1 C Human Body Model (HBM) 2 C Machine Model (MM) 3 C Charge Device Model (CDM)
Latch-up Current at TA = 125°C
4C
5C
positive negative
Latch-up Current at T positive
negative
= 27°C
A
V
V
V
HBM
MM
CDM
I
LAT
I
LAT
2000 - V
200 - V 500 - V
+100
-100
+200
-200
-mA
-mA
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A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data.
NOTE: Please refer to the temperature rating of the device (C, V, M) with regards to the
ambient temperature T calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics.
Rating Symbol Min Typ Max Unit
and the junction temperature TJ. For power dissipation
A

Table A-4 Operating Conditions

I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage PLL Supply Voltage
Voltage Difference VDDX to VDDR and VDDA Voltage Difference VSSX to VSSR and VSSA Oscillator Bus Frequency MC9S12DT256C
Operating Ambient Temperature Range
MC9S12DT256V
Operating Ambient Temperature Range
MC9S12DT256M
Operating Ambient Temperature Range
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source.
2. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the rela­tion between ambient temperature T
1
Operating Junction Temperature Range
Operating Junction Temperature Range
Operating Junction Temperature Range
1
and device junction temperature TJ.
A
V
DD5
V
DD
V
DDPLL
∆
VDDX
∆
VSSX
f
osc
f
bus
T
J
2
T
A
T
J
2
T
A
T
J
2
T
A
4.5 5 5.25 V
2.35 2.5 2.75 V
2.35 2.5 2.75 V
-0.1 0 0.1 V
-0.1 0 0.1 V
0.5 - 16 MHz
0.5 - 25 MHz
-40 - 100 °C
-40 27 85 °C
-40 - 120 °C
-40 27 105 °C
-40 - 140 °C
-40 27 125 °C
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (T obtained from:
)in°C can be
J
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MC9S12DT256 Device User Guide — V03.07
T T T P
Θ
The total power dissipation can be calculated from:
P
Two cases with internal voltage regulator enabled and disabled must be considered:
Junction Temperature, [°C]=
J
Ambient Temperature, [°C]=
A
Total Chip Power Dissipation, [W]=
D
JA
INT
1. Internal Voltage Regulator disabled
Package Thermal Resistance, [°C/W]=
Chip Internal Power Dissipation, [W]=
P
INT
I
⋅ I
DDVDD
T
J
P
D
DDPLLVDDPLL
A
P
D
P
INT
⋅ I
Θ
•()+=
JA
PIO+=
+V
DDA
⋅+=
DDA
2
I
P
IO
P
is the sum of all output currents on I/O ports associated with VDDX and VDDR.
IO
For R
respectively
2. Internal voltage regulator enabled
I
DDR
additionally contains the current flowing into the external loads with output high.
is valid:
DSON
R
DSON
V
R
DSON
P
INT
is the current shown in Table A-7 and not the overall current flowing into VDDR, which
DD5VOH
------------------------------------ for outputs driven high;=
I
DDRVDDR
P
IO
R
∑
i
V
OL
------------ for outputs driven low;= I
OL
–
I
OH
⋅ I
R
∑
i
DSON
DSON
⋅=
IO
i
⋅+=
DDAVDDA
2
I
⋅=
IO
i
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
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MC9S12DT256 Device User Guide — V03.07

Table A-5 Thermal Package Characteristics

1
Num C Rating Symbol Min Typ Max Unit
1T
2T
Thermal Resistance LQFP112, single sided PCB Thermal Resistance LQFP112, double sided PCB
with 2 internal planes
3
3 T Thermal Resistance LQFP 80, single sided PCB
4T
Thermal Resistance LQFP 80, double sided PCB with 2 internal planes
2
θ
JA
θ
JA
θ
JA
θ
JA
NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-2
3. PC Board according to EIA/JEDEC Standard 51-7
--54
--41
--51
--41
o
C/W
o
C/W
o
C/W
o
C/W
A.1.9 I/O Characteristics
This section describes the characteristics of all 5V I/O pins. All parameters are not alwaysapplicable, e.g. not all pins feature pull up/down resistances.
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MC9S12DT256 Device User Guide — V03.07

Table A-6 5V I/O Characteristics

Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 P Input High Voltage
T Input High Voltage
2 P Input Low Voltage
T Input Low Voltage
3 C Input Hysteresis
V
V V
V V
HYS
IH
IH
IL
IL
0.65*V
DD5
--V
- - VDD5 + 0.3 V
--
0.35*V
DD5
VSS5 - 0.3 - - V
250 mV
Input Leakage Current (pins in high impedance input
1
4P
5C
6P
7C
8P
9P
10 C
11 P
12 C
mode) Vin= V
DD5
or V
SS5
Output High Voltage (pins in output mode) Partial Drive IOH= –2mA
Output High Voltage (pins in output mode) Full Drive IOH = –10mA
Output Low Voltage (pins in output mode) Partial Drive IOL = +2mA
Output Low Voltage (pins in output mode) Full Drive IOL= +10mA
Internal Pull Up Device Current, tested at V
Max.
IL
Internal Pull Up Device Current, tested at V
IH
Min.
Internal Pull Down Device Current, tested at V
IH
Min.
Internal Pull Down Device Current, tested at V
Max.
IL
13 D Input Capacitance
2
14 T
Injection current Single Pin limit
Total Device Limit. Sum of all injected currents 15 P 16 P
Port H, J, P Interrupt Input Pulse filtered
Port H, J, P Interrupt Input Pulse passed
3
3
I
in
V
OH
V
OH
V
OL
V
OL
I
PUL
I
PUH
I
PDH
I
PDL
C
I
ICS
I
ICP
t
PULSE
t
PULSE
–2.5 - 2.5 µA
V
V
DD5
DD5
– 0.8
– 0.8
--V
--V
- - 0.8 V
- - 0.8 V
- - -130 µA
-10 - - µA
- - 130 µA
10 - - µA
in
-2.5
-25
6-pF
- 2.5 25
3 µs
10 µs
NOTES:
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temperature range from 50 C to 125 C.
2. Refer to Section A.1.4 Current Injection, for more details
3. Parameter only applies in STOP or Pseudo STOP mode.
V
mA
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MC9S12DT256 Device User Guide — V03.07
A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for the measurements.
A.1.10.1 Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input.
A.1.10.2 Additional Remarks
In expanded modesthecurrents flowing in the system are highly dependentonthe load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
97
MC9S12DT256 Device User Guide — V03.07
given. A very good estimate is to take the single chip currents and add the currents due to the external loads.

Table A-7 Supply Current Characteristics

Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1P
Run supply currents
Wait Supply current
2P
P
C P C C
3
P C P C P
Pseudo Stop Current (RTI and COP enabled)
C C C
4
C C C C
Stop Current
C P C C
5
P C P C P
Single Chip, Internal regulator enabled
All modules enabled, PLL on
only RTI enabled
Pseudo Stop Current (RTI and COP disabled)
"C" Temp Option 100°C "V" Temp Option 120°C
"M" Temp Option 140°C
2
"C" Temp Option 100°C
"V" Temp Option 120°C
"M" Temp Option 140°C
1, 2
-40°C 27°C 70°C 85°C
105°C 125°C
1, 2
-40°C 27°C 70°C 85°C
105°C 125°C 140°C
-40°C 27°C 70°C 85°C
105°C 125°C
I
DD5
I
DDW
1
65
40
5
mA
mA
370 400
500
450
I
DDPS
550 600
1600
µA
650 800
2100
850
1200
5000
570 600
I
DDPS
650 750
µA
850 1200 1500
12 25
100
100
I
DDS
130
160
1200
µA
200
350
1700 400 600
5000
NOTES:
1. PLL off
2. At those low power dissipation levels T
98
= TA can be assumed
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MC9S12DT256 Device User Guide — V03.07

A.2 ATD Characteristics

This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The Table A-8 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results:
V
≤ VRL≤ VIN≤ VRH≤ V
SSA
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped.

Table A-8 ATD Operating Characteristics

Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
Reference Potential
1D
2C 3 D ATD Clock Frequency
4D
5D
6D 7 P Reference Supply current 2 ATD blocks on 8 P Reference Supply current 1 ATD block on
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimumtime assumes a final sample periodof 2 ATD clocks cycles whilethe maximum time assumes a finalsample
Differential Reference Voltage
ATD 10-Bit Conversion Period
Conv, Time at 2.0MHz ATD Clock f
ATD 8-Bit Conversion Period
Conv, Time at 2.0MHz ATD Clock f
Recovery Time (V
period of 16 ATD clocks.
=5.0 Volts)
DDA
. This constraint exists since the sample buffer amplifier can not drive
DDA
Low
High
1
Clock Cycles
ATDCLK
Clock Cycles
ATDCLK
2
2
V
RL
V
RH
VRH-V
f
ATDCLK
N
CONV10
T
CONV10
N
CONV8
T
CONV8
t
REC
I
REF
I
REF
RL
V
V
DDA
SSA
/2
V
DDA
V
/2
DDA
4.50 5.00 5.25 V
0.5 2.0 MHz
14
7
12
6
28 14
26 13
20 µs
0.750 mA
0.375 mA
V V
Cycles
µs
Cycles
µs
A.2.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the ATD.
A.2.2.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R
S
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MC9S12DT256 Device User Guide — V03.07
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operatingconditionsare less thanworstcase or leakage-inducederror is acceptable,largervalues of source resistance is allowed.
A.2.2.2 Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage ≤ 1LSB, then the external filter capacitor, C
≥ 1024 * (C
f
INS
- C
INN
).
A.2.2.3 Current Injection
There are two cases to consider.
1. A current is injected into the channel being converted. The channel being stressed has conversion values of$3FF($FF in 8-bit mode) for analoginputsgreater than V
unless the current is higher than specified as disruptive condition.
V
RL
and $000forvalues less than
RH
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as V I
INJ
, with I
being the sum of the currents injected into the two pins adjacent to the converted
INJ
=K*RS*
ERR
channel.

Table A-9 ATD Electrical Characteristics

Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 C Max input Source Resistance
Total Input Capacitance
2T
3 C Disruptive Analog Input Current 4 C Coupling Ratio positive current injection 5 C Coupling Ratio negative current injection
Non Sampling Sampling
R
S
C
INN
C
INS
I
NA
K
p
K
n
--1KΩ
10 22
-2.5 2.5 mA
-4
10
-2
10
pF
A/A A/A
100
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