Motorola MC92500ZQ Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ATM Cell Processor
The ATM Cell Processor (MC92500) is a peripheral device composed of dedicated
high performance Ingress and Egress Cell Processors combined with UTOPIA
Compliant PHY and Switch Interface ports (see Figure 1).
MC92500 Features
• Full duplex operation at SONET STS-3c, SONET STS-1, DS3 PLCP, or any physical link
running up to 155 Mbit/sec
• Implements ATM Layer functions for broadband ISDN according to ITU recommendations
and ATM forum UNI specification
• Performs internal VPI and VCI address compression (with an option for external
compression) for up to 64K VCs
• Supports up to 16 physical links using dedicated Ingress/Egress MultiPhy control signals
• Each physical link can be configured as either a UNI or NNI port
• Supports multicast, multiport address translation
• Maintains both virtual connection and physical link counters on both Ingress and Egress
cell flows for detailed billing and diagnostics
• Provides a flexible 32 bit external memory port for context management
• Automated AIS, RDI, CC and Loopback functions with Performance Monitoring Block Test
on up to 64 Bidirectional connections
• Programmable 32 bit microprocessor interface supporting either big- or little-endian bus
formats
• Per-connection leaky-bucket based UPC or NPC design with up to four buckets per
connection allows any combination of CLP-aware peak, average, and burst-length
policing with programmable tag/drop action per policer
• Implements separate rate controlled cell insertion and priority based cell extraction
queues accessible from all cell flows
• Supports a programmable number of additional switch overhead parameters allowing
adaptation to any switch routing header format
Order this document by MC92500/D
ΤΜ
MC92500
ATM Cell Processor
ZQ SUFFIX
GTBGA
CASE 5203
Ordering Information
Device
MC92500ZQ
Package
256 GTBGA
Utopia
I/F
Host
System
Utopia
I/F
Ingress PHY I/F (IPHI)
MultiPhy Support
Microprocessor I/F
(MPIF)
Egress PHY I/F (EPHI)
MultiPhy Support
Ingress Cell Processor
(IPU)
External Memory I/F
(EMIF)
Internal SCAN
(ISCAN)
Egress Cell Processor
(EPU)
FMC Generation
(FMC)
Figure 1. Representative Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
MOTOROLA, INC. 1997
REV 1.1
Ingress Switch I/F
(ISWI)
JTAG
Boundary
Scan
Egress Switch I/F
(ESWI)
Utopia
I/F
Memory
I/F
Test
Port
Utopia
I/F
TABLE OF CONTENTS
1. ATM NETWORK
1.1 ATM Network Description ................................... 3
1.2 ATM Network Applications ................................. 4
2. FUNCTIONAL DESCRIPTION
2.1 System Functional Description .......................... 5
2.2 MC92500 Functional Description ....................... 5
2.2.1 Ingress Cell Flow ......................................... 6
2.2.2 Egress Cell Flow .......................................... 6
2.3 Other Functions ................................................. 7
2.4 MC92500 Block Diagram ................................... 7
2.4.1 Ingress PHY Interface (IPHI) ....................... 8
2.4.2 Ingress Cell Processing Unit (IPU) .............. 8
2.4.3 Ingress Switch Interface (ISWI) ................... 8
2.4.4 Egress Switch Interface (ESWI) ................... 8
2.4.5 Egress Cell Processing (EPU) ..................... 8
2.4.6 Egress PHY Interface (EPHI) ....................... 9
2.4.7 External Memory Interface (EMIF) ............... 9
2.4.8 Microprocessor Interface (MPIF) ................. 9
2.4.9 Internal Scan (ISCAN) ................................. 9
2.4.10 Forward Monitoring Cell Generation(FMC) 9
3. REGISTERS DESCRIPTION
3.1 MC92500 Registers ........................................... 9
4. EXTERNAL MEMORY DESCRIPTION
6.2 Interface to Physical Layer - Cell Assembly .....18
6.3 Address Compression ...................................... 19
6.4 Cell Counting .................................................... 19
6.5 Ingress Cell Insertion .......................................20
6.6 Switch Overhead Information ........................... 20
6.7 Transfer to Switch .............................................20
7. EGRESS DATA PATH OPERATION
7.1 Egress Data Path .............................................20
7.1.1 Transfer from Switch ...................................21
7.1.2 Multicast Identifier Translation .................... 22
7.1.3 Egress Cell Insertion .................................. 22
7.1.4 Address Translation .................................... 22
7.1.5 Cell Counting .............................................22
7.1.6 Transmission to Physical Layer .................. 22
8. SYSTEM OPERATION
8.1 MC92500 Modes of Operation......................... 23
8.1.1 Setup Mode ................................................ 23
8.1.2 Operate Mode ............................................23
8.1.3 Reset .......................................................... 23
8.2 Data Path Clock Configuration .........................23
4.1 MC92500 External Memory ............................. 11
4.1.1 Memory Partitioning ................................... 11
5. SIGNAL DESCRIPTION
5.1 Functional Signal Groups ................................. 13
5.2 Ingress PHY Signals ........................................ 13
5.3 Egress PHY Signals ......................................... 14
5.3.1 Ingress Switch Interface Signals ................ 14
5.3.2 Egress Switch Interface Signals ................ 15
5.4 External Memory Signals ................................. 15
5.4.1 Control Signals .......................................... 16
5.4.2 Microprocessor Signals (MP)..................... 16
5.4.3 Clock Signals ............................................. 17
5.4.4 JTAG Interface Test Signals ....................... 17
6. INGRESS DATA PATH OPERATION
6.1 Ingress Data Path ............................................ 17
9. ELECTRICAL CHARACTERISTICS
9.1 Electrical Specifications ...................................24
9.1.1 Clocks ........................................................ 24
9.1.2 Microprocessor Interface Timing................ 25
9.1.3 PHY Interface Timing .................................32
9.1.4 Switch Interface Timing .............................. 33
9.1.5 External Memory Interface Timing............. 34
9.1.6 Write Cycle Timing ..................................... 34
9.1.7 Read Cycle Timing ..................................... 35
9.1.8 DC Electrical Characteristics .....................36
10. PACKAGE INFORMATION
10.1 Pin Assignment .............................................. 38
10.2 256 PBGA Case Outline .................................39
MOTOROLA MC92500
2
1. ATM NETWORK
1.1 ATM Network Description
A typical ATM network consists of user end stations
that transmit and receive 53-byte data cells on virtual
connections (see Figure 1). The virtual connections are
implemented using physical links and switching systems that interconnect them. The specific combination
of physical links that implements a virtual connection is
chosen when the connection is established. On a given
physical link, each connection is assigned a unique
connection identifier. The connection identifier is
placed in the header of each cell by the transmitting
equipment and is used by the receiving equipment to
route the cell to the next physical link on the connection
path. All cells belonging to a specific virtual connection
follow the identical path from the transmitting end station through the switching systems to the receiving end
station.
Each switching system handles multiple physical links
and transfers each arriving ATM cell from its source link
to its destination link according to the pre-arranged
routing for the connection to which the cell belongs. The
switching system consists of a switch fabric, which handles the actual routing of the cells, and a line card for
each physical link (or group of links) to interface between the physical medium and the switch fabric. The
line card recovers incoming cells from the arriving bit
stream and converts outgoing cells into a bit stream for
transmission.
ATM standards divide the tasks to be performed on
each side of the switch fabric into PHY-layer and ATMlayer tasks. The PHY-layer tasks are dependent on the
physical medium used to connect the switching
systems, while the ATM-layer tasks operate at the cell
level and are independent of the physical medium.
Therefore, it is logical to implement the PHY-layer and
ATM-layer functions on separate devices. In this case
the line card appears as in Figure 2. There are one or
more PHY-layer devices, an ATM-layer device, and
clock recovery devices to clock the PHY devices in
accordance with the signals arriving on the physical
media.
End
Stations
Switch
Clk Rec
Switch
Line
Card
PHY
Switch
Switch Switch Switch
Switching Fabric
MC92500
ATM Layer Functions
Switch
Line Card
VCsVCs
End
Stations
Line
Card
Figure 2. MC92500 in an ATM Network Application
MC92500 MOTOROLA
3
1.2 ATM Network Applications
The MC92500, an Asynchronous Transfer Mode cellprocessing device, is ideally suited for use in the interface between a PHY-layer device and an ATM switch
fabric. The primary application of the MC92500 is ATMlayer cell processing and routing.
Figure 3 illustrates a typical ATM line card using the
MC92500 device. The MC92500 uses an external
memory for storing the ATM virtual connections of the
cells it processes. In addition, the MC92500 offers an
option to utilize an external address compression device accessed via the same external memory bus.
The microprocessor is used for configuration, control
and status monitoring of the MC92500 and is responsible for initializing and maintaining the external memory.
The MC92500 is the master of the external memory
bus. At regular intervals the MC92500 allows the microprocessor to access the external memory for updating
and maintenance.
System RAM can also be located on the line card. The
MC92500 can support a DMA device to allow efficient
data transfer to this RAM without processor intervention.
The physical interface (PHY-IF) implements the physical layer functions of the B-ISDN Protocol Reference
Model.This includes the physical medium dependent
functions required to transport ATM cells between the
ATM user and the ATM switch (UNI) or between two
ATM switches (NNI). The cells are transferred between
the physical interface and the MC92500 using the
UTOPIA standard.
The MC92500 implements B-ISDN UNI/NNI ATM-layer
functions required to transfer cells to and from the
switch over virtual connections. These functions
include usage enforcement, address translation, and
Operation and Maintenance (OAM) processing.The
MC92500 provides context management for up to 64K
Virtual Connections (VCs). The VCs can be either
Virtual Path Connections (VPCs) or Virtual Channel
Connections (VCCs). ATM cells belonging to a
particular VCC on a logical link have the same unique
Virtual Path Identifier/Virtual Channel Identifier,
(VPI/VCI) value in the cell header. Similarly, cells
belonging to a particular VPC on the same logical link
share a unique VPI.
RAM
RAM
LINE CARD
Microprocessor
Bus
Clock
Recovery
µP
µP
PHY-IF
PHY-IF
PHY-IF
DMA
DMA
MC92500
Figure 3. Typical MC92500 Line Card Application
External
Ext-MEM
Memory
External
Memory
Bus
External
Ext
Address
Addr
Compression
Comp
to switch
from switch
MOTOROLA MC92500
4
2. FUNCTIONAL DESCRIPTION
2.1 System Functional Description
A serial transmission link operating at up to 155.52Mbit/
sec (PHY) is coupled to the MC92500 via a byte-based
interface. The transmission link timing is adapted to the
MC92500 and switch timing by means of internal FIFO
cell buffers. A common clock is used to supply both the
PHY-IF and MC92500.
The host microprocessor initializes and provides realtime control of the data-flow chips (PHY-IF and
MC92500) using slave accesses.
The MC92500 operates in conjunction with an external
connection memory, which provides one context entry
for each active connection. The entry consists of two
types of context parameters: static and dynamic. The
static parameters are loaded into the context memory
when the VC is established, and are valid for the duration of that connection. Included in the static parameters are traffic descriptors, OAM flags and parameters
used by the ATM switch. The dynamic context parameters, which include cell counters, UPC/NPC fields and
OAM parameters, may be modified as cells belonging
to that particular connection are processed by the
MC92500. The microprocessor also accesses the external memory through the MC92500 from time to time
to collect traffic statistics and to update the OAM parameters. During normal cell processing, the MC92500
has exclusive access to the external memory. The context entries for the cells being processed are read and
the updated dynamic parameters are written back. The
MC92500 is responsible for the coherency of the external memory during this time.
At user-programmable intervals the MC92500 provides
the microprocessor with a “maintenance slot”, during
which no cell processing is done, and relinquishes the
external memory bus. The break in cell processing is
made possible by the difference between the MC92500
cell-processing rate and the line rate.
The maintenance slot shall be used by the microprocessor for one or more of the following tasks:
• Connection setup and tear down
• Statistics collection
• Updating OAM parameters of active
connection
The microprocessor is responsible for the coherency of
the external memory at the end of each maintenance
slot.
2.2 MC92500 Functional Description
MC92500 General Features
• Implements ATM Layer functions for Broadband
ISDN according to CCITT recommendations and
ATM forum user network interface specifications
• Provides a throughput capacity of up to 155 Mbit/
sec in each direction
• Processes ATM cells from a SONET STS-3c,
SONET STS-1, DS3 PLCP, or any other physical
link running at up to 155 Mbit/sec
• Optionally supports up to 16 physical links
• Optionally configured as a User Network Interface
(UNI) or Network Node Interface (NNI) on a per-link
basis
• Operates in conjunction with an external memory
(up to 16 MB) to provide context management for
up to 64K Virtual Connections
• Provides explicit bank select signals to support up
to four banks of external memory
• Provides per-connection cell counters with the ability to maintain multiple copies of the counter tables
and dynamically switch between them
• Provides per-link cell counters in both directions
• Provides per-connection Usage Parameter Control
(UPC) or Network Parameter Control (NPC) using
a leaky bucket design with up to four buckets per
connection
• Provides support for Operation and Maintenance
(OAM) Continuity Check function for all connections
• Supports Virtual Path (VP) and Virtual Channel
(VC) level Alarm Surveillance on all connections
using an internal scan process to generate and
insert OAM cells
• Supports OAM Fault Management Loopback test
on all connections
• Supports bidirectional OAM Performance Monitoring on up to 64 connections
• Provides a slave microprocessor interface including a 32-bit data bus
• Provides byte-swapping on cell payloads to and
from the microprocessor bus in order to support
both big-endian and little-endian buses
• Supports cell insertion into the cell streams using
direct access registers which may be written by the
microprocessor or by a DMA device
• Supports copying cells from the cell streams using
direct access registers which may be read by the
microprocessor or by a DMA device
• Supports multicast operation
MC92500 MOTOROLA
5
2.2.1 Ingress Cell Flow
In the Ingress direction, the MC92500 extracts cells
from the FIFO in the PHY. Cell discrimination based on
pre-defined header field values is performed to recognize unassigned and invalid cells. Cell rate decoupling
is accomplished by discarding unassigned cells. Unassigned and invalid cell slots may be used to insert OAM
and messaging cells into the Ingress cell flow. For
VCCs, the 28-bit VPI/VCI address space (32-bit Link/
VPI/VCI if multiple physical links are supported) needs
to be compressed into a 16-bit Ingress Connection
Identifier (ICI). The MC92500 provides a choice of two
methods for performing VCC address compression to
obtain the ICI: a table lookup based on reduced addressing and an external address compression option.
For VPCs, the VPI field is used for a lookup into the
VP Table to obtain the ICI. The ICI is a pointer used to
access the context parameters for the current Ingress
cell from the external context memory. Included in
these parameters are cell counters, UPC/NPC traffic
descriptor, OAM parameters and switch parameters.
The UPC/NPC mechanism entails counting the arriving
cells and, using a flexible arrangement of traffic enforcement algorithms, admitting cells that do not violate
the traffic characteristics established for that connection. Violating cells are tallied and may optionally be
tagged or discarded (removed from the cell flow).
• Provides either a restricted address table
lookup scheme for Ingress address
compression or support for an external address
compression mechanism
• Reads Virtual Connection related UPC/NPC,
OAM and switch context parameters through a
32-bit wide interface to an external memory
• Provides per-connection usage count
• Provides per-connection option to copy cells to
the microprocessor
• Provides per-connection UPC/NPC policing
including detection/counting of violating cells
• Supports OAM continuity check, alarm
surveillance and loopback test on all
connections
• Provides OAM performance monitoring test
capabilities for selected connections
• Supports insertion of cells into the ingress cell
flow
• Optionally performs VPI/VCI translation
• Forwards the received ATM cells to the switch
using a UTOPIA-style interface, optionally
adding associated internal switch context
parameters
• Delay of 3 - 5 cell times from the PHY to the
switch
The OAM flags are used to control when and how OAM
cells are processed and to determine if the current user
cell belongs to a connection that has been selected for
a performance monitoring test. If the Ingress cell belongs to such a connection, the OAM table in external
memory contains the relevant parameters.
Subsequent to the context processing, the Ingress cells
are transferred to the Ingress switch
ally, the associated switch context parameters may be
added to the cell before the header or placed in the VPI/
VCI fields of the header.
Ingress Features
The Ingress section (Ingress refers to cells being transferred from the physical interface to the switch):
• Interfaces to one or more physical interface
chips via an 8-bit wide, parity-protected receive
data bus using the UTOPIA standard
• Decouples PHY timing from switch timing using
independent clocks and a FIFO in the physical
interface
• Performs Ingress cell discrimination based on
pre-assigned ATM cell header values
interface. Option-
2.2.2 Egress Cell Flow
In the Egress direction, the MC92500 receives cells
from the switch along with their associated parameters,
if any. One of these parameters is the Egress Connection Identifier (ECI), which is used for direct lookup into
the context table located in external memory to obtain
the VPI/VCI, cell counters, and OAM flags. If multicast
translation is enabled, the Multicast Identifier (MI) is received from the switch instead of the ECI, and the ECI
is found in the multicast translation table. Cells are subject to processing as indicated by the OAM flags. If the
Egress cell belongs to a connection that has been selected for a performance monitoring test, the OAM Table in external memory contains the relevant
parameters.
The Egress cell header is generated by inserting the
VPI/VCI-field obtained from the Address Translation
Table in the (GFC)/VPI/VCI position and modifying the
PTI-field if and when so indicated by the switch or in
case of an OAM cell. The cell is then forwarded to the
PHY I/F queue. Cell rate decoupling is performed in the
Egress direction, i.e. unassigned cells are optionally
generated if no cells are available from the switch.
MOTOROLA MC92500
6
Egress Features
The Egress section (Egress refers to cells being transferred from the switch to the physical interface):
• Receives ATM cells and associated switch
context parameters (including congestion
notification) from the switch using a UTOPIAstyle interface
• Provides optional multicast identifier to
connection identifier translation
• Reads Egress context parameters from
external memory using direct lookup
• Provides per-connection usage count
• Provides per-connection option to copy cells to
the microprocessor
• Supports OAM continuity check, alarm
surveillance and loopback test on all
connections
• Provides OAM performance monitoring test
capabilities for selected connections
• Supports insertion of cells into the egress cell
flow
• Performs VPI/VCI translation
• Transfers ATM cells to one or more physical
interfaces via an 8-bit wide, parity-protected
transmit data bus using the UTOPIA standard
• Decouples PHY timing from switch timing using
independent clocks and a FIFO in the physical
interface
• Delay of 3 - 5 cell times from the switch to the
PHY
2.3 Other Functions
A general 32-bit slave system interface is provided for
configuration, control, status monitoring, and insertion
and extraction of cells. This interface provides for direct
register access to the MC92500.
The MC92500 is equipped with a standard IEEE
1149.1 boundary scan test logic.
2.4 MC92500 Block Diagram
Figure 4 contains a block diagram of the MC92500. The
individual blocks will be described in this section.
Utopia
I/F
Host
System
Utopia
I/F
Ingress PHY I/F (IPHI)
MultiPhy Support
Microprocessor I/F
(MPIF)
Cell Insertion
Cell Extraction
Configuration Regs.
Maintenance Access
Egress PHY I/F (EPHI)
MultiPhy Support
Ingress Cell Processor (IPU)
VP and VC Address compression
NPC/UPC
Cell Counting
OAM Operations
Add Switch parameters
Microprocessor Cell Insertion
Microprocessor Cell Extraction
External Memory I/F
(EMIF)
Internal SCAN
(ISCAN)
Egress Cell Processor (EPU)
Multicast Translation
Cell Counting
OAM Operations
Address Translation
Microprocessor Cell Insertion
Microprocessor Cell Extraction
FMC Generation
(FMC)
Ingress Switch I/F
(ISWI)
Independent Clock
JTAG
Boundary
Scan
Egress Switch I/F
(ESWI)
Independent Clock
Extract Overhead
Utopia
I/F
Memory
I/F
Test
Port
Utopia
I/F
Figure 4. MC92500 Block Diagram
MC92500 MOTOROLA
7
2.4.1 Ingress PHY Interface (IPHI)
The Ingress PHY Interface (IPHI) block receives cells
on a byte basis from the ATM PHY layer using the
UTOPIA standard interface. It assembles the cells and
synchronizes their arrival to the MC92500 cell processing slots. Unassigned and invalid cells (Table 1 and Ta-
ble 2) are removed to provide cell rate decoupling. Also,
the MC92500 can process cells at a higher rate than
the PHY provides them, thereby creating “holes” in the
cell flow. These can be used for either cell insertion or
for maintenance access (used by the microprocessor to
maintain external memory).
2.4.2 Ingress Cell Processing Unit (IPU)
The Ingress Cell Processing Unit (IPU) operates at a
rate of one cell per cell processing slot. The cell may
have arrived from the IPHI block or may be inserted
from the Microprocessor Interface or Internal Scan
blocks. The Ingress OAM function may also insert PM
Forward Monitoring cells into the Ingress cell flow. A
cell may be inserted when an unused cell slot is available, subject to pacing by a simple leaky bucket algorithm.
The IPU performs address compression on cells that
arrived from the IPHI block in order to associate the cell
with Context Table records in External Memory. The
address compression function detects inactive cells
(cells with no corresponding records in the Context Table).
UPC/NPC is performed on a connection basis or optionally on arbitrary groups of connections. The UPC/
NPC function may detect violating cells as dictated by
the selected UPC/NPC algorithm. Violating cells will
normally be tagged or discarded from the cell flow, but
an option exists to perform the UPC/NPC algorithm for
statistical purposes only without modifying or removing
the cells.
OAM processing is performed where appropriate. The
Ingress OAM function records OAM alarm cells: Alarm
Indication Signal/Remote Defect Indicator (AIS/RDI).
OAM processing for user cells involved in a performance monitoring block test involves computing the
Bit-Interleaved Parity (BIP) and updating the Total User
Cells (TUC) count. For OAM cells the processing may
include overwriting the values of specific fields and
checking or generating the CRC-10 field.
Switch-specific overhead information is read from the
context entry and added to the cell before it is sent on
to the switch interface block. Address translation may
optionally be performed at this point.
The IPU will remove from the cell flow any OAM cell
that has reached its endpoint. Also, certain cells may be
copied to the MPIF for transfer to the microprocessor.
2.4.3 Ingress Switch Interface (ISWI)
The ISWI block contains a cell FIFO. Cells are received
from the IPU. When a full cell has been transferred, the
overhead information needed by the switch (as programmed by the user) is extracted from the internal
data structure along with the ATM header and payload
of the cell. This information is transferred to the switch
at the rate of one byte per clock cycle.
2.4.4 Egress Switch Interface (ESWI)
The ESWI block contains a cell FIFO. Data is received
from the switch at the rate of one byte per clock cycle.
The data structure received from the switch includes
overhead routing information in addition to the ATM
cell. When a full cell has been transferred, it is transformed into an internal data structure and presented to
the EPU for processing.
2.4.5 Egress Cell Processing (EPU)
The Egress Cell Processing Unit (EPU) operates at the
rate of one cell per cell processing slot. The cell may
arrive from the Egress Switch Interface Block or may be
inserted from the Microprocessor Interface or Internal
Scan Blocks. The Egress OAM function may also insert
PM Forward Monitoring cells into the Egress cell flow.
The cell insertion is paced by a simple leaky bucket algorithm.
The first stage of the Egress cell processing is performing multicast translation, if needed. Then the EPU performs OAM processing where appropriate. The Egress
OAM function records OAM Alarm cells. OAM processing for user cells involved in a Performance Monitoring
block test is limited to computing the bit-interleaved parity and updating the Total User Cells count. For OAM
cells the processing may include over-writing the values
of specific fields and checking or generating the CRC10 field.
Address translation is performed to replace the address
fields of the ATM cell header with the address of the
outgoing link.The EPU will remove from the cell flow
any OAM cell that has reached its endpoint. Also, certain cells may be copied to the MPIF for transfer to the
microprocessor.
MOTOROLA MC92500
8
2.4.6 Egress PHY Interface (EPHI)
The Egress PHY Interface (EPHI) block takes the processed cells from the EPU, disassembles them into
bytes and transfers them to the physical layer using the
UTOPIA standard interface. Unassigned cells may be
inserted to provide cell rate decoupling.
2.4.7 External Memory Interface (EMIF)
The External Memory Interface (EMIF) block performs
address generation for the MC92500 accesses to the
external memory. It provides 32-bit data and 22-bit address lines along with standard memory control signals.
2.4.8 Microprocessor Interface (MPIF)
The Microprocessor Interface (MPIF) block provides for
configuration of the MC92500, the transfer of cells between the microprocessor and the MC92500, and the
maintenance of external memory. A generic 68xxx compatible 32-bit slave interface is provided for easy
connection to a variety of microprocessor buses. Output signals are provided that can serve as request signals for up to three DMA devices to improve system
performance.
Cells to be inserted in the Ingress or Egress flows are
transferred from the processor memory to an internal
insertion queue.
2.4.9 Internal Scan (ISCAN)
The Internal Scan (ISCAN) block scans the external
memory for connections on which AIS, RDI, or Continuity Check (CC) OAM cells must be inserted. When such
a connection is found, the cells are generated and added to the insertion queue for the cell flow in the appropriate direction.
2.4.10 Forward Monitoring Cell Generation
(FMC)
The Forward Monitoring Cell (FMC) Generation block
keeps track of the connections on which FMCs are
pending during the course of a Performance Monitoring
block test and maintains a priority among them. When
a hole in the cell flow is available, this block requests
the insertion of an FMC on the highest-priority connection.
A cell extraction queue is used to store cells that are directed to the processor. Cells in this queue are transferred first to an internal cell buffer. Then they may be
read by the processor.
3. REGISTERS DESCRIPTION
3.1 MC92500 Registers
The MC92500 registers are divided into several
groups. The register groups are:
Status Reporting Registers - these registers report on
the MC92500 status, and generally may be read and
written by the processor in either of the MC92500
modes of operation (Setup Mode or Operate Mode).
Control Registers - these registers control the
MC92500 operation, and may be read and written by
the processor in either of the MC92500 modes of operation (Setup Mode or Operate Mode).
Configuration Registers - these registers are used to
define the MC92500 configuration, and may be read by
the processor in either of the MC92500 modes of operation (Setup Mode or Operate Mode). These registers
may be written by the processor only in Setup Mode of
operation.
Cell Insertion Registers - these registers are used for
cell insertion into the MC92500 cell flow, and may be
written by the processor when the MC92500 is in Operate Mode. In order to improve performance, the
MC92500 Cell Insertion Registers receive special treatment and may be accessed without wait states.
Cell Extraction Registers - these registers are used for
copying cells from the MC92500 cell flows, and may be
read by the processor when the MC92500 is in Operate
Mode. In order to improve performance, the MC92500
Cell Extraction Registers receive special treatment and
may be accessed without wait states.
Pseudo Registers - these registers are used to perform
certain operations on the MC92500, and may be written
by the processor in either of the MC92500 modes of operation (Setup Mode or Operate Mode).
MC92500 MOTOROLA
9
External Address Compression Device - this memory
space may be used by the processor to access the external address compression device. The External
Address Compression Device may be accessed when
the MC92500 is in Setup Mode or during maintenance
slots.
External Memory - this memory space may be used by
the processor to access the External Memory. If the “De-
ADD (25:0)
0000000
Cell Insertion
0010000
Alt. Cell Insertion
0020000
Cell Extraction
0030000
General Registers
0030FFF
structive” memory space is used, the MC92500 will automatically provide a write-back of zeros to each
External Memory location that is read. The External
Memory may be accessed when the MC92500 is in Setup Mode or during maintenance slots.
Figure 5 presents the MC92500 memory space addres-
sable by the microprocessor using the MADD bus.
Status Reporting
Control Registers
Configuration Registers
1000000
2000000
3000000
3FFFFFF
Pseudo Registers
External Address
Compression Device
External Memory
(Non-“Destructive”)
External Memory
(“Destructive”)
Figure 5. MC92500 Processor Memory Map
MOTOROLA MC92500
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4. EXTERNAL MEMORY DESCRIPTION
4.1 MC92500 External Memory
The MC92500 uses external memory to store the database (context information) relating to the processing of
cells on a per-connection basis. The MC92500 can access External Memory with 16- or 32-bit data.
4.1.1 Memory Partitioning
The External memory is partitioned into several tables:
(see Figure 6)
• Ingress Billing Counters - consists of a record for
each active connection. The record contains the
cell counters that are used by the connection during the normal Ingress cell flow. This table is dynamic and updated by the MC92500. The
microprocessor is responsible for collecting the
contents of the counters on a regular basis.
• Egress Billing Counters - consists of a record for
each active connection. The record contains the
counters that are used by the connection during the
normal Egress cell flow. This table is dynamic and
updated by the MC92500. The microprocessor is
responsible for collecting the contents of the
counters on a regular basis.
Flags Table - consists of a record for each active
•
connection. The record contains OAM flags that
are used by all the connections during the normal
cell flow. This table is dynamic and updated by the
MC92500
checking the flags on a regular basis
• Context Parameters Table - consists of a record for
each active connection. The record contains connection-specific information for processing and
routing the cells belonging to the connection.
• Ingress Policing Counters - consists of a record for
each active connection. The record contains the
counters that are used to record the results of the
UPC/NPC policing. This table is dynamic and updated by the MC92500. The microprocessor is responsible for collecting the contents of the counters
on a regular basis.
. The microprocessor is responsible for
• VC Table - contains a list of all the Ingress Connection Identifiers (ICIs) that have been defined by the
microprocessor as active Virtual Channel Connections. This table exists only if the Table Lookup
method of Address Compression is used with VC
Table Lookup enabled.
• Multicast Translation Table - contains the Egress
Connection Identifiers (ECIs) associated with the
multicast identifiers.
• OAM Table - contains the additional information
required to run OAM Performance Monitoring.
• VP Table(s) - each record contains an Ingress Connection Identifier (ICI) that has been defined by the
microprocessor as an active connection. The size
and location of the VP Table(s) are determined by
the Link Register. If multiple links are supported,
each Link Register defines a separate VP Table.
The multiple VP Tables are not required to be contiguous.
• Dump Vector Table - contains the dump vectors
describing the recent history of the cell processing.
This table is generally only used for debugging
purposes.
• Egress Link Counters - consists of a record for
each link. The record contains the cell counters that
are used by the link during the normal Egress cell
flow. This table is dynamic and updated by the
MC92500. The microprocessor is responsible for
collecting the contents of the counters on a regular
basis.
• Ingress Link Counters - consists of a record for
each link. The record contains the cell counters that
are used by the link during the normal Ingress cell
flow. This table is dynamic and updated by the
MC92500. The microprocessor is responsible for
collecting the contents of the counters on a regular
basis.
• Virtual Bucket Table - each record in this table contains the information for the UPC/NPC enforcement. This is not a physical table, but a virtual one.
Since the Parameters Table contains a full address
for the location of the Bucket record of each connection, there is no need to put all the Bucket
records in consecutive physical locations. Although
the user can distribute the records in any manner.
MC92500 MOTOROLA
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Ingress Billing Counters Table pointer
Egress Billing Counters Table pointer
Flags Table pointer
Context Parameters Table pointer
Ingress Policing Counters Table pointer
VC Table pointer
32 bits
Ingress Billing
Counters Table
Egress Billing
Counters Table
Flags Table
Context
Parameters Table
Ingress Policing
Counters Table
Multicast Table pointer
OAM Table pointer
VP Table pointer
Dump V ector Table pointer
Egress Link Counters Table pointer
Ingress Link Counters Table pointer
Bucket pointer
Figure 6. External Memory Partitioning
VC Table
Multicast Table
OAM Table
VP Table(s)
Dump V ector Table
Egress Link
Counters Table
Ingress Link
Counters Table
Virtual Bucket Table
MOTOROLA MC92500
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5. SIGNAL DESCRIPTION
5.1 Functional Signal Groups
This section contains brief descriptions of the input and
output signals in their functional groups, as shown in
Figure 7. Each signal is explained briefly.
CONTROL
PROCESSOR
INTERFACE
INGRESS
PHY
INTERFACE
EGRESS
PHY
INTERFACE
ENID
AMODE(0-1)
MCLK
MADD(2-25)
MWR
MSEL
MDS
MWSH
MWSL
MDTACK
MDATA(0-31)
MINT
MCIREQ
MCOREQ
EMMREQ
RXDATA(0-7)
RXPRTY
RXSOC
RXEMPTY
RXENB
RXPHYID(0-3)
TXFULL
TXDATA(0-7)
TXPRTY
TXSOC
TXENB
TXCCLR
TXPHYID(0-3)
TXPHYIDV
MC92500
5.2 Ingress PHY Signals
The following signals relate to the PHY interface that is
connected to the PHY chip(s) using the UTOPIA standard. All of the input signals are sampled at the rising
edge of ACLK, and all of the output signals are updated
at the rising edge of ACLK.
ACLKARST
TESTSEL
TESTOUT
VCOCTL
EMDATA(0-31)
EMADD(2-23)
EMWR
EMBSH(0-3)
EMBSL(0-3)
EACEN
SRXDATA(0-7)
SRXPRTY
SRXSOC
SRXCLAV
SRXENB
SRXCLK
STXCLAV
STXDATA(0-7)
STXPRTY
STXSOC
STXENB
STXCLK
TCK
TMS
TDI
TRST
TDO
CLOCK
EXTERNAL
MEMORY
INTERFACE
INGRESS
SWITCH
INTERFACE
EGRESS
SWITCH
INTERFACE
JTAG
INTERFACE
Figure 7. Functional Signal Groups
MC92500 MOTOROLA
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