MOTOROLA MC92314 User Manual
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DVB-T Single Chip Demodulator
Freescale Semiconductor, Inc.
MC92314
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Application Note
Authors
Christoph Patzelt (Motorola),
Adrian Turner (NDS)
(Single Chip DVB-T Demodulator)
Rev. 1.3
Date: November 30, 1998 3:37 pm
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola a ssume any liability arising out of the application or use of any product or c ircuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including
“Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the
rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustainlife,orforanyotherapplicationinwhich the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
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Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
MOTOROLA, INC. 1997 All Rights Reserved
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Rev. 1.3
Revision Status:
Version 1.2 Finalised.
Summary of Changes or Updates:
• Significant reduction in external intervention.
Rev. 1.1:
• Changes to VCXO LPF included.
Rev. 1.2:
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• Added CSE register to OFDM block register map.
• Added AGC Fix and VCXO Fix descriptions.
Rev. 1.3:
• Included performance values and power consumption values.
• Included suggestions to speed up acquisition (AFC Sweep Start, fixing FEC coderate).
• Added Timing Diagram
• Added BGA package information
• Added VCXO tolerance requirement
Trademarks:
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Single Chip DVB-T Demodulator
Table of Contents
Section 1
SYSTEM OVERVIEW
1.1 General Description............................................................................................1-1
1.2 Considerations on Terrestrial Transmission.......................................................1-2
1.2.1 Echoes on the Transmission Path.................................................................1-2
1.2.2 Noise.............................................................................................................1-3
1.3 Advantages of the OFDM Transmission Scheme...............................................1-3
1.4 Overview of the DVB-T System..........................................................................1-4
1.4.1 Modulation Scheme.......................................................................................1-4
1.4.2 OFDM Block..................................................................................................1-6
1.4.3 FFT Block......................................................................................................1-6
1.4.4 Forward Error Correction Block.....................................................................1-6
1.4.4.1 Viterbi Decoder...................................................................................1-6
1.4.4.2 Convolutional Deinterleaver ...............................................................1-7
1.4.4.3 Reed-Solomon Decoder.....................................................................1-7
1.4.4.4 Energy Dispersal Removal (Descrambling)........................................1-7
1.5 References .........................................................................................................1-8
Section 2
PINOUT & SIGNAL DESCRIPTION OF THE MC92314
2.1 Pinout for the 160PQFP Package.......................................................................2-2
2.2 Pinout for the 169BGA Package.........................................................................2-3
2.3 Pin Description of the Single Chip DVB-T Demodulator MC92314....................2-4
Preliminary Information
Section 3
DEVICE DESCRIPTION
3.1 Complete DVB-T Digital Frontend......................................................................3-1
3.2 Component Descriptions ....................................................................................3-1
3.2.1 2K-FFT Processor Block...............................................................................3-1
3.2.2 2K-OFDM Demodulator Block.......................................................................3-2
3.2.2.1 I/Q-Demodulator.................................................................................3-3
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
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Table of Contents
3.2.2.2 Derotator.............................................................................................3-3
3.2.2.3 Time Synchronisation.........................................................................3-3
3.2.2.4 Channel Estimation ............................................................................3-4
3.2.2.5 Channel Estimation RAM ...................................................................3-4
3.2.2.6 Channel Correction.............................................................................3-4
3.2.2.7 Channel State Estimation...................................................................3-4
3.2.2.8 Inner Deinterleaver.............................................................................3-5
3.2.2.9 Symbol Demapper and Bit Deinterleaver ...........................................3-5
3.2.2.10Data Formatter ...................................................................................3-5
3.2.3 FEC Block .....................................................................................................3-6
3.2.3.1 Node Synchroniser.............................................................................3-6
3.2.3.2 Viterbi Error Correction.....................................................................3-12
3.2.3.3 Frame Synchronisation.....................................................................3-18
3.2.3.4 Deinterleaver ....................................................................................3-23
3.2.3.5 Reed-Solomon Decoder...................................................................3-24
3.2.3.6 Descrambler .....................................................................................3-28
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Section 4
DVB-T DEMODULATOR INTERFACES
4.1 General Purpose Outputs...................................................................................4-1
4.2 I2C Interface.......................................................................................................4-1
4.2.1 I2C Functionality............................................................................................4-2
4.2.1.1 Start Condition....................................................................................4-2
4.2.1.2 Stop Condition....................................................................................4-3
4.2.1.3 Transmitting “1” and “0”......................................................................4-3
Preliminary Information
4.2.1.4 Data Transfer Sequence ....................................................................4-3
4.2.1.5 Accessing Registers via I2C...............................................................4-4
4.2.1.6 I2C Interface of the MC92314 ............................................................4-5
4.2.2 I2C Register Maps of the MC92314..............................................................4-7
4.2.2.1 Register Map for the OFDM Part........................................................4-8
4.2.2.2 Register Map for the FEC Part .........................................................4-17
4.3 Tuner Interface .................................................................................................4-25
4.3.1 General Tuner Characteristics ....................................................................4-25
4.3.2 Clock Signals...............................................................................................4-26
4.3.3 Input from the Tuner Analog-to-Digital Converter .......................................4-27
MOTOROLA ANTOC.doc - Rev. 1.3 (11/30/98)
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4.3.4 Tuner Control signals from the MC92314 ...................................................4-27
4.3.4.1 VCXO Control Loop..........................................................................4-28
4.3.4.2 AGC Control Loop ............................................................................4-28
4.4 MPEG-2 Output Interface of the MC92314.......................................................4-28
4.5 References .......................................................................................................4-29
Table of Contents
Section 5
USAGE AND PERFORMANCE OF MOTOROLA’S SINGLE-CHIP DVB-T DEVICE
5.1 Remarks on the Circuit Diagram.........................................................................5-1
5.2 Initialising the Chipset.........................................................................................5-1
5.2.1 Setup of the OFDM Block..............................................................................5-2
5.2.1.1 Registers of the OFDM Block.............................................................5-2
5.3 Monitoring the DVB-T Single Chip......................................................................5-2
5.3.1 Status Information of the OFDM Block..........................................................5-2
5.3.1.1 Hardware pins ....................................................................................5-2
5.3.1.2 Lock Status Registers.........................................................................5-2
5.3.1.3 Usage of the AGC Feedback Register ...............................................5-3
5.3.2 Status Information of the FEC Block.............................................................5-3
5.3.2.1 Hardware Pins....................................................................................5-3
5.3.2.2 Software Registers .............................................................................5-3
5.3.2.3 FEC Block QVAL Values corresponding to BER values ....................5-3
5.4 Performance Considerations..............................................................................5-4
5.4.1 Possible Changes in the OFDM Block..........................................................5-4
5.4.1.1 Speeding up the Acquisition Time......................................................5-4
5.4.1.2 Co-Channel Protection vs. Noise .......................................................5-6
5.4.2 Possible Changes in the FEC Block..............................................................5-6
5.5 MC92314 Performance.......................................................................................5-7
5.5.1 Performance in a typical Consumer Application............................................5-7
5.6 References .......................................................................................................5-10
Preliminary Information
5.4.2.1 Fixing the Coderate for the Viterbi Decoder .......................................5-6
5.4.2.2 Adjusting the MPEG Frame Synchroniser..........................................5-6
5.5.1.1 Typical Lock Performance..................................................................5-7
5.5.1.2 Noise and Interference Performance..................................................5-9
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
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Table of Contents
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Section 6
ELECTRICAL CHARACTERISTICS
6.1 MC92314 Electrical Considerations....................................................................6-1
6.2 MC92314 DC Electrical Specifications...............................................................6-3
6.3 MC92314 Timing Characteristics........................................................................6-4
Section 7
MECHANICAL CHARACTERISTICS
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7.1 Outlines of the 160PQFP Package.....................................................................7-1
7.2 Outlines of the 169BGA Package.......................................................................7-3
Preliminary Information
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System Overview
SECTION 1
SYSTEM OVERVIEW
In this Application Note Motorola’s single chip demodulator and FEC for DVB-T receivers along
with the usual application is described.
This section covers the overall descriptions as well as an introduction into the DVB-T standard,
supporting the understanding of the special features of the OFDM system.
1.1 General Description
Before describing the important specialities of the DVB-T system itself the key features of
Motorola’s single chip are outlined.
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• 0.35mm CMOS process at 3.3 V.
• 160 pin QFP package
• 169 BGA package
There are two main sections in the chip, providing the functions necessary to obtain a complete
MPEG-2 transport stream out of one real IF-sampled DVB-T signal. The steps necessary are
OFDM demodulation and FEC decoding, corresponding to the three separate devices
described in Reference [1-4]:
Important capabilities of the FFT/OFDM block:
• Usable for 8 MHz, 7 MHz and 6 MHz channel bandwidth by adjusting the clock rate.
• C/N performance according to Reference [1-1] Annex A with a degradation margin of 3 dB.
• Supported DVB-T modulation schemes: QPSK, 16-QAM and 64-QAM.
• Automatic lock onto all specified guard interval lengths (
• Data input: 8 Bit TTL compatible 2’s complement or offset binary.
• Channel estimation and correction using the pilot carriers.
2
•I
C compatible interface (M-Bus).
Preliminary Information
1
/32,1/16,1/8,1/4).
• Transmission Parameter Signalling (TPS) data is decoded and made available to the
system controller via M-Bus.
• Processing of one block of 2048 complex samples (i.e. one 2K-OFDM symbol) in 224 ms.
• FFT input wordlength 8 bit, output accuracy 12 bit.
• Overflow on certain OFDM subcarriers due to co-channel interferes is prevented internally.
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
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System Overview
Key items of the FEC part include:
• Maximum 37 Mbit/s output rate.
• 3 Bit soft-decision input matched to the output of the OFDM block.
• Code rate
• Automatic or manual rate selection.
• Viterbi decoder survivor depth 96
• Signal quality output data.
• DVB compliant 12 x 17 Forney Convolutional Deinterleaver
• Reed-Solomon (204, 188, 8) decoder as specified by DVB
• DVB Descrambler for Energy Dispersal & inverted Sync Byte removal
1
/2 and depunctured rates of2/3,3/4,5/6, and7/8.
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• Bit Error Rate (BER) and uncorrectable Frame Error (BAD) monitoring
• setting of “transport_error_indicator” bit in the MPEG2 output stream (MSB of first byte
immediately following the Sync Byte)
1.2 Considerations on Terrestrial Transmission
Oneof the mostimportant aspectsin designinga transmission systemis tochose themodulation
schemethat fits bestto thecharacteristics ofthe transmission channelemployed. Comparingthe
terrestrial channel in the UHF band with the channels of the satellite or cable system yields
several important differences that exclude the modulation schemes used there from an efficient
usage in the terrestrial channel.
1.2.1 Echoes on the Transmission Path
InFigure 1-1 atypical environmentfor terrestrial receptionis given. Theantenna ofthe stationary
receiver receives the signal belonging to the direct path from the transmitter as well as delayed
echoes e.g.from buildings (this iscalled a Ricean channel).In contrast to thisa portable receiver
may receive only echoes without a signal direct from the transmitter (Rayleigh channel
characteristics).
Preliminary Information
MOTOROLA Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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System Overview
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Figure 1-1. Possible echo constellation
In the well knownanalog TV transmission systems such echoes appear as ghost pictures onthe
screen, but as long as they don’t get too strong the original information remains visible, at the
penalty of reduced picture quality.
1.2.2 Noise
Anotherimpairment on everytransmission channel isthe addition ofnoise. Due tomany reasons
(e.g. thermal noise, impulse noise from ignition sources) the signal quality degrades with
increasing distance from the transmitter. On the analog TV picture the different noise sources
decrease the quality of the picture, but as long as the synchronisation circuitry remains in lock
even heavily distorted pictures deliver visible information to the viewers.
Preliminary Information
1.3 Advantages of the OFDM Transmission Scheme
In contrast to this the behaviour of analog systems outlined in the paragraphs above the
behaviour of digital transmission systems is different. The picture contents are mapped into
digital signals, transmission impairments lead to transmission errors, resulting inbit errors of the
received datastream. Due to the high compression ration of the source encoded MPEG-2
transport stream used in the DVB systems even single bit errors may have a severe impact on
the picture quality. Without careful system layout, taking into account the characteristics of the
transmission channel, the performance of a digital transmission system may be very poor.
The problemsmentioned above canbe circumvented successfully leadingto the presentsystem
for digital terrestrial transmission. One of the main points is the
Multiplex (OFDM)scheme. The following list givesa short overview aboutthe key features of the
DVB-T standard:
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Orthogonal Frequency Division
1-3
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System Overview
• Divide the whole available bandwidth into a large number of subchannels with different
frequencies (Frequency Division Multiplex).
• each subchannel is independent form all others (Orthogonality).
• To combat the echoes in the terrestrial channel a guard interval is used to absorb them.
• Acertain amount ofredundancy isadded tothe bits atthe transmitterside, allowingpowerful
error correction techniques in the receiver.
In principle the whole available bandwidth is divided into a large number N (e.g. 2048) of
separate narrowband subchannels (the OFDM subcarriers). Data transmission on each
subcarrier frequency is independent from and in parallel with the other subcarriers, leading to a
verylow datarate on eachsubcarrier compared tothe overall transmissioncapacity. The splitting
into the subchannels including the modulation onto the subcarriers can be done very efficiently
by performing an
receiver must do a FFT to obtain the original information. Following the usual terms of digital
signal processing the region
is called
before the FFT (in the receiver) is associated with the ‘time domain’.
All these steps together allow the realisation of a robust transmission scheme specially adapted
to the terrestrial channel. Advances in silicon technology enable the implementation of the
advanced signal processing algorithms necessary at costs suitable to the consumer electronics
industry.
Additional information on the OFDM system can be obtained from Reference [1-2] and
Reference [1-3].
‘frequency domain’ and in contrast to it the signal after the IFFT (in the transmitter) until
Inverse Fast Fourier Transform (FFT) to the data to be transmitted. In turn the
before the IFFT in the transmitter and after the FFT in the receiver
1.4 Overview of the DVB-T System
After thorough investigation of the requirements the standard for digital terrestrial television was
finalised in 1996 (see Reference [1-1]). In line with the standards for the satellite system (DVBS) and the cable system (DVB-C) it specifies all the transmission parameters for the
broadcasting of services via terrestrial (e.g. UHF) channels.
Preliminary Information
1.4.1 Modulation Scheme
The standard covers the Orthogonal Frequency Division Multiplex (OFDM) scheme, using
OFDM symbollengths of either 2048(2K) or 8192 (8K) complex-valuedsamples. The integrated
circuit covered in this document can deal only with the 2K-system, so the 8K system is not
covered here.
Figure1-2 givesa block diagramof thecomplete DVB-Ttransmission system,theblocks marked
with thick lines are unique to the terrestrial system, whereas the other blocks are identical to the
satellite standard DVB-S. In this diagram also the basic parameters of the transmission
parameters are given, for a more detailed description see Reference [1-1]
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Channel
Terrestrial
System Overview
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Upconversion
OFDM-Mod.
Frame-Adapt.
and
Mapper
Inner
Preliminary Information
FEC-Encod.
UHF Range
Amplification
Guard-Int.
Modulator
Interleaving
and Interl.
470-862 MHz
2 K IFFT
Pilot insertion
QPSK,
64-QAM,
16-QAM or
72 Bits
with Block size
Bit-Interleaving
Interleaving depth I=12;
RS (204,188) of GF (256)
Different
guard interval
lengths possible
possible
Modulation
Non-uniform
Gray mapping
Symbol
Interleaving
(Frequency)-
,
2
/
1
(G1=171, G2=133),
Convolutional Encoding
Cell memory M=17 byte
8
/
7
,
6
/
5
,
4
/
3
,
3
/
2
Possible Coderates
Mothercoderate
sion I,Q-
Downconver-
Demodulation
OFDM
Synchron.
Demodulation
DemappingInner De-
interleaving
FEC-Decod.
Deinterleaving
15
+x
14
Sync-Inversion
MPEG-2 TS
Scrambling
P(x)=1+x
Descrambling
Sync-Inversion
Figure 1-2. DVB-T transmission system
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
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1.4.2 OFDM Block
The OFMD block performs the functions given in the blocks ‘Synchronisation’, ‘Demapping’ and
‘Inner Deinterleaving’ in Figure 1-2. This includes all the necessary synchronisation tasks,
OFDM-related deinterleaving, demapping of the constellation diagram, generation of softdecision information and output formatting. This block is designed to work directly with the FFT
block.
Important capabilities are:
• Usable for 8 MHz, 7 MHz and 6 MHz channel bandwidth by adjusting the clock rate.
• C/N performance according to Reference [1-1] Annex A with a degradation margin of 3 dB.
• Supported DVB-T modulation schemes: QPSK, 16-QAM and 64-QAM.
1
• Automatic lock on all specified guard interval lengths (
• Data input: 8 Bit TTL compatible 2’s complement or offset binary.
• Channel estimation and correction using the pilot carriers.
2
•I
C compatible interface (M-Bus) to the system controller.
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• Transmission Parameter Signalling (TPS) data is decoded and made available to the
system controller via M-Bus.
1.4.3 FFT Block
The FFT block performs the OFDM demodulation in the true sense of the word. It gets the time
domain information from the OFDM block, performs a Fast Fourier Transform on it and delivers
the frequency domain information, i.e. the constellation diagram (suffering from the channel
impairments) back again to the OFDM block.
Main features of the FFT block are:
• Processing of one block of 2048 complex samples (i.e. one 2K-OFDM symbol) in 224 µs.
• FFT input wordlength 8 bit, output accuracy selectable between 10 and 12 bit.
• Overflow on certain OFDM subcarriers due to co-channel interferes is handled internally.
Preliminary Information
1.4.4 Forward Error Correction Block
The FEC part of the DVB-T transmission is located in the blocks ‘FEC-Decoding’,
‘Deinterleaving’, ‘Sync-Inversion’ and Descrambling. All these tasks are handled by the FEC
block. The FEC scheme itself consist of the inner Viterbi decoder and the outer RS decoder.
1.4.4.1 Viterbi Decoder
The Viterbi decoder block is DVB compliant with all the coderates available according to the
specification. Its main features are:
• Maximum 37 Mbit/s output rate.
• Constraint length 7, generator polynomial (171
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• 3 Bit soft-decision input in suited to the output of the OFDM block.
• Code rate
• Automatic or manual rate selection.
• Programmable internal synchronizer.
• Provision for external synchronization.
• Survivor depth 96
• No internal APLL needed, clock is provided by the OFDM block.
• Signal quality output data.
1.4.4.2 Convolutional Deinterleaver
To achieve the optimal performance of any concatenated coding scheme there must be an
interleaver in the transmitter between the inner and outer encoder. This interleaver distributes
the bytes in a pseudo random order before feeding them into the inner encoder. In turn the
deinterleaver in the receiver rearranges the original order, spreading error bursts provoked by
overloading the inner decoder due to bad channel conditions.
In case of the DVB system the interleaving scheme uses a Convolutional 12x17 Forney
Interleaver: Every 204 bytes of data are interleaved (reordered) at the transmitter and
deinterleaved in the receiver using a Convolutional Deinterleaver with I=12 branches and M=17
byte storage cells as defined by the DVB Specifications.
1
/2 and depunctured rates of2/3,3/4,5/6, and7/8.
System Overview
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1.4.4.3 Reed-Solomon Decoder
The FEC block contains a complete Reed-Solomon decoder as specified by DVB for digital
receiver applications (204, 188) of GF(256), that means input blocks with 188 byte in length,
added redundancy of 16 checkbytes leading to 204 bytes output block length. The block will
acceptdata from theViterbi decoderand deliveran MPEG-2 transportstream tothe Set-TopBox
core demultiplexer.
1.4.4.4 Energy Dispersal Removal (Descrambling)
The MPEG-2 data (excluding Sync Bytes) are randomised for Energy Dispersal in the
transmitter. This block reverses the process and re-inverts the inverted Sync Byte prior to
delivering the data to the MPEG-2 Transport Demultiplexer. It is the last step in the frontend
processing chain.
The main features of the deinterleaver, RS decoder and descrambling block are given below:
• 37 MBit/s typical input and output data rates
• optimized Frame Synchronizer performance for DVB parameters
• DVB compliant 12x17 Forney Deinterleaver
• Reed-Solomon (204,188,8) decoder as specified by DVB
• DVB Descrambler for Energy Dispersal & inverted Sync Byte removal
Preliminary Information
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
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System Overview
• setting of “transport_error_indicator” bit in the MPEG2 output stream (MSB of first byte
immediately following the Sync Byte)
• Bit Error Rate (BER) and uncorrectable Frame Error (BAD) monitoring
• 180
o
input data stream phase error correction
1.5 References
[1-1] ETSI (European Telecommunication Standards Institute): Digital broadcasting systems
for television, sound and data services; Framing structure, channel coding and
modulation for digital terrestrial television. Draft prETS 300 744, September 1996.
[1-2] M.Alard, R. Lassalle:Principles ofmodulation and channelcoding for digitalbroadcasting
for mobile receivers. EBU Collected Papers on concepts for sound broadcasting into the
21st century, August 19988, pp. 47-69.
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[1-3] J. Gledhill, S. Anikhindi, P. Avon: The transmission of digital television in the UHF band
using Orthogonal Frequency Division Multiplex. Proceedings of the 6th International IEE
Conference on Digital Processing of Signals in Communications, IEEE Conf. Publ.
No. 340, pp. 175-180, September 1991.
[1-4] C. Patzelt, M. Drozd, S. Anikhindi: MC92307 MC92308 MC92309 DVB-T, Chipset
Application Note Version 1.1; Motorola; July 1998.
Preliminary Information
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Pinout & Signal Description of the MC92314
SECTION 2
PINOUT & SIGNAL DESCRIPTION OF THE MC92314
Motorola’s DVB-T demodulator is available in a 160QFP package as well as in a 169BGA. The
pinout of this packages as well as the input and output lines are given in Figure 2-1, Figure 2-2
and Table 2-1. The mechanical dimensions of the package are given in Section 7.
The supply voltage of the IC is 3.3 V, its power consumption is app. 1.7 W in a typical DVB-T
application as it is described Section 5.
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Preliminary Information
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
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Pinout & Signal Description of the MC92314
2.1 Pinout for the 160PQFP Package
ADCDATA2
VSS
reserved (VSS)
VDD
reserved (VSS)
ADCDATA1
VSS
reserved (VSS)
VDD
reserved (VSS)
ADCDATA0
VSS
VDD
ADCDATA-1
VSS
ADCDATA-2
VDD
INSYNC
VLOCK
TPSLOCKB
reserved (open)
AFCLOCK
CLKLOCK
VSS
reserved (open)
RESB
VDD
reserved (open)
VSS
reserved (open)
TRERROR
VDD
reserved (open)
VSS
reserved (open)
TRSTART
reserved (open)
VDD
reserved (open)
TRVALID
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ADCDATA3
reserved (VSS)
VSS
reserved (VSS)
VDD
ADCDATA4
reserved (VSS)
VSS
reserved (VSS)
VDD
ADCDATA5
reserved (VSS)
VSS
reserved (VSS)
VDD
ADCDATA6
reserved (VSS)
VSS
reserved (VSS)
VDD
ADCDATA7
reserved (VSS)
VSS
reserved (VSS)
VDD
reserved (VSS)
reserved (VSS)
VSS
reserved (VSS)
VDD
reserved (VSS)
VSS
CLKEN18
reserved (VSS)
VDD
AGCCTLP
reserved (VSS)
VSS
reserved (VSS)
AGCCTLN
140
20
Preliminary Information
160PQFP
60
100
TRCLK
reserved (open)
VSS
reserved (open)
VDD
TRDOUT7
reserved (open)
VSS
reserved (open)
VDD
TRDOUT6
reserved (open)
VSS
reserved (open)
VDD
TRDOUT5
GP3
VSS
GP2
VDD
TRDOUT4
GP1
VSS
GP0
VDD
TRDOUT3
reserved (open)
VSS
reserved (open)
VDD
TRDOUT2
reserved (open)
VSS
reserved (open)
VDD
TRDOUT1
reserved (open)
VSS
reserved (open)
TRDOUT0
Fr
VDD
CLKCTLP
reserved (VSS)
VSS
CLKCTLN
reserved (VSS)
reserved (VSS)
VDD
reserved (VSS)
VSS
SCL
reserved (VSS)
VDD
reserved (VSS)
VSS
SDA
reserved (VSS)
VDD
reserved (VSS)
VSS
CLK
reserved (VSS)
VDD
reserved (VSS)
VSS
MBUSID0
reserved (VSS)
VDD
reserved (VSS)
VSS
MBUSID1
reserved (VSS)
VDD
reserved (open)
VSS
MBUSID2
reserved (open)
VDD
MBUSID3
reserved (open)
Figure 2-1. Pinout for the 160PQFP
MOTOROLA Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Pinout & Signal Description of the MC92314
2.2 Pinout for the 169BGA Package
View from top, x-ray through package.
1 2 3 4 5 6 7 8 9 10 11 12 13
ADCDATA3ADCDATA4 (VSS) ADCDATA5ADCDATA6 ADCDATA7 (VSS) (VSS) CLKEN18 AGCCTLP (VSS) AGCCTLN CLKCTLP
A
ADCDATA2 (VSS) (VSS) (VSS) (VSS) (VSS) (VSS) OPEN8 (VSS) (VSS) (VSS) (VSS) (VSS)
B
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(VSS) (VSS) (VSS) VDD (VSS) VDD OPEN9 VDD (VSS) (VSS)
C
ADCDATA1 (VSS) (VSS) GND VDD VDD VDD VDD VDD GND CLKCTLN MSCL (VSS)
D
ADCDATA0 (VSS)
E
(VSS) INSYNC VDD VDD GND GND GND GND GND VDD VDD (VSS) CLK
F
VLOCK
G
H
AFCLOCK
J
CLKLOCK
TRERROR (OPEN) (OPEN) GND VDD VDD VDD VDD VDD GND (OPEN) MBUSID2 (OPEN)
K
(OPEN) (OPEN) VDD (OPEN) VDD
L
TPSLOCK
B
(OPEN) VDD VDD GND GND GND GND GND VDD VDD MBUSID0 (VSS)
RESB GND GND GND GND GND GND VDD (VSS) MBUSID1 (VSS)
x
x
VDD GND GND GND GND GND VDD (VSS) MSDA
(OPEN) GND GND GND GND GND GND GND (VSS) (VSS) (VSS)
x
VDD
VDD
Preliminary Information
x
x
GP2
VDD (OPEN) (OPEN) MBUSID3
x
x
x
x
Fr
TRSTART (OPEN) (OPEN) (OPEN) (OPEN) (OPEN)
M
(OPEN) TRVALID TRCLK TRDOUT7 (OPEN) TRDOUT6 TRDOUT5 TRDOUT4
N
GP3 GP1
(OPEN) (OPEN) (OPEN) (OPEN) TRDOUT0
GP0
TRDOUT3 TRDOUT2 TRDOUT1 (OPEN)
Figure 2-2. Pinout for the 169BGA
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
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Freescale Semiconductor, Inc.
Pinout & Signal Description of the MC92314
2.3 Pin Description of the Single Chip DVB-T Demodulator MC92314
The description of the MC92314 pinout is given in the table below:
Table 2-1. MC92314 Pin List
SIGNAL PIN-NR. FUNCTIONALITY TYPE ACTIVE
CLK 61 Common clock input (36.57 MHz) TTL - IN high
RESB 135 Reset (asynchronous) TTL - IN low
CLKEN18 33 ADC data strobe TTL - IN high
21, 16, 11,
ADCDATA[7:0]
ADCDATA[-1:-2] 147, 145 10-Bit extension for future 8K device
CLKCTLP 41 ADC clock control (+) TTL - OUT high
CLKCTLN 46 ADC clock control (-) TTL - OUT low
AGCCTLP 36 Analogue AGC control (+) TTL - OUT high
AGCCTLN 40 Analogue AGC control (-) TTL - OUT low
MSDA 56 I
MSCL 51 I
MBUSID[3:0]]
GP[3:0]
TRERROR 130 MPEG-2 Frame Error Indicator TTL - OUT high
TRVALID 121 MPEG-2 Byte Valid Indicator TTL - OUT high
TRSTART 125 MPEG-2 Sync Byte Indicator TTL - OUT high
TRCLK 120 MPEG-2 Byte Clock TTL - OUT high
TRDOUT[7:0]
INSYNC 143 FEC Frame Synchronization Status TTL - OUT high
VLOCK 142 Viterbi Decoder Synchronization Status TTL - OUT high
TPSLOCKB 141 TPS Data Valid indicator (inverted) TTL - OUT low
AFCLCK 139 AFC status indicator TTL - OUT high
CLKLCK 138 Time Synchronization state indicator TTL - OUT high
6, 1, 160,
155, 150
80, 76, 71,
66
104, 102,
99, 97
115, 110,
105, 100,
95, 90, 85,
81
ADC input TTL - IN high
reserved
(VSS)
2
C compatible control bus, data pin TTL - OD N/A
2
C compatible control bus, clock pin TTL - IN high
2
C compatible control bus, variable ID
I
selector
General Purpose Output pins TTL - OUT high
MPEG-2 Transport Stream Byte Output TTL - OUT high
TTL - IN high
Preliminary Information
N/A
NOTE
The pins marked with (VSS) in the BGA pinout must be tied to V
SS
.
As they are reserved pins they need not to be connected directly to
, instead of a pulldown resistor of about 10 K is sufficient.
V
SS
Similar the pins ‘(OPEN)’ must be left unconnected.
MOTOROLA Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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Device Description
SECTION 3
DEVICE DESCRIPTION
In this section the chipset as a whole as well as the operation of the several components are
described.
3.1 Complete DVB-T Digital Frontend
Motorola’s terrestrialchipset builds a complete digital frontendfor the DVB-T system, it performs
according to the following functional diagram:
2
2
IC
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RF-Input
Tuner
Core
A
1/2
RESB
ADCDATA
8
D
CLKEN18
CLK
2K DVB-T
CLK
CLK
CTLP
CTLN
MC92314
AGC
CTLP
AGC
CTLN
MBUS
TRERROR
TRVALID
TRTART
TRCLK
TRDOUT
MPEG-2
8
Transport
Stream
~
VCXO
Tuner
Figure 3-1. Block Diagram of a complete DVB-T Frontend
Whereas Motorola’s chipset covers all the digital functions required by the standard, the analog
parts (RF amplification, RF filtering, downconversion, AGC, clock generation and ADconversion) are located in the DVB-T tuner.
The RF signal obtained by the antenna has to be fed into the tuner core, given that the C/N of
the signal is high enough for the demodulation the receiver frontend will lock onto it andproduce
the transmitted transport stream ready to deliver it to the MPEG-2 demultiplexer.
Preliminary Information
3.2 Component Descriptions
After giving the overall functions of the complete digital frontend in the last paragraph we go into
more detail of the individual components:
3.2.1 2K-FFT Processor Block
Integrated into the MC92314 is a pipelined Fast Fourier Transformation (FFT) processor with a
blocklength of 2048 complex samples. It is especially designed for use in digital terrestrial Set-
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
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Device Description
Freescale Semiconductor, Inc.
Top boxes according to the DVB-T standard for 2K transmission. One block of 2048 complex
samples can be processed in 224 µs
NOMUX
DIN
FFTSTART
RESB
8
Input
8DINR
Buffer
16 24
FFT (11 stages)
incl. Rounding
Output
Reorder
Buffer
12 DOUT
12 DOUTR
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CLK
FFTSTART
OFFSET
RES[1:0]
REVRSB
Control
Twiddle Factor ROM
SYMSYNC
Figure 3-2. Block Diagram of the FFT Processor
3.2.2 2K-OFDM Demodulator Block
The MC92314 contains also a Demodulator for the Orthogonal Frequency Division Multiplex
transmission scheme according to the 2K-mode of the ETSI specification for digital terrestrial
transmission (see reference [1-1]). Together with the 2K FFT block described in the previous
paragraph it includes all the functions required to demodulate the information transmitted in one
single UHF channel.In Figure 3-3 the blockdiagram of the OFDM block is given, followedby the
description of the functional blocks.
Preliminary Information
Fr
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Device Description
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CLK Loop
Filter & DAC
Clock
VCXO
From ADC
Received Data
AGC
Time Sync
(Coarse &
Fine)
I/Q Demodulator
& Derotator
AFC
AGCAGC-DAC
Channel Data RAM
I2C & Parallel
Interface
FFT Block
TPS & Frame Synchronisation
Extracted
Pilots
Channel Estimation &
Correction
Data
Formatter
Symbol
Deinterleaving & Demapping
Control
G1, G2
Data
Channel
State
Estimation
Figure 3-3. OFDM Demodulator Part of the MC92314
3.2.2.1 I/Q-Demodulator
In this first stage the complex samples are reconstructed from the (real valued) input stream by
means of a discrete Hilbert transformer. The input stream is fed into the Hilbert transformer and
delayed appropriately to calculate the real and imaginary parts of the signal.
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3.2.2.2 Derotator
Carrier frequency offsets resulting from local oscillator offsets in the tuner are removed digitally
by means of a NCO and a phase accumulator, that are controlled by the
Automatic Frequency
Control (AFC). During the acquisition phase (when locking onto a DVB-T transmission) the AFC
circuit sweeps permanently through the available range until the correct frequency offset has
been detected. During the tracking phase the control signal for the phase increment is derived
Preliminary Information
from the pilot carriers in the frequency domain.
3.2.2.3 Time Synchronisation
The Time Synchronisation (separated in the coarse synchronisation valid during the acquisition
phase and the fine synchronisation for tracking purposes) sets the FFT window position for the
real OFDM demodulation and controls the clocking of the whole chip.
In the tracking mode the time synchronisation generates the VCXO control signal using the filter
structure given in Figure 3-4 below. The contribution of the proportional branch and of the
integrator branch can be adjusted separately using the Clock Loop Filter Coefficients (see also
paragraph 4.2.2.1.5).
The gain of the proportional part is set using Bits [7:4] and the gain of the integrator part is
adjusted with Bits [3:0].
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
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Device Description
Freescale Semiconductor, Inc.
C_Proportional
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VCXO
Figure 3-4. Time Synchronisation of the OFDM Block
3.2.2.4 Channel Estimation
To compensate for the impairments of the terrestrial channel it is essential to estimate the
channeltransfer function. Thisestimationis done usingthe scattered andcontinual pilot carriers.
As the scattered pilots change in subsequent OFDM symbols a
symbols isnecessary to build a complete setof pilot information. This set containsone valid pilot
sampleat every 3rdcarrier position. To obtaina channel estimationvalue so theset ends upwith
an estimation value for each carrier position,
3.2.2.5 Channel Estimation RAM
Thechannel estimationRAM must storethe datacarriers untilthe channelestimation is available
for a given OFDM symbol.
3.2.2.6 Channel Correction
In the channel correction block the estimate of the channel transfer function is used to
compensate the influence of the terrestrial transmission. In principle each data carrier’s value is
multiplied with the inverse of the estimate to approximate the desired flat overall frequency
response to as close as possible.
Preliminary Information
Phase
Detector
Integrator
C_Integrator
LPF
time interpolation over 4 OFDM
frequency interpolation must be performed.
sd-DAC
3.2.2.7 Channel State Estimation
To improve the efficiency of the decoding of the inner convolutional code, information about the
reliabilityof each bitreceived viathe transmissionchannel, is generatedduring thedemodulation
process. So data that were transmitted in subchannels disturbed heavily due to echoes or
interference (resulting in alow SNR in these specific subchannels) are marked less reliable than
those transmitted in nearly undisturbed subchannels. In the channel state estimation this
MOTOROLA Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
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reliability information is generated for each carrier individually and passed together with the
subcarriers data to the following stage.
3.2.2.8 Inner Deinterleaver
Due to the echoes on the transmission path it is obvious that adjacent subcarriers are disturbed
in a similar way: the used bandwidth of 7.61 MHz corresponds to 1705 active carriers, so the
difference in the channel transfer function from one carrier to the adjacent carrier is limited. In
case of a simple parallel to serial conversion adjacent bits of data would suffer from similar
distortions.In this case theViterbi decoder cannotwork with itsoptimal performance. Insteadthe
best performance is given if the disturbance applied to adjacent data bits is uncorrelated. To
achieve this the data of all the relevant subcarriers are interleaved in the transmitter according
to par. 4.3.4 in reference [1-1]. This interleaving has to be reversed prior to the demodulation.
3.2.2.9 Symbol Demapper and Bit Deinterleaver
The modulated (complex valued) frequency domain samples are demapped into 2, 4 or 6
streams depending on the modulation scheme chosen. Each demodulated data bit is extended
to a 3-bit soft decision value using the reliability information from the Channel State Estimation
to support the following FEC.
Device Description
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In par. 4.3.4 in reference [1-1], bit interleaving is also specified in order to disperse bursts of bit
errorsin the receiverafter demappingthe complex datasymbols. Thisbit interleaving isreversed
in the Bit Deinterleaver module.
3.2.2.10 Data Formatter
This is the final stage in the OFDM specific part of the DVB-T frontend. It generates from the up
to 6 bitstreams according to par. 4.3.4 in reference [1-1] the correct datastreams corresponding
to the G1 and G2 data to be fed into the Viterbi decoder.
Although the FEC scheme and the format of the data delivered by the OFDM block is identical
to the satellite system there is a fundamental difference in clocking. In the DVB-S system the
data are delivered continuously to the Viterbi decoder, where as, this cannot be the case in
DVB-T. The internal clocking is uncorrelated to the transmitted data rate. Instead of going the
costly way of synthesizing an extra clock signal for the Viterbi decoder, the demodulated data
areoutput in burst modeat an averagefrequency corresponding tothe transmitted data rate.For
details see the paragraph 4.6 OFDM -> FEC Interface in reference [1-1].
Preliminary Information
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
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Device Description
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3.2.3 FEC Block
The FEC block completes Motorola’s DVB-T single chip demodulator by providing all the FEC
functions necessary for the reception of DVB-T transmissions. It is fully compliant to the ETSI
specification for digital terrestrial broadcasting (see reference [1-1]).
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SR2..0
Depuncturing
CheckByte
Generation
Deinterleav-
er Memory
andAddress
Sequencer
Frame
Synchroniser
Viterbi
Core
Error Detec-
tion and Evalu-
Code-
word
Delay
FIFO
Error Location
and Value Gener-
Descrambler for
Energy Dispersal
Removal
Frame Detection
INSYNC
FSTART
VO
BITCLKOUT
RERRU
SPO7..0
DOVALID
SVALO
G1DATA2..0
G2DATA2..0
VDCLK
DIVALID
SYMCLK
RESB
SERIALIN
RSONLY
VLCK
Node
Synchroniser
I2C Interface
VEF
VFF
FIFO
SDASCL
Figure 3-5. Block Diagram of the FEC Block
3.2.3.1 Node Synchroniser
3.2.3.1.1 Syndrome Based Node Synchronisation
Priorto producing validdata the Viterbidecoder block mustsynchronise to theinput data stream,
Preliminary Information
including removing any phase ambiguity in the received symbols and determine the punctured
code rate transmitted.
The Viterbi block employs a method known as Syndrome Based Node Synchronisation to
achieve both I & Q symbol and punctured rate Synchronisation. This method has certain
advantages over other more common Synchronisation methods such as observation of path
metric growth rates and re-encoding of the received data stream:
• Path metric growth observations are relatively sensitive to input magnitude variations and
require multiple estimation cycles to detect Synchronisation.
• Re-encodingof the datastream (usinga convolutional encoder)requires multipleestimation
cycles and can increase the latency of the decoder.
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Syndrome based node synchronisation is independent of the average input magnitude and can
also easily detect changes of the synchronisation state.
The theory is based on the observation that the product of the incoming data and a syndrome
(predetermined by simulation for each data rate) is zero if synchronised correctly. In any other
case, the probability of 0’s vs. 1’s in the product increases. In the extreme case, i.e. the node
synchronisation is completely wrong, the product is random and there is equiprobability of 0’s
and 1’s. This behaviour is exploited for syndrome based node synchronisation.
3.2.3.1.2 Synchronisation States
The possible states that the synchroniser has to deal with are a combination of the following
factors:
• The phasing of the received symbols. The synchroniser must decide which of two possible
states theI and Q inputstreams are in. Theycan either be processedas-is or can berotated
o
to account for constellation rotation in the receiver.
90
• Determination of the framing of the I and Q bit streams so as to extract the correct symbol.
There are four possible ways to frame the two bit streams and the synchroniser must
determine the correct one.
Device Description
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3.2.3.1.3 Synchroniser Parameters
The synchroniser is based on an estimator which determines whether the received symbol
sequence is in the correct synchronisation state. This estimate is based on single sided
sequential probability ratio tests (SPRTs). The tests are based on the accumulation of the loglikelihood ratio (LLR) that a certain hypothesis (in-sync or out-of-sync) for the input sequence
holds. A vote for a hypothesis is obtained if the accumulated LLR reaches a certain threshold.
The accumulator value L is computed as shown in the flowchart in Figure .
NOTE
If a vote for out-of-sync occurs, the synchronisation state (which is
Preliminary Information
2
I
output at
hypothesis.
C register SYNCH_STATE) is increased to test the next
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
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Device Description
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Read Syndrome
Bit
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IN-SYNCH
Y
L = L + INC
Y
L = 0
N
Bit == 1
L < 0
N
L>=THRESH
N
L = L - DEC
Y
Move To
Next State
L = 0
OUT-OF-SYNCH
Figure 3-6. Synchronisation Flow
3.2.3.1.4 Choice of DEC and THRES
The constants INC, DEC and THRES influence the acquisition behaviour of the synchroniser as
well asit’s robustness. Theconstants INC and DECshould be chosen suchthat the accumulator
is driven towards zero in the case that the syndrome sequence is identifying the in-sync state
(i.e. rate of zeroes is p
Ifthe syndromesequence isidentifying an out-of-syncstate (i.e.p
).
0
=0.5) theaccumulator should
0
be driven with approximately equal average increments towards the threshold. Obviously, the
synchroniser will erroneously vote for out-of-sync condition if the channel SNR falls below a
certain limit since p
Preliminary Information
will approach 0.5 for very low SNR.
0
• The decoder uses a fixed Increment of INC = 32.
• DEC is set via I
2
C register DEC[4:0] and can have a maximum value of 32, default selection
of DEC values according to the rate being decoded is enabled by setting the DDEC bit in
the CONFIG register to 0. The default values of DEC for each of the supported rates is
shown in Table 3-1.
2
I
• THRES is set via
C register THRESHOLD and can have a maximum value of 32, default
selection of THRES = 8 is enabled by setting the DTHRES bit in the CONFIG register to be
0.
9
The actual value of THRES is interpreted as <register_value> x 2
.
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Device Description
The defaults have been chosen such that the synchroniser will operate correctly (but with a
performance degradation) roughly 2 dB below the output error rate, which is required for quasi
-4
error free operation (BER of the decoded stream approximately =2 x 10
).
Table 3-1. Default Settings For DEC Parameter
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Lower SNR
Rate Dec
1/2 29 1.2 3.0 2.15 0.100
2/3 26 2.0 3.5 2.49 0.062
3/4 25 2.4 4.0 3.00 0.042
5/6 24 2.9 4.5 3.51 0.026
7/8 23 3.5 5.2 4.10 0.017
Boundary
(dB)
Quasi
Error
Free SNR
(dB)
Design
Point SNR
(dB)
Design
Point
Channel
BER
3.2.3.1.5 Synchroniser Performance
The performance of the synchroniser can be characterized by three figures:
Short Average Run Length (SARL):
•
Thisis the meantime requiredto detect thatthe currentlyinvestigated synchronisation state
is not the correct synchronisation state.
The SARL is calculated as:
SARL
2XTHRES
-----------------------------=
INC DEC–
NOTES
Preliminary Information
SARL performance is not affected by the channel SNR since the
syndrome sequence is composed of equiprobable 1’s and 0’s for an
out of synch condition and low channel SNR would also result in
equiprobable 1’s and 0’s.
Fr
Reacquisition Average Run Length (RARL):
•
This is the mean time between a erroneous detection of a change of the synchronisation
state and successful acquisition of the new synchronisation state (reacquisition).
The RARL is calculated as:
SARL
RARL
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
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Device Description
Where “syncstates” is given by:
Table 3-2. Number of Syncstates in Code Rates
For automatic rate selection the synchroniser investigates the
possible synchronisation states one after the other and RARL is
calculated as follows:
Freescale Semiconductor, Inc.
Rate Synchstates
1/2 2
2/3 6
3/4 4
5/6 6
7/8 8
NOTE
7
-- -
8
RARL Synchstates
∑
1
rate
-- -=
2
SARL×=
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Long Average Run Length (LARL): This is the mean time until the algorithm incorrectly
•
indicates a change of the synchronisation state that did not actually occur.
This grows exponentially with the threshold value THRES.
NOTE
While the SARL and RARL can be determined analytically the
evaluation of the LARL is nontrivial and is best determined via
simulation.
Figure 6-2. showsthe simulated LARL for all code rates,the channel error rate is set sothe SNR
Preliminary Information
is 1dB below the error rate required for QEF operation at the output of Viterbi decoder.
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LARL (Syndrome Bits)
2
1e+05
5
2
Freescale Semiconductor, Inc.
+
♦
•
◊
♥
#
Device Description
•
r=1/2, design point
•
+
r=1/2, quasi error free
×
r=1/2, worst case
♦
r=2/3, design point
♥
r=3/4, design point
#
r=5/6, design point
◊
r=7/8, design point
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emiconduct
eescale S
Fr
1e+04
1e+03
+
♦
5
•
2
◊
♥
#
+
♦
××
•
×
×
××
THIS GRAPH NEEDS TO BE EXTENDED!
THE SCALES TO SHOW THE THRESHOLD UP TO 5000
AND THE CURVES EXTRAPOLATED
5
•
×
2
0.50 1.00 1.50 2.00 2.50
Preliminary Information
THRES x 10
3
Figure 3-7. LARL Versus THRES At Various Design Points
For rate1/2 (worst case for the synchroniser) the results for QEF (BER = 0.0789) and 2.8 dB
below (BER = 0.125) are shown extrapolated.
From it can be seen that the LARL increases with decreasing SNR. For QEF operation a
1
threshold below5000 is sufficientto obtain less thanone synchroniser error perday for a rate
/2.
3.2.3.1.6 Lock Detection and Time-out
Lockof the decoderis indicatedif the stateof thesynchroniser has notchanged fora significantly
long time, this period is measured in number of syndrome bits. The time-out period can be set
2
via the I
set to 0. The actual period is TIMEOUT * 2
Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA
C register TIMEOUT, a default value of 8 is used if bit DLT in the CONFIG register is
11
syndrome bits.
3-11
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Device Description
• If the accumulator value L does not reach the threshold value THRES within the period
specified by TIMEOUT then it is reset and the decoder continues to indicate a locked state.
• If L exceeds THRES before the end of the TIMEOUT period then an out of lock condition is
declared and the synchroniser moves to the next state and restarts the synchronisation
process.
To avoid false lock indications, and to quickly detect out of lock situations the optimal value for
TIMEOUT is SARL * 4.
3.2.3.2 Viterbi Error Correction
3.2.3.2.1 BER vs. SNR Performance
Figure 3-8 shows the performance curves for each code rate as a function of Bit Error Rate
(BER) versus channel Signal to Noise Ratio (SNR). The graph also shows the Quasi Error Free
(QEF) operating limit at 2 * 10
nc...
an AWGN channel with a normalized gain of 1 at the output of the receiver A/D.
-4
. The graph was generated assuming QPSK transmission over
, I
or
emiconduct
eescale S
Fr
In paragraph 5.3.2.3 an example is given how to obtain a BER estimate from the QVAL values
that are available from the FEC register.
Preliminary Information
MOTOROLA Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98)
3-12
For More Information On This Product,
Go to: www.freescale.com
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