Motorola MC88LV926DW Datasheet



SEMICONDUCTOR TECHNICAL DATA

    
 

The MC88LV926 Clock Driver utilizes phase–locked loop technology
to lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for CISC microprocessor
or single processor RISC systems. The RST
provide a processor reset function designed specifically for the
MC68/EC/LC030/040/060 microprocessor family. To support the 68060
processor, the 88LV926 operates from a 3.3V as well as a 5.0V supply.

The PLL allows the high current, low skew outputs to lock onto a single
clock input and distribute it with essentially zero delay to multiple
locations on a board. The PLL also allows the MC88LV926 to multiply a
low frequency input clock and distribute it locally at a higher (2X) system
frequency.

• 2X_Q Output Meets All Requirements of the 50 and 66MHz 68060

Microprocessor PCLK Input Specifications

• Low Voltage 3.3V V

CC

• Three Outputs (Q0–Q2) With Output–Output Skew <500ps

• CLKEN Output for Half Speed Bus Applications

• The Phase Variation From Part–to–Part Between SYNC and the ‘Q’

Outputs Is Less Than 600ps (Derived From the TPD Specification,
Which Defines the Part–to–Part Skew)

• SYNC Input Frequency Range From 5MHZ to 2X_Q F

• All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels

• Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level Compatible

• Test Mode Pin (PLL_EN) Provided for Low Frequency Testing

_IN/RST_OUT(LOCK) pins

/4

Max



LOW SKEW CMOS PLL

68060 CLOCK DRIVER

20

1

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

Three ‘Q’ outputs (Q0–Q2) are provided with less than 500ps skew between their rising edges. A 2X_Q output runs at twice
the ‘Q’ output frequency . The 2X_Q output is ideal for 68060 systems which require a 2X processor clock input, and it meets the
tight duty cycle spec of the 50 and 66MHz 68060. The QCLKEN output is designed to drive the CLKEN
the bus logic runs at half of the microprocessor clock rate. The QCLKEN output is skewed relative to the 2X_Q output to ensure
that CLKEN
multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is provided)
the input/output frequency relationships are fixed. The Q3
tree design.

In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88LV926 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment.

The RST
pin will be pulled actively low until phase–lock is achieved. When phase–lock occurs, the RST_OUT(LOCK) is released and a
pull–up resistor will pull the signal high. To give a processor reset signal, the RST
RST

_OUT(LOCK) pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high.

Description of the RST

The RST
acting as a lock indicator. If the RST
steady state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after phase–lock is achieved the
RST

_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull–up resistor (see the
AC/DC specs for the characteristics of the RST
RST

_OUT(LOCK) pin will remain low.

1/96

 Motorola, Inc. 1996

setup and hold times of the 68060 are satisfied. A Q/2 frequency is fed back internally, providing a fixed 2X

output provides an inverted clock output to allow flexibility in the clock

_OUT(LOCK) pin doubles as a phase–lock indicator. When the RST_IN pin is held high, the open drain RST_OUT

_IN pin is toggled low, and the

_IN/RST_OUT(LOCK) Functionality

_IN and RST_OUT(LOCK) pins provide a 68030/040/060 processor reset function, with the RST_OUT pin also

_IN pin is held high during system power–up, the RST_OUT pin will be in the low state until

_OUT(LOCK) pin). If the RST_IN pin is held low during power–up, the

1

REV 3

input of the 68060 when

MC88LV926

Pinout: 20–Lead Wide SOIC Package (Top View)

1

2

CC

3

Q0

4

5

6

7

8

9

10

RST_IN

Description of the RST_IN/RST_OUT(LOCK) Functionality (continued)

After the system start–up is complete and the 88LV926 is

phase–locked to the SYNC input signal (RST

_OUT high), the
processor reset functionality can be utilized. When the
RST

_IN pin is toggled low (min. pulse width=10nS),

RST

_OUT(LOCK) will go to the low state and remain there
for 1024 cycles of the ‘Q’ output frequency (512 SYNC
cycles). During the time in which the RST

_OUT(LOCK) is
actively pulled low, all the 88LV926 clock outputs will
continue operating correctly and in a locked condition to the
SYNC input (clock signals to the 68030/040/060 family of
processors must continue while the processor is in reset). A
propagation delay after the 1024th cycle RST

_OUT(LOCK)
goes back to the high impedance state to be pulled high by
the resistor.

phase–lock to the reference source, some constraints must
be placed on the power supply ramp rate to make sure the
RST

_OUT(LOCK) signal holds the processor in reset during
system start–up (power–up). With the recommended loop
filter values (see Figure 6.) the lock time is approximately
10ms. The phase–lock loop will begin attempting to lock to a
reference source (if it is present) when VCC reaches 2V. If
the VCC ramp rate is significantly slower than 10ms, then the
PLL could lock to the reference source, causing
RST

_OUT(LOCK) to go high before the 88LV926 and
’030/040 processor is fully powered up, violating the
processor reset specification. Therefore, if it is necessary for
the RST
ramp rate must be less than 10mS for proper 68030/040/060
reset operation.

Power Supply Ramp Rate Restriction for Correct 030/040
Processor Reset Operation During System Start–up

Because the RST_OUT(LOCK) pin is an indicator of

This ramp rate restriction can be ignored if the RST
can be held low during system start–up (which holds
RST

_OUT low). The RST_OUT(LOCK) pin will then be
pulled back high 1024 cycles after the RST

CAPACITANCE AND POWER SPECIFICATIONS

20

GNDQ3

19

2X_QV

18

QCLKENMR

17

V

CC

16

Q2VCC(AN)

15

GNDRC1

14

RST

_OUT(LOCK)GND(AN)

13

PLL_ENSYNC

12

Q1GND

11

V

CC

_IN pin to be held high during power–up, the V

_IN pin goes high.

CC

_IN pin

Symbol Parameter Value Typ Unit Test Conditions

C

IN

C

PD

PD

1

PD

2

* Value at VCC = 3.3V TBD.

MOTOROLA TIMING SOLUTIONS

Input Capacitance 4.5* pF VCC = 5.0V
Power Dissipation Capacitance 40* pF VCC = 5.0V
Power Dissipation at 33MHz With 50Ω

Thevenin Termination
Power Dissipation at 33MHz With 50Ω

Parallel Termination to GND

15mW/Output*

90mW/Device

37.5mW/Output*
225mW/Device

2

mW VCC = 5.0V

T = 25°C

mW VCC = 5.0V

T = 25°C

BR1333 — REV 5

MC88LV926

MAXIMUM RATINGS*

Symbol Parameter Limits Unit

VCC, AV
V
V
I
I
I
T

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the

Recommended Operating Conditions.

CC
in
out

in
out
CC

stg

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Limits Unit

V

CC

V

in

V

out

T

A

ESD Static Discharge Voltage > 1500 V

DC Supply Voltage Referenced to GND –0.5 to 7.0 V
DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V
DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V
DC Input Current, Per Pin ±20 mA
DC Output Sink/Source Current, Per Pin ±50 mA
DC VCC or GND Current Per Output Pin ±50 mA
Storage Temperature –65 to +150 °C

Supply Voltage 3.3 ±0.3 V
DC Input Voltage 0 to V
DC Output Voltage 0 to V
Ambient Operating Temperature 0 to 70 °C

CC
CC

V
V

DC CHARACTERISTICS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V)

Symbol Parameter V

V

IH

V

IL

V

OH

V

OL

I

IN

I

CCT

I

OLD

I

OHD

I

CC

1. IOL is +12mA for the RST_OUT output.

2. The PLL_EN input pin is not guaranteed to meet this specification.

3. Maximum test duration 2.0ms, one output loaded at a time.

4. The MC88LV926 can also be operated from a 5.0V supply. VOH output levels will vary 1:1 with VCC, input levels and current specs will be
unchanged.

Minimum High Level Input Voltage 3.0

Minimum Low Level Input Voltage 3.0

Minimum High Level Output Voltage 3.0

Minimum Low Level Output Voltage 3.0

Maximum Input Leakage Current 3.3 ±1.0 µA VI = VCC, GND
Maximum ICC/Input 3.3 2.0
Minimum Dynamic3 Output Current 3.3 88 mA V

Maximum Quiescent Supply Current 3.3 750 µA VI = VCC, GND

CC

3.3

3.3

3.3

3.3

3.3 –88 mA V

4

Guaranteed Limits Unit Condition

2.0

2.0

0.8

0.8

2.2

2.5

0.55

0.55

2

V V

V V

V VIN = VIH or V

V VIN = VIH or V

mA VI = VCC – 2.1V

= 0.1V or

OUT

VCC – 0.1V

= 0.1V or

OUT

VCC – 0.1V

I

OH –36mA

I

OH +36mA

OLD
OHD

–36mA

+36mA

= 1.0V Max

= 3.85 Min

IL

IL

1

TIMING SOLUTIONS
BR1333 — REV 5

3 MOTOROLA