Motorola MC88LV915TFN Datasheet

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SEMICONDUCTOR TECHNICAL DATA

1

REV 2

 Motorola, Inc. 1997

1/97

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The MC88LV915T Clock Driver utilizes phase–locked loop technology
to lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for high performance
PC’s and workstations.

The PLL allows the high current, low skew outputs to lock onto a single
clock input and distribute it with essentially zero delay to multiple
components on a board. The PLL also allows the MC88LV915T to
multiply a low frequency input clock and distribute it locally at a higher
(2X) system frequency. Multiple 88LV915’s can lock onto a single
reference clock, which is ideal for applications when a central system
clock must be distributed synchronously to multiple boards (see Figure 4
on Page 9).

Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5

output is inverted (180°
phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”
frequency.

The VCO is designed to run optimally between 20 MHz and the 2X_Q F

max

specification. The wiring diagrams in Figure 2 detail
the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the
“Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.

The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1
and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on
page 2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding
FREQ_SEL low (÷2) will allow the VCO to run in its optimal range (>20MHz).

In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88LV915T in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing
(see detailed description on page 11).

Pulling the OE

/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After the

OE

/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC

input. Assuming PLL_EN is low, the outputs will remain reset until the 88LV915 sees a SYNC input pulse.

A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will go
low if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88L V915 sees a
SYNC signal and full 5V VCC.

Features

•

Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input

• The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the t

PD

specification, which defines the part–to–part skew)

• Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available

• Input frequency range from 5MHz – 2X_Q FMAX spec.

• Additional outputs available at 2X and +2 the system “Q” frequency . Also a Q (180° phase shift) output available

• All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs

are TTL–level compatible. ±88mA IOL/IOH specifications guarantee 50Ω transmission line switching on the incident edge

• Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.

All outputs can go into high impedance (3–state) for board test purposes

• Lock Indicator (LOCK) accuracy indicates a phase–locked state

Yield Surface Modeling and YSM are trademarks of Motorola, Inc.



LOW SKEW CMOS

PLL CLOCK DRIVER

MC88LV915T

MOTOROLA TIMING SOLUTIONS

BR1333 — Rev 6

2

PLL_ENGNDQ1V

CC

Q0GND

FREQ_SEL

LOCK

GND

Q2

V

CC

Q3

GND

Q/2

RC1

GND(AN)

VCC(AN)

SYNC[1]

SYNC[0]

REF_SEL

FEEDBACK

2X_QOE

/RST V

CC

V

CC

Q4Q5 GND

25

24

23
22

21
20

1911

10

9

8

7

6

5

18171612 13 14 15

2627284321

Pinout: 28–Lead PLCC (Top View)

Reference clock input
Reference clock input
Chooses reference between sync[0] & Sync[1]
Doubles VCO Internal Frequency (low)
Feedback input to phase detector
Input for external RC network
Clock output (locked to sync)
Inverse of clock output
2 x clock output (Q) frequency (synchronous)
Clock output(Q) frequency

÷

2 (synchronous)
Indicates phase lock has been achieved (high when locked)
Output Enable/Asynchronous reset (active low)
Disables phase–lock for low freq. testing
Power and ground pins (note pins 8, 10 are
“analog” supply pins for internal PLL only)

Input
Input
Input
Input
Input

Input
Output
Output
Output
Output
Output

Input

Input

1
1
1
1
1
1
5
1
1
1
1
1
1

11

PIN SUMMARY

SYNC[0]
SYNC[1]
REF_SEL
FREQ_SEL
FEEDBACK
RC1
Q(0–4)
Q5
2x_Q
Q/2
LOCK
OE

/RST
PLL_EN
VCC,GND

Pin Name Num I/O Function

FN SUFFIX

PLASTIC PLCC

CASE 776–02

MC88LV915T

TIMING SOLUTIONS
BR1333 — Rev 6

3 MOTOROLA

MC88LV915T BLOCK DIAGRAM

M
U
X

0

1

M
U
X

0

1

MUX

1

0

PLL_EN

R

R

R

R

R

R

R

OE/RST

FEEDBACK

Q/2

Q

CP

D

Q5

Q4

Q

CP

D

Q

CP

D

EXTERNAL REC NETWORK

(RC1 Pin)

REF_SEL

SYNC (1)

SYNC (0)

CHARGE PUMP/LOOP

FILTER

DIVIDE

BY TWO

Q3

Q

CP

D

Q2

Q1

Q0

2x_Q

Q

CP

D

Q

CP

D

Q

Q

CP

D

(

÷

1)

(

÷

2)

FREQ_SEL

OSCILLATOR

VOLTAGE

CONTROLLED

PHASE/FREQ.

DETECTOR

LOCK

MC88LV915T

MOTOROLA TIMING SOLUTIONS

BR1333 — Rev 6

4

MAXIMUM RATINGS*

Symbol Parameter Limits Unit

VCC, AV

CC

DC Supply Voltage Referenced to GND –0.5 to 7.0 V

V

in

DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V

V

out

DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V

I

in

DC Input Current, Per Pin ±20 mA

I

out

DC Output Sink/Source Current, Per Pin ±50 mA

I

CC

DC VCC or GND Current Per Output Pin ±50 mA

T

stg

Storage Temperature –65 to +150 °C

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating
Conditions.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Limits Unit

V

CC

Supply Voltage 3.3 ±0.3 V

V

in

DC Input Voltage 0 to V

CC

V

V

out

DC Output Voltage 0 to V

CC

V

T

A

Ambient Operating Temperature 0 to 70 °C

ESD Static Discharge Voltage > 1000 V

DC CHARACTERISTICS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V)

Symbol Parameter V

CC

Guaranteed Limits Unit Condition

V

IH

Minimum High Level Input Voltage 3.0

3.3

2.0

2.0

V V

OUT

= 0.1V or

VCC – 0.1V

V

IL

Minimum Low Level Input Voltage 3.0

3.3

0.8

0.8

V V

OUT

= 0.1V or

VCC – 0.1V

V

OH

Minimum High Level Output Voltage 3.0

3.3

2.4

2.7

V VIN = VIH or V

IL

IOH= –24mA

V

OL

Minimum Low Level Output Voltage 3.0

3.3

0.44

0.44

V VIN = VIH or V

IL

IOH= 24mA

I

IN

Maximum Input Leakage Current 3.6 ±1.0 µA VI = VCC, GND

I

CCT

Maximum ICC/Input 3.6 2.0 mA VI = VCC – 2.1V

I

OLD

Minimum Dynamic3 Output Current 3.6 +50 mA V

OLD

= 1.25V

I

OHD

3.6 –50 mA V

OHD

=2.35V

I

CC

Maximum Quiescent Supply Current 3.6 TBD µA VI = VCC, GND

1. IOL is +12mA for the RST_OUT output.

2. The PLL_EN input pin is not guaranteed to meet this specification.

3. Maximum test duration 2.0ms, one output loaded at a time.

SYNC INPUT TIMING REQUIREMENTS

Symbol Parameter Minimum Maximum Unit

t

RISE/FALL

SYNC Input

Rise/Fall Time, SYNC Input
From 0.8V to 2.0V

— 5.0 ns

t

CYCLE

,

SYNC Input

Input Clock Period
SYNC Input

1

f

2X_Q

ń

4

100 ns

Duty Cycle Duty Cycle, SYNC Input 50% ± 25%