Motorola MC88916DW Datasheet

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SEMICONDUCTOR TECHNICAL DATA

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The MC88916 Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for CISC microprocessor
or single processor RISC systems. The RST
provide a processor reset function designed specifically for the
MC68/EC/LC030/040 microprocessor family. The 88916 comes in two
speed grades: 70 and 80MHz. These frequencies correspond to the
2X_Q maximum output frequency . The two grades should be ordered as
the MC88916DW70 and MC88916DW80, respectively.

• Provides Performance Required to Drive 68030 Microprocessor Family

as well as the 33 and 40MHz 68040 Microprocessors

• Three Outputs (Q0–Q2) With Output–Output Skew <500ps and Six

Outputs T otal (Q0–Q2, Q3
and Frequency Locked to the SYNC Input

, 2X_Q,) With <1ns Skew Each Being Phase

• The Phase Variation From Part–to–Part Between SYNC and the ‘Q’

Outputs Is Less Than 600ps (Derived From the TPD Specification,
Which Defines the Part–to–Part Skew)

• SYNC Input Frequency Range From 5MHZ to 2X_Q F

• Additional Outputs Available at 2X and ÷2 the System ‘Q’ Frequency.

Also a Q

(180° Phase Shift) Output Available.

• All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels.

Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level
Compatible

• Test Mode Pin (PLL_EN) Provided for Low Frequency Testing

_IN/RST_OUT(LOCK) pins

/4

Max

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LOW SKEW CMOS PLL

CLOCK DRIVER WITH

PROCESSOR RESET

20

1

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay
to multiple locations on a board. The PLL also allows the MC88916 to multiply a low frequency input clock and distribute it locally
at a higher (2X) system frequency.

Three ‘Q’ outputs (Q0–Q2) are provided with less than 500ps skew between their rising edges. The Q3
phase shift) from the ‘Q’ outputs. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output does not meet the
stringent duty cycle requirement of the 20 and 25Mhz 68040 microprocessor PCLK input. The 88920 has been designed
specifically to provide the 68040 PCLK and BCLK inputs for the low frequency 68040 microprocessor. 68040 designers should
refer to the 88920 data sheet for more details. For the 33 and 40MHz 68040, the 2X_Q output will meet the duty cycle
requirements of the PCLK input. The Q/2 output runs at 1/2 the ‘Q’ frequency . This output is fed back internally, providing a fixed
2X multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is
provided) the input/output frequency relationships are fixed.

In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88916 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment.

The RST
pin will be pulled actively low until phase–lock is achieved. When phase–lock occurs, the RST_OUT(LOCK) is released and a
pull–up resistor will pull the signal high. To give a processor reset signal, the RST
RST

Description of the RST_IN/RST_OUT(LOCK) Functionality

The RST
a lock indicator. If the RST
state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after phase–lock is achieved the
RST
AC/DC specs for the characteristics of the RST
RST

_OUT(LOCK) pin doubles as a phase–lock indicator. When the RST_IN pin is held high, the open drain RST_OUT

_IN pin is toggled low, and the

_OUT(LOCK) pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high.

_IN and RST_OUT(LOCK) pins provide a 68030/040 processor reset function, with the RST_OUT pin also acting as

_IN pin is held high during system power–up, the RST_OUT pin will be in the low state until steady

_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull–up resistor (see the

_OUT(LOCK) pin). If the RST_IN pin is held low during power–up, the

_OUT(LOCK) pin will remain low.

output is inverted (180°

11/93

 Motorola, Inc. 1995

1

REV 2

MC88916

1

2

CC

3

Q0

4

5

6

7

8

9

10

RST_IN

Pinout: 20–Lead Wide SOIC Package (Top View)

Description of the RST_IN/RST_OUT(LOCK) Functionality (continued)

20

19

18

17

16

15

14

13

12

11

GNDQ3

2X_QV

Q/2MR

V

CC

Q2VCC(AN)

GNDRC1

RST

PLL_ENSYNC

Q1GND

V

CC

_OUT(LOCK)GND(AN)

After the system start–up is complete and the 88916 is
phase–locked to the SYNC input signal (RST

_OUT high), the
processor reset functionality can be utilized. When the
RST

_IN pin is toggled low (min. pulse width=10nS),

RST

_OUT(LOCK) will go to the low state and remain there
for 1024 cycles of the ‘Q’ output frequency (512 SYNC
cycles). During the time in which the RST

_OUT(LOCK) is
actively pulled low, all the 88916 clock outputs will continue
operating correctly and in a locked condition to the SYNC
input (clock signals to the 68030/040 family of processors
must continue while the processor is in reset). A propagation
delay after the 1024th cycle RST

_OUT(LOCK) goes back to

the high impedance state to be pulled high by the resistor.

phase–lock to the reference source, some constraints must
be placed on the power supply ramp rate to make sure the
RST

_OUT(LOCK) signal holds the processor in reset during
system start–up (power–up). With the recommended loop
filter values (see Figure 7) the lock time is approximately
10ms. The phase–lock loop will begin attempting to lock to a
reference source (if it is present) when VCC reaches 2V. If
the VCC ramp rate is significantly slower than 10ms, then the
PLL could lock to the reference source, causing
RST

_OUT(LOCK) to go high before the 88916 and 68030
processor is fully powered up, violating the processor reset
specification. Therefore, if it is necessary for the RST
to be held high during power–up, the VCC ramp rate must be
less than 10mS for proper 68030/040 reset operation.

Power Supply Ramp Rate Restriction for Correct 68030
Processor Reset Operation During System Start–up

Because the RST_OUT(LOCK) pin is an indicator of

This ramp rate restriction can be ignored if the RST
can be held low during system start–up (which holds
RST

_OUT low). The RST_OUT(LOCK) pin will then be
pulled back high 1024 cycles after the RST

CAPACITANCE AND POWER SPECIFICATIONS

Symbol Parameter Value Typ Unit Test Conditions

C
C
PD

PD

IN
PD

1

2

Input Capacitance 4.5 pF VCC = 5.0V
Power Dissipation Capacitance 40 pF VCC = 5.0V
Power Dissipation at 33MHz With 50Ω

Thevenin Termination
Power Dissipation at 33MHz With 50Ω

Parallel Termination to GND

15mW/Output
90mW/Device

37.5mW/Output
225mW/Device

mW VCC = 5.0V

T = 25°C

mW VCC = 5.0V

T = 25°C

_IN pin

_IN pin

_IN pin goes high.

MOTOROLA TIMING SOLUTIONS

2

BR1333 — REV 5

MC88916

MAXIMUM RATINGS*

Symbol Parameter Limits Unit

VCC, AV
V
V
I
I
I
T

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the

Recommended Operating Conditions.

CC
in
out

in
out
CC

stg

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Limits Unit

V

CC

V

in

V

out

T

A

ESD Static Discharge Voltage > 1500 V

DC Supply Voltage Referenced to GND –0.5 to 7.0 V
DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V
DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V
DC Input Current, Per Pin ±20 mA
DC Output Sink/Source Current, Per Pin ±50 mA
DC VCC or GND Current Per Output Pin ±50 mA
Storage Temperature –65 to +150 °C

Supply Voltage 5.0 ±10% V
DC Input Voltage 0 to V
DC Output Voltage 0 to V
Ambient Operating Temperature –40 to 85 °C

CC
CC

V
V

DC CHARACTERISTICS (TA = –40°C to +85°C; VCC = 5.0V ± 5%)

Symbol Parameter V

V

IH

V

IL

V

OH

V

OL

I

IN

I

CCT

I

OLD

I

OHD

I

CC

1. IOL is +12mA for the RST_OUT output.

2. The PLL_EN input pin is not guaranteed to meet this specification.

3. Maximum test duration 2.0ms, one output loaded at a time.

Minimum High Level Input Voltage 4.75

Minimum Low Level Input Voltage 4.75

Minimum High Level Output Voltage 4.75

Minimum Low Level Output Voltage 4.75

Maximum Input Leakage Current 5.25 ±1.0 µA VI = VCC, GND
Maximum ICC/Input 5.25 2.0
Minimum Dynamic3 Output Current 5.25 88 mA V

Maximum Quiescent Supply Current 5.25 750 µA VI = VCC, GND

CC

5.25

5.25

5.25

5.25

5.25 –88 mA V

Guaranteed Limits Unit Condition

2.0

2.0

0.8

0.8

4.01

4.51

0.44

0.44

2

V V

V V

V VIN = VIH or V

V VIN = VIH or V

mA VI = VCC – 2.1V

= 0.1V or

OUT

VCC – 0.1V

= 0.1V or

OUT

VCC – 0.1V

I

OH –36mA

I

OH +36mA

OLD
OHD

–36mA

+36mA

= 1.0V Max

= 3.85 Min

IL

IL

1

TIMING SOLUTIONS
BR1333 — REV 5

3 MOTOROLA