Motorola MC88915FN70, MC88915FN55 Datasheet

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SEMICONDUCTOR TECHNICAL DATA

1

REV 4

 Motorola, Inc. 1997

1/97

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The MC88915 Clock Driver utilizes phase–locked loop
technology to lock its low skew outputs’ frequency and phase
onto an input reference clock. It is designed to provide clock
distribution for high performance PC’s and workstations.

The PLL allows the high current, low skew outputs to lock
onto a single clock input and distribute it with essentially zero
delay to multiple components on a board. The PLL also allows
the MC88915 to multiply a low frequency input clock and
distribute it locally at a higher (2X) system frequency . Multiple
88915’s can lock onto a single reference clock, which is ideal
for applications when a central system clock must be
distributed synchronously to multiple boards (see Figure 7).

Five “Q” outputs (QO–Q4) are provided with less than 500
ps skew between their rising edges. The Q5

output is inverted
(180° phase shift) from the “Q” outputs. The 2X_Q output runs
at twice the “Q” output frequency, while the Q/2 runs at 1/2 the
“Q” frequency.

The VCO is designed to run optimally between 20 MHz and
the 2X_Q Fmax specification. The wiring diagrams in Figure 5
detail the different feedback configurations which create
specific input/output frequency relationships. Possible
frequency ratios of the “Q” outputs to the SYNC input are 2:1,
1:1, and 1:2.

The FREQ_SEL pin provides one bit programmable
divide–by in the feedback path of the PLL. It selects between
divide–by–1 and divide–by–2 of the VCO before its signal
reaches the internal clock distribution section of the chip (see
the block diagram on page 2). In most applications
FREQ_SEL should be held high (÷1). If a low frequency
reference clock input is used, holding FREQ_SEL low (÷2) will
allow the VCO to run in its optimal range (>20 MHz).

In normal phase–locked operation the PLL_EN pin is held
high. Pulling the PLL_EN pin low disables the VCO and puts
the 88915 in a static “test mode”. In this mode there is no
frequency limitation on the input clock, which is necessary for
a low frequency board test environment. The second SYNC
input can be used as a test clock input to further simplify
board–level testing (see detailed description on page 11).

A lock indicator output (LOCK) will go high when the loop is
in steady–state phase and frequency lock. The LOCK output
will go low if phase–lock is lost or when the PLL_EN pin is low.
Under certain conditions the lock output may remain low, even
though the part is phase–locked. Therefore the LOCK output
signal should not be used to drive any active circuitry; it should
be used for passive monitoring or evaluation purposes only.

Yield Surface Modeling and YSM are trademarks of Motorola, Inc.

Features

• Five Outputs (QO–Q4) with Output–Output Skew < 500

ps each being phase and frequency locked to the SYNC
input

• The phase variation from part–to–part between the SYNC

and FEEDBACK inputs is less than 550 ps (derived from
the tPD specification, which defines the part–to–part
skew)

• Input/Output phase–locked frequency ratios of 1:2, 1:1,

and 2:1 are available

• Input frequency range from 5MHz – 2X_Q FMAX spec

• Additional outputs available at 2X and +2 the system “Q”

frequency. Also a Q

(180° phase shift) output available

• All outputs have ±36 mA drive (equal high and low) at

CMOS levels, and can drive either CMOS or TTL inputs.
All inputs are TTL–level compatible

• Test Mode pin (PLL_EN) provided for low frequency

testing. Two selectable CLOCK inputs for test or
redundancy purposes



PLL_ENGNDQ1V

CC

Q0GND

FREQ_SEL

LOCK

GND

Q2

V

CC

Q3

GND

Q/2

RC1

GND(AN)

VCC(AN)

SYNC[1]

SYNC[0]

REF_SEL

FEEDBACK

2X_QRST V

CC

V

CC

Q4Q5 GND

25

24

23
22

21
20

1911

10

9

8

7

6

5

18171612 13 14 15

2627284321

28–Lead Pinout (Top View)

ORDERING INFORMATION

MC88915FN55 PLCC
MC88915FN70 PLCC

FN SUFFIX

PLASTIC PLCC

CASE 776–02

MC88915

MOTOROLA TIMING SOLUTIONS

BR1333 — Rev 6

2

MC88915 Block Diagram

M
U
X

0

1

M
U
X

0

1

MUX

1

0

PLL_EN

R

R

R

R

R

R

R

RST

FEEDBACK

Q/2

Q

CP

D

LOCK

Q5

Q4

Q

CP

D

Q

CP

D

EXTERNAL REC NETWORK

(RC1 Pin)

REF_SEL

SYNC (1)

SYNC (0)

CHARGE PUMP/LOOP

FILTER

DIVIDE

BY TWO

Q3

Q

CP

D

Q2

Q1

Q0

2x_Q

Q

CP

D

Q

CP

D

Q

Q

CP

D

(

÷

1)

(

÷

2)

FREQ_SEL

OSCILLATOR

VOLTAGE

CONTROLLED

PHASE/FREQ.

DETECTOR

Reference clock input
Reference clock input
Chooses reference between sync[0] & Sync[1]
Selects Q output frequency
Feedback input to phase detector
Input for external RC network
Clock output (locked to sync)
Inverse of clock output
2 x clock output (Q) frequency (synchronous)
Clock output(Q) frequency

÷

2 (synchronous)
Indicates phase lock has been achieved (high when locked)
Asynchronous reset (active low)
Disables phase–lock for low freq. testing
Power and ground pins (note pins 8, 10 are
“quiet” supply pins for internal logic only)

Input
Input
Input
Input
Input

Input
Output
Output
Output
Output
Output

Input

Input

1
1
1
1
1
1
5
1
1
1
1
1
1

11

PIN SUMMARY

SYNC[0]
SYNC[1]
REF_SEL
FREQ_SEL
FEEDBACK
RC1
Q(0–4)
Q5
2x_Q
Q/2
LOCK
RST
PLL_EN
VCC,GND

Pin Name Num I/O Function

MC88915

TIMING SOLUTIONS
BR1333 — Rev 6

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND; TA =0° C to + 70° C, VCC = 5.0V ± 5%)

Symbol Parameter Test Conditions V

CC
V

Guaranteed Limit Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V 4.75

5.25

2.0

2.0

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V 4.75

5.25

0.8

0.8

V

V

OH

Minimum High–Level Output
Voltage

Vin = VIH or V

IL

IOH = –36 mA

1

4.75

5.25

4.01

4.51

V

V

OL

Maximum Low–Level Output
Voltage

Vin = VIH or V

IL

IOL = 36 mA

1

4.75

5.25

0.44

0.44

V

I

in

Maximum Input Leakage Current VI = VCC or GND 5.25 ±1.0 µA

I

CCT

Maximum ICC/Input VI = VCC – 2.1 V 5.25

1.5

2

mA

I

OLD

Minimum Dynamic Output Current

3

V

OLD

= 1.0V Max 5.25 88 mA

I

OHD

V

OHD

= 3.85 V Max 5.25 –88 mA

I

CC

Maximum Quiescent Supply
Current (per Package)

VI = VCC or GND 5.25 1.0 mA

1. IOL and IOH are 12mA and –12mA respectively for the LOCK output.

2. The PLL_EN input pin is not guaranteed to meet this specification.

3. Maximum test duration is 2.0ms, one output loaded at a time.

CAPACITANCE AND POWER SPECIFICATIONS

Symbol Parameter Typical Values Unit Conditions

C

IN

Input Capacitance 4.5 pF VCC = 5.0 V

C

PD

Power Dissipation Capacitance 40 pF VCC = 5.0 V

PD

1

Power Dissipation @ 33MHz with 50Ω Thevenin Termination 15 mW/Output

120 mW/Device

mW VCC = 5.0 V

T = 25°C

PD

2

Power Dissipation @ 33MHz with 50Ω Parallel Termination to GND 37.5 mW/Output

300 mW/Device

mW VCC = 5.0 V

T = 25° C

SYNC INPUT TIMING REQUIREMENTS

Symbol Parameter Min Max Unit

t

RISE

, t

FALL

Maximum Rise and Fall times, (SYNC Inputs: From 0.8V – 2.0V) – 3.0 ns

FN55 FN70

t

CYCLE

I

nput Clock Period

(SYNC I

nputs

)

36 28.5

200

1

ns

Duty Cycle Input Duty Cycle (SYNC Inputs) 50% ±25%

1. Information in Fig. 5 and in the “General AC Specification Notes”, Note #3 describes this specification and its actual limits depending on the
application.

FREQUENCY SPECIFICATIONS (TA =0° C to + 70° C, VCC = 5.0V ±5%, CL = 50pF)

Guaranteed Minimum

Symbol Parameter MC88915FN55 MC88915FN70 Unit

f

max

1

Maximum Operating Frequency

(2X_Q Output)

55 70 MHz

Maximum Operating Frequency (Q0–Q4,Q5 Output) 27.5 35 MHz

1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded at 50 pF.

MC88915

MOTOROLA TIMING SOLUTIONS

BR1333 — Rev 6

4

AC ELECTRICAL CHARACTERISTICS (TA =0° C to +70° C, VCC = 5.0V ±5%, CL = 50pF)

Symbol Parameter Min Max Unit

t

RISE

, t

FALL

(Outputs)

Rise and Fall Times, all Outputs Into a 50 pF, 500 Ω Load
(Between 0.2VCC and 0.8VCC)

1.0 2.5 ns

t

RISE

, t

FALL

3

(2X_Q Output)

Rise and Fall Time, 2X_Q Output Into a 20 pF Load With Termina­tion specified in note 2 (Between 0.8 V and 2.0 V)

0.5 1.6 ns

t

Pulse Width

3Output Pulse Width (Q0, Q1, Q3, Q4, Q5, Q/2 @VCC/2) 0.5t

CYCLE

– 0.5 0.5t

CYCLE

+ 0.5

(Q0,Q1,Q3,Q4,

Q5,Q/2)

t

CYCLE

= 1/Freq. at which the “Q”

Outputs are running ns

t

Pulse Width

3

(Q2 only)

Output Pulse Width (Q2 Output @ VCC/2) 0.5t

CYCLE

– 0.6 0.5t

CYCLE

+ 0.6

t

Pulse Width

3

(2X_Q Output)

Output Pulse Width (2X_Q Output @ 1.5 V) (See AC Note 2) 0.5t

CYCLE

– 0.5 0.5t

CYCLE

+ 0.5 ns

t

Pulse Width

3

(2X_Q Output)

Output Pulse Width (2X_Q Output @ VCC/2) 0.5t

CYCLE

– 1.0 0.5t

CYCLE

+ 1.0 ns

tPD

3

(470kΩ From RC1 to An.VCC)

(Sync–Feedback) SYNC input to feedback delay –1.05 –0.50

(meas. @ SYNC0 or 1 and FEEDBACK input pins) (470kΩ From RC1 to An.GND) ns
(See General AC Specification note 4 and Fig. 2 for explanation) +1.25 +3.25

t

SKEWr

1,3

(Rising)

Output–to–Output Skew Between Outputs Q0 – Q4, Q/2
(Rising Edges Only)

– 500 ps

t

SKEWf

1,3

(Falling)

Output–to–Output Skew Between Outputs Q0 – Q4
(Falling Edges Only)

– 750 ps

t

SKEWall

1,3

Output–to–Output Skew Between Outputs 2X_Q, Q/2, Q0 – Q4
Rising, Q5 Falling

– 750 ps

t

LOCK

Time Required to acquire 2 Phase–Lock from time SYNC Input Sig­nal is Received.

1 10 ms

t

PHL

(Reset – Q)

Propagation Delay, RST to Any Output (High–Low) 1.5 13.5 ns

1. Under equally loaded conditions, CL ≤50pF (±2pF), and at a fixed temperature and voltage.

2. With VCC fully powered–on and an output properly connected to the FEEDBACK pin. t

LOCK

Max. is with C1 = 0.1µF, t

LOCK

Min is with

C1 = 0.01µF.

3. These specifications are not tested, they are guaranteed by statistical characterization. See General AC Specification note 1.

RESET TIMING REQUIREMENTS

1

Symbol

Parameter Minimum Unit

t

REC

, RST

to SYNC

Reset Recovery Time rising RST

edge to falling SYNC edge

9.0 ns

tW, RST

LOW

Minimum Pulse Width,

RST

input LOW

5.0 ns

1. These reset specs are valid only when PLL_EN is LOW and the part is in Test mode (not in phase–lock)