MOTOROLA MC7660DR2 Datasheet

MC7660

Charge Pump DC-to-DC
V oltage Converter

The MC7660 is a pin–compatible replacement for the Industry
standard ICL7660 charge pump voltage converter . It converts a +1.5V
to +10V input to a corresponding –1.5V to –10V output using only two
low–cost capacitors, eliminating inductors and their associated cost,
size and EMI.

The on–board oscillator operates at a nominal frequency of 10kHz.
Operation below 10kHz (for lower supply current applications) is
possible by connecting an external capacitor from OSC to ground
(with pin 1 open).

The MC7660 is available in an 8–pin SOIC package in extended
temperature range.

Features

• Converts +5V Supply to –5V Supply

• Wide Input Voltage Range: 1.5V to 10V

• Ef ficient Voltage Conversion: 99.9%

• Excellent Power Efficiency: 98%

• Low Power Supply: 80µA @ 5V

• Low Cost and Easy to Use

– Only Two External Capacitors Required

• Available in Small Outline (SO) Package

• ESD Protection: ≥ 2.5kV

• No Dx Diode Required for High Voltage Operation

Typical Applications

• RS–232 Negative Bias

• Display Bias

• Data Aquisition Negative Supply Generation

IN

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SO–8
D SUFFIX
CASE 751

PIN CONFIGURATION

(Top View)

+

V

NC

1

+

2

CAP

3

GND

–

4

CAP

ORDERING INFORMATION

Device Package Shipping

MC7660DR2 8–Pin SOIC 2500 Tape/Reel

8
7

OSC

6

LV

5

V

OUT

OSC

LV

7

6

RC

OSCILLATOR

INTERNAL

REGULATOR

MC7660

 Semiconductor Components Industries, LLC, 1999

February , 2000 – Rev. 2

VOLTAGE

FUNCTIONAL BLOCK DIAGRAM

V+ CAP+

28

VOLTAGE–

B

2

LEVEL

TRANSLATOR

3

GND

1 Publication Order Number:

LOGIC

NETWORK

4

CAP–

5

V

OUT

MC7660/D

MC7660

ABSOLUTE MAXIMUM RATINGS*

Parameter Value Unit

Supply Voltage +10.5 V
LV and OSC Inputs Voltage (Note 1.)

V+ < 5.5V
V+ > 5.5V

Current Into LV (Note 1.) V+ > 3.5V
Output Short Duration (V

SUPPLY

≤ 5.5V) Continuous

Power Dissipation (TA ≤ 70°C)

Derate above 50°C

–0.3 to (V+ + 0.3)

(V+ – 5.5) to (V+ + 0.3)

20 µA

470

5.5

Operating Temperature Range

–40 to +85
Storage Temperature Range –65 to +150 °C
Lead Temperature (Soldering, 10 Seconds) +300 °C

* Maximum Ratings are those values beyond which damage to the device may occur.

1. Connecting any input terminal to voltages greater than V+ or less than GND may cause destructive latch–up. It is recommended that no inputs
from sources operating from external supplies be applied prior to ”power up” of the MC7660.

V

mW

mW/°C

°C

ELECTRICAL CHARACTERISTICS (Specifications Measured Over Operating Temperature Range, V+ = 5V, C
Test Circuit

(Figure 1), unless otherwise noted.

OSC

Symbol Characteristic Min Typ Max Unit

+

I

+

V

H

+

V

L

R

OUT

F

OSC

P

EFF

V

OUT EFF

Z

OSC

Supply Current (RL = R) — 80 180 µA
Supply Voltage Range, High

(–40°C ≤ TA ≤ +85°C, RL = 10 kW, LV Open)

3.0 — 10

Supply Voltage Range, Low

(–40°C ≤ TA ≤ +85°C, RL = 10 kW, LV to GND)

1.5 — 3.5

Output Source Resistance

I

= 20mA, TA = 25°C

OUT

I

= 20mA, 0°C ≤ TA ≤ +70°C

OUT

I

= 20mA, –40°C ≤ TA ≤ +85°C

OUT

V+ =2V, I

= 3 mA, LV to GND, 0°C ≤ TA ≤ +70°C

OUT

—
—
—
—

70
—
—

150

100
120
130

300
Oscillator Frequency (Pin 7 Open) — 10 — kHz
Power Efficiency (RL = 5kW)

95 98 — %
Voltage Conversion Efficiency 97 99.9 — %
Oscillator Impedance

V+ = 2V
V+ = 5V

C1

10 mF

—
—

I

1
2

+

MC7660

3
4

8
7

C

6
5

OSC

S

V+

I

L

R

L

(+6 V)

V

O

*

1000

100

—
—

= 0,

V

V

W

k

W

*NOTE: For large values of C

of C1 and C2 should be increased to 100 mF.

Figure 1. MC7660 T est Circuit

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C2
10 mF

+

(>1000 pF), the values

OSC

2

MC7660

APPLICATIONS INFORMATION

Detailed Description

The MC7660 contains all the necessary circuitry to

implement a voltage inverter, with the exception of two
external capacitors, which may be inexpensive 10 µF
polarized electrolytic capacitors. Operation is best
understood by considering Figure 2, which shows an
idealized voltage inverter. Capacitor C
voltage, V

+

, for the half cycle when switches S1 and S3 are

is charged to a

1

closed. (Note: Switches S2 and S4 are open during this half
cycle.) During the second half cycle of operation, switches
S2 and S4 are closed, with S1 and S3 open, thereby shifting
capacitor C1 negatively by V+ volts. Charge is then
transferred from C

to C2, such that the voltage on C2 is

1

exactly V+, assuming ideal switches and no load on C2.

V+

GND

Figure 2. Idealized Charge Pump Inverter

S1 S2

S3 S4

C1

C2

V
–V

OUT

IN

=

The four switches in Figure 2 are MOS power switches;

S

is a P–channel device, and S2, S3 and S4 are N–channel

1

devices. The main difficulty with this approach is that in
integrating the switches, the substrates of S3 and S4 must
always remain reverse–biased with respect to their sources,
but not so much as to degrade their ON resistances. In
addition, at circuit start–up, and under output short circuit
conditions (V

= V+), the output voltage must be sensed

OUT

and the substrate bias adjusted accordingly. Failure to
accomplish this will result in high power losses and probable
device latch–up.

This problem is eliminated in the MC7660 by a logic

network which senses the output voltage (V

) together

OUT

with the level translators, and switches the substrates of S
and S4 to the correct level to maintain necessary reverse bias.

The voltage regulator portion of the MC7660 is an integral

part of the anti–latch–up circuitry. Its inherent voltage drop

can, however, degrade operation at low voltages. To
improve low–voltage operation, the LV pin should be
connected to GND, disabling the regulator. For supply
voltages greater than 3.5V , the L V terminal must be left open
to ensure latch–up–proof operation and prevent device
damage.

Theoretical Power Efficiency Considerations

In theory, a capacitive charge pump can approach 100%

efficiency if certain conditions are met:

(1) The drive circuitry consumes minimal power.
(2) The output switches have extremely low ON

resistance and virtually no offset.

(3) The impedances of the pump and reservoir

capacitors are negligible at the pump frequency.

The MC7660 approaches these conditions for negative

voltage multiplication if large values of C

and C2 are used.

1

Energy is lost only in the transfer of charge between
capacitors if a change in voltage occurs. The energy lost

is defined by:

2

E = 1/2 C

and V2 are the voltages on C1 during the pump and

V

1

1

(V

1

— V

2

)

2

transfer cycles. If the impedances of C1 and C2 are relatively
high at the pump frequency (refer to Figure 2), compared to
the value of R

, there will be a substantial difference in

L

voltages V1 and V2. Therefore, it is not only desirable to
make C2 as large as possible to eliminate output voltage
ripple, but also to employ a correspondingly large value for
C

in order to achieve maximum efficiency of operation.

1

Dos and Don’ts

• Do not exceed maximum supply voltages.

• Do not connect LV terminal to GND for supply voltages

greater than 3.5V.

• Do not short circuit the output to V

+

supply for voltages
above 5.5V for extended periods; however, transient
conditions including start–up are okay.

• When using polarized capacitors in the inverting mode,

3

the + terminal of C

must be connected to pin 2 of the

1

MC7660 and the + terminal of C2 must be connected to
GND Pin 3.

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3

Simple Negative V oltage Converter

Figure 3 shows typical connections to provide a negative
supply where a positive supply is available. A similar
scheme may be employed for supply voltages anywhere in
the operating range of +1.5V to +10V, keeping in mind that
pin 6 (LV) is tied to the supply negative (GND) only for
supply voltages below 3.5V.

The output characteristics of the circuit in Figure 3 are
those of a nearly ideal voltage source in series with 70W.
Thus, for a load current of –10mA and a supply voltage of
+5V, the output voltage would be –4.3V.

The dynamic output impedance of the MC7660 is due,
primarily, to capacitive reactance of the charge transfer
capacitor (C

). Since this capacitor is connected to the output

1

for only 1/2 of the cycle, the equation is:

XC+

where f = 10kHz and C

2

2pfC

= 10µF.

1

+

3.18W,

1

+

V

MC7660

Parallel Devices

paralleled to reduce output resistance (Figure 4). The
reservoir capacitor, C
requires its own pump capacitor, C1. The resultant output
resistance would be approximately:

+

V

8
7
6
5

V

OUT

C2
10 mF

+

C1

10 mF

1
2

+

MC7660

3
4

Figure 3. Simple Negative Converter

Any number of MC7660 voltage converters may be

, serves all devices, while each device

2

R

(of MC7660)

R

OUT

OUT

+

n (number of devices)

8
7
6
5

C1

C1

1
2

MC7660

3
4

Figure 4. Paralleling Devices Lowers Output Impedance

Cascading Devices

The MC7660 may be cascaded as shown (Figure 5) to
produce larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:

V

= –n (VIN)

OUT

where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual MC7660
R

values.

OUT

Changing the MC7660 Oscillator Frequency

It may be desirable in some applications (due to noise or
other considerations) to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an
external clock, as shown in Figure 6. In order to prevent
possible device latch–up, a 1kW resistor must be used in
series with the clock output. In a situation where the designer

1
2

MC7660

3
4

8
7
6
5

R

L

C2

+

has generated the external clock frequency using TTL logic,
the addition of a 10kW pull–up resistor to V+ supply is
required. Note that the pump frequency with external
clocking, as with internal clocking, will be 1/2 of the clock
frequency. Output transitions occur on the positive–going
edge of the clock.

It is also possible to increase the conversion efficiency of
the MC7660 at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is
achieved by connecting an additional capacitor, C

OSC

, as
shown in Figure 7. Lowering the oscillator frequency will
cause an undesirable increase in the impedance of the pump
(C

) and the reservoir (C2) capacitors. To overcome this,

1

increase the values of C1 and C2 by the same factor that the
frequency has been reduced. For example, the addition of a
100pF capacitor between pin 7 (OSC) and pin 8 (V

+

) will
lower the oscillator frequency to 1kHz from its nominal
frequency of 10kHz (a multiple of 10), and necessitate a
corresponding increase in the values of C1 and C2 (from
10µF to 100µF).

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