MOTOROLA MC74VHCT74ADT, MC74VHCT74AD, MC74VHCT74ADR2, MC74VHCT74ADTR2 Datasheet

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SEMICONDUCTOR TECHNICAL DATA

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   

The MC74VHCT74A is an advanced high speed CMOS D–type flip–flop
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.

The signal level applied to the D input is transferred to Q output during the
positive going transition of the Clock pulse.

Reset (RD
accomplished by setting the appropriate input Low.

The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.

The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V , because it has full 5V CMOS
level output swings.

The VHCT74A input structures provide protection when voltages between
0V and 5.5V are applied, regardless of the supply voltage. The output
structures also provide protection when VCC=0V. These input and output
structures help prevent device destruction caused by supply voltage –
input/output voltage mismatch, battery backup, hot insertion, etc.

• High Speed: f

• Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Designed for 4.5V to 5.5V Operating Range

• Low Noise: V

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300mA

• ESD Performance: HBM > 2000V; Machine Model > 200V

• Chip Complexity: 128 FETs or 32 Equivalent Gates

) and Set (SD) are independent of the Clock (CP) and are

= 60MHz (Typ) at VCC = 5V

max

= 0.8V (Max)

OLP

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D SUFFIX

14–LEAD SOIC PACKAGE

CASE 751A–03

14–LEAD TSSOP PACKAGE

14–LEAD SOIC EIAJ PACKAGE

MC74VHCTXXAD
MC74VHCTXXADT
MC74VHCTXXAM

DT SUFFIX

CASE 948G–01

M SUFFIX

CASE 965–01

ORDERING INFORMATION

SOIC
TSSOP
SOIC EIAJ

PIN ASSIGNMENT

LOGIC DIAGRAM

RD1

D1

CP1

SD1

1

2

3

4

5

Q1

6

Q1

RD2

D2

CP2

SD2

13

12

11

10

9

Q2

8

Q2

FUNCTION TABLE

Inputs Outputs

RD CP D Q Q

SD

LH XX HL

HL XX LH

L L X X H* H*
HH H HL
HH L LH
H H L X No Change
H H H X No Change
H H X No Change

*Both outputs will remain high as long as Set and Reset are low, but the output

states are unpredictable if Set and Reset go high simultaneously.

3/98

 Motorola, Inc. 1998

1

REV 0

RD1

D1

CP1
SD1

Q1
Q1

GND

1
2
3
4

6
7

14
13
12
11
105

V

CC

RD2
D2

CP2
SD2

9

Q2

8

Q2

MC74VHCT74A

Î

Î

Î

Î

Î

Î

Î

Î
Î

Î

Î

Î

Î

Î

Î

Î

Î

ОООООООО

V

CC

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

Î

Î

Î

ÎÎÎ

Î

ÎÎÎ

Î

Î

ÎÎÎ

ÎÎÎ

Output Voltage

ÎÎÎ

ÎÎÎ

Î

Î

Î

Î

ÎÎÎ

Î

ÎÎÎ

Î

Î

Î

Output Voltage

Î

Î

ÎÎÎ

Î

ÎÎÎ

Î

Î

ÎÎÎ

ÎÎÎ

Î

Î

Î

Î

ÎÎÎ

Î

ÎÎÎ

Î

Î

Î

Î

Î

Î

ÎÎÎ

Î

ÎÎÎ

Î

Î

ÎÎÎ

ÎÎÎ

MAXIMUM RATINGS*

Symbol

V

V

Î

I
I
I

Î

T

Î

DC Supply Voltage

CC

V

DC Input Voltage

in

DC Output Voltage VCC = 0

out

ОООООООООООО

I

Input Diode Current

IK

Output Diode Current (V

OK

DC Output Current, per Pin

out

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, SOIC Packages†

D

ОООООООООООО

Storage Temperature

stg

ОООООООООООО

* Absolute maximum continuous ratings are those values beyond which damage to the device

may occur. Exposure to these conditions or conditions beyond those indicated may adversely
affect device reliability . Functional operation under absolute–maximum–rated conditions is not
implied.

†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C

TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

Parameter

< GND; V

OUT

High or Low State

> VCC)

OUT

TSSOP Package†

Value

– 0.5 to + 7.0
– 0.5 to + 7.0
– 0.5 to + 7.0

– 0.5 to VCC + 0.5

ÎÎÎÎ

– 20

± 20
± 25
± 50

500
450

ÎÎÎÎ

– 65 to + 150

ÎÎÎÎ

Unit

V
V
V

Î

mA
mA
mA
mA

mW

Î

_

C

Î

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

should be constrained to the

out

range GND v (Vin or V

Unused inputs must always be

) v VCC.

out

tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

RECOMMENDED OPERATING CONDITIONS

Symbol

V

CC

V

in

V

out

ÎÎ

T

A

tr, t

f

DC Supply Voltage
DC Input Voltage
DC Output Voltage VCC = 0

ОООООООООООО

Operating Temperature
Input Rise and Fall Time VCC =5.0V ±0.5V

Parameter

DC ELECTRICAL CHARACTERISTICS

Symbol

V

IH

V

IL

ÎÎ

V

OH

V

OL

ÎÎ

ÎÎÎООООО

I

in

I

CC

ÎÎ

I

CCT

ÎÎ

I

OPD

ÎÎ

Parameter

Minimum High–Level
Input Voltage

Maximum Low–Level

ООООО

Input Voltage
Minimum High–Level

Vin = VIH or V
Maximum Low–Level

ООООО

Vin = VIH or V

IL

IL

Maximum Input
Leakage Current

Maximum Quiescent

ООООО

Supply Current
Quiescent Supply

Current

ООООО

Output Leakage
Current

ООООО

Test Conditions

ОООООÎÎÎ

ООООО

ООООО

Vin = 5.5 V or GND

Vin = VCC or GND

ООООО

Per Input: VIN = 3.4V
Other Input: VCC or GND

ООООО

V

= 5.5V

OUT

ООООО

High or Low State

IOH = – 50µA

IOH = – 8mA

IOL = 50µA

IOL = 8mA

Min

4.5
0
0

Î

0

– 40

0

V

V

4.5 to

5.5

4.5 to

5.5

4.5

4.5

4.5

ÎÎ

4.5

ÎÎ

0 to 5.5

5.5

ÎÎ

5.5

ÎÎ

0

ÎÎ

Max

Unit

5.5

5.5

5.5

Î

V
+ 85

CC

20

V
V
V

Î

_

C

ns/V

TA = 25°C

Min

Typ

2.0

ÎÎÎÎÎ

4.4

4.5

3.94

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎ

0.0

ÎÎ

Max

0.8

ÎÎ

0.1

ÎÎ

0.36

ÎÎ

± 0.1

2.0

ÎÎ

1.35

ÎÎ

0.5

ÎÎ

TA = – 40 to 85°C

Min

Max

2.0

0.8

ÎÎÎÎÎ

4.4

3.80

ÎÎÎÎÎ

ÎÎÎÎÎ

0.1

0.44

± 1.0

ÎÎÎÎÎ

20.0

1.50

ÎÎÎÎÎ

5.0

ÎÎ

ÎÎ

Unit

V

V

Î

V

V

Î

Î

µA

µA

Î

mA

Î

µA

Î

MOTOROLA VHC Data – Advanced CMOS Logic

2

DL203 — Rev 2