MOTOROLA MC74VHCT573AMEL, MC74VHCT573AML1, MC74VHCT573AML2, MC74VHCT573ADWR2, MC74VHCT573ADTR2 Datasheet
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SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1997
6/97
The MC74VHCT573A is an advanced high speed CMOS octal latch with
3–state output fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
This 8–bit D–type latch is controlled by a latch enable input and an output
enable input. When the output enable input is high, the eight outputs are in a
high impedance state.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V , because it has full 5V CMOS
level output swings.
The VHCT573A input and output (when disabled) structures provide
protection when voltages between 0V and 5.5V are applied, regardless of
the supply voltage. These input and output structures help prevent device
destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
• High Speed: tPD = 7.7ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Designed for 4.5V to 5.5V Operating Range
• Low Noise: V
OLP
= 1.6V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 234 FETs or 58.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
11
1
9
8
7
6
5
4
3
219
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
PIN ASSIGNMENT
D4
D2
D1
D0
OE
GND
D7
D6
D5
D3 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
V
CC
LE
Q7
Q6
Q5
Q4
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC74VHCTXXXADW
MC74VHCTXXXADT
MC74VHCTXXXAM
SOIC
TSSOP
SOIC EIAJ
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
OE LE Q
L
L
L
H
H
H
L
X
H
L
No Change
Z
INPUTS OUTPUT
FUNCTION TABLE
D
H
L
X
X
MC74VHCT573A
MOTOROLA VHC Data – Advanced CMOS Logic
DL203 — Rev 1
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage
– 0.5 to + 7.0
V
V
in
DC Input Voltage
– 0.5 to + 7.0
V
Î
Î
V
out
ОООООООООООО
Î
DC Output Voltage Outputs in 3–State
High or Low State
ÎÎÎÎ
Î
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
Î
Î
V
I
IK
Input Diode Current
– 20
mA
I
OK
Output Diode Current (V
OUT
< GND; V
OUT
> VCC)
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
Î
Î
P
D
ОООООООООООО
Î
Power Dissipation in Still Air, SOIC Packages†
TSSOP Package†
ÎÎÎÎ
Î
500
450
Î
Î
mW
Î
Î
T
stg
ОООООООООООО
Î
Storage Temperature
ÎÎÎÎ
Î
– 65 to + 150
Î
Î
_
C
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may adversely
affect device reliability . Functional operation under absolute–maximum–rated conditions is not
implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage
4.5
5.5
V
V
in
DC Input Voltage
0
5.5
V
ÎÎ
Î
V
out
ОООООООООООО
Î
DC Output Voltage Outputs in 3–State
High or Low State
Î
Î
0
0
Î
Î
5.5
V
CC
Î
Î
V
T
A
Operating Temperature
– 40
+ 85
_
C
tr, t
f
Input Rise and Fall Time VCC =5.0V ±0.5V
0
20
ns/V
DC ELECTRICAL CHARACTERISTICS
V
ОООООООО
TA = 25°C
TA = – 40 to 85°C
Symbol
Parameter
Test Conditions
V
CC
V
ÎÎÎ
Min
Typ
ÎÎÎ
Max
Min
Max
Unit
V
IH
Minimum High–Level
Input Voltage
4.5 to
5.5
ÎÎÎ
2.0
ÎÎÎ
2.0
V
ÎÎ
Î
V
IL
ООООО
Î
Maximum Low–Level
Input Voltage
ОООООÎÎÎ
Î
4.5 to
5.5
ÎÎÎ
ÎÎÎÎÎ
Î
ÎÎÎ
ÎÎ
Î
0.8
ÎÎÎÎÎ
Î
0.8
Î
V
V
OH
Minimum High–Level
IOH = – 50µA
4.5
ÎÎÎ
4.4
4.5
ÎÎÎ
4.4
V
Output Voltage
Vin = VIH or V
IL
IOH = – 8mA
4.5
ÎÎÎ
3.94
ÎÎÎ
3.80
ÎÎ
Î
V
OL
ООООО
Î
Maximum Low–Level
ООООО
Î
IOL = 50µA
ÎÎ
Î
4.5
ÎÎÎ
ÎÎÎÎÎ
Î
0.0
ÎÎÎ
ÎÎ
Î
0.1
ÎÎÎÎÎ
Î
0.1
Î
V
ÎÎÎООООО
Î
Output Voltage
Vin = VIH or V
IL
ООООО
Î
IOL = 8mA
ÎÎ
Î
4.5
ÎÎÎ
ÎÎÎÎÎ
Î
ÎÎÎ
ÎÎ
Î
0.36
ÎÎÎÎÎ
Î
0.44
Î
I
in
Maximum Input
Leakage Current
Vin = 5.5 V or GND
0 to 5.5
ÎÎÎ
ÎÎÎ
± 0.1
± 1.0
µA
ÎÎ
Î
I
OZ
ООООО
Î
Maximum 3–State
Leakage Current
ООООО
Î
Vin = VIL or V
IH
V
out
= VCC or GND
ÎÎ
Î
5.5
ÎÎÎ
ÎÎÎÎÎ
Î
ÎÎÎ
ÎÎ
Î
± 0.25
ÎÎÎÎÎ
Î
± 2.5εA
ÎÎ
Î
I
CC
ООООО
Î
Maximum Quiescent
Supply Current
ООООО
Î
Vin = VCC or GND
ÎÎ
Î
5.5
ÎÎÎ
ÎÎÎÎÎ
Î
ÎÎÎ
ÎÎ
Î
4.0
ÎÎÎÎÎ
Î
40.0
Î
µA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74VHCT573A
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS
Unit
TA = – 40 to 85°C
ОООООООО
TA = 25°C
V
CC
V
Test Conditions
Parameter
Symbol
Unit
Max
Min
ÎÎÎ
Max
Typ
ÎÎÎ
Min
V
CC
V
Test Conditions
Parameter
Symbol
ÎÎ
Î
I
CCT
ООООО
Î
Quiescent Supply
Current
ООООО
Î
Per Input: VIN = 3.4V
Other Input: VCC or GND
ÎÎ
Î
5.5
ÎÎÎ
ÎÎÎÎÎ
Î
ÎÎÎ
ÎÎ
Î
1.35
ÎÎÎÎÎ
Î
1.50ÎmA
ÎÎ
Î
I
OPD
ООООО
Î
Output Leakage
Current
ООООО
Î
V
OUT
= 5.5V
ÎÎ
Î
0
ÎÎÎ
ÎÎÎÎÎ
Î
ÎÎÎ
ÎÎ
Î
0.5
ÎÎÎÎÎ
Î
5.0
Î
µA
AC ELECTRICAL CHARACTERISTICS (Input t
r
= tf = 3.0ns)
TA = 25°C
TA = – 40 to 85°C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Unit
ÎÎ
Î
t
PLH
,
t
PHL
ОООООО
Î
Maximum Propagation Delay,
LE to Q
ООООООО
Î
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
ÎÎÎÎ
Î
7.7
8.5
ÎÎ
Î
12.3
13.3
Î
Î
1.0
1.0
ÎÎ
Î
13.5
14.5
ns
ÎÎ
Î
t
PLH
,
t
PHL
ОООООО
Î
Maximum Propagation Delay,
D to Q
ООООООО
Î
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
ÎÎÎÎ
Î
5.1
5.9
ÎÎ
Î
8.5
9.5
Î
Î
1.0
1.0
ÎÎ
Î
9.5
10.5
ns
t
PZL
,
t
PZH
Output Enable Time,
OE
to Q
VCC = 5.0 ± 0.5V CL = 15pF
RL = 1kΩ CL = 50pF
6.3
7.1
10.9
11.9
1.0
1.0
12.5
13.5
ns
ÎÎ
Î
t
PLZ
,
t
PHZ
ОООООО
Î
Output Disable Time,
OE
to Q
ООООООО
Î
VCC = 5.0 ± 0.5V CL = 50pF
RL = 1kΩ
ÎÎÎÎ
Î
8.8
ÎÎ
Î
11.2
Î
Î
1.0
ÎÎ
Î
12.0
ns
ÎÎ
Î
t
OSLH
,
t
OSHL
ОООООО
Î
Output to Output Skew
ООООООО
Î
VCC = 5.5 ± 0.5V CL = 50pF
(Note 1.)
ÎÎÎÎÎÎÎ
Î
1.0
ÎÎÎÎ
Î
1.0
ns
C
in
Maximum Input Capacitance
4
10
10
pF
ÎÎ
Î
C
out
ОООООО
Î
Maximum Three–State Output
Capacitance (Output in
High–Impedance State)
ОООООООÎÎÎÎÎ
Î
6
ÎÎÎÎÎÎÎ
Î
pF
Typical @ 25°C, VCC = 5.0V
C
PD
Power Dissipation Capacitance (Note 2.)
25
pF
1. Parameter guaranteed by design. t
OSLH
= |t
PLHm
– t
PLHn
|, t
OSHL
= |t
PHLm
– t
PHLn
|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= CPD VCC fin + ICC/8 (per latch). CPD is used to determine the no–load
dynamic power consumption; PD = CPD V
CC
2
fin + ICC VCC.
NOISE CHARACTERISTICS (Input t
r
= tf = 3.0ns, CL = 50 pF, VCC = 5.0V)
TA = 25°C
Symbol Parameter
Typ Max
Unit
V
OLP
Quiet Output Maximum Dynamic V
OL
1.2 1.6 V
V
OLV
Quiet Output Minimum Dynamic V
OL
–1.2 –1.6 V
V
IHD
Minimum High Level Dynamic Input Voltage 2.0 V
V
ILD
Maximum Low Level Dynamic Input Voltage 0.8 V
TIMING REQUIREMENTS (Input t
r
= tf = 3.0ns)
TA = 25°C
TA = – 40
to 85°C
Symbol Parameter Test Conditions
Typ Limit Limit
Unit
t
w(h)
Minimum Pulse Width, LE VCC = 5.0 ±0.5V 6.5 8.5 ns
t
su
Minimum Setup Time, D to LE VCC = 5.0 ± 0.5V 1.5 1.5 ns
t
h
Minimum Hold Time, D to LE VCC = 5.0 ± 0.5V 3.5 3.5 ns
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