MOTOROLA MC74VHCT540ADWR2, MC74VHCT540ADT, MC74VHCT540ADTR2, MC74VHCT540ADW Datasheet



SEMICONDUCTOR TECHNICAL DATA

REV 0

 Motorola, Inc. 1999

4/99

  



The MC74VHCT540A is an advanced high speed CMOS inverting octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

The MC74VHCT540A features inputs and outputs on opposite sides of the package and two AND–ed active–low output enables. When either OE1

OE2

are high, the terminal outputs are in the high impedance state.

The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3V to 5.0V , because it has full 5V CMOS level output swings.

The VHCT540A input and output (when disabled) structures provide protection when voltages between 0V and 5.5V are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch, battery backup, hot insertion, etc.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

• High Speed: tPD = 3.7ns (Typ) at VCC = 5V

• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C

• TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Designed for 2V to 5.5V Operating Range

• Low Noise: V

OLP

= 1.2V (Max)

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300mA

• ESD Performance: HBM > 2000V; Machine Model > 200V

• Chip Complexity: 124 FETs or 31 Equivalent Gates

OE1

OE2

OUTPUT

ENABLES

DATA

INPUTS

INVERTING OUTPUTS

LOGIC DIAGRAM



PIN ASSIGNMENT

OE1

GND

A4 5

OE2

L L H X

L L X H

L H X X

FUNCTION TABLE

Inputs

Output Y

OE1 OE2 A

H L Z Z

DW SUFFIX

20–LEAD SOIC WIDE PACKAGE

CASE 751D–05

ORDERING INFORMATION

MC74VHCTXXXADW MC74VHCTXXXADT MC74VHCTXXXAM

SOIC WIDE TSSOP SOIC EIAJ

DT SUFFIX

20–LEAD TSSOP PACKAGE

CASE 948E–02

M SUFFIX

20–LEAD SOIC EIAJ PACKAGE

CASE 967–01

MC74VHCT540A

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

DC Supply Voltage

– 0.5 to + 7.0

DC Input Voltage

– 0.5 to + 7.0

out

DC Output Voltage

– 0.5 to VCC + 0.5

Input Diode Current

– 20

Output Diode Current

± 20

out

DC Output Current, per Pin

± 25

DC Supply Current, VCC and GND Pins

± 75

ОООООООООООО

Power Dissipation in Still Air, SOIC Packages†

TSSOP Package†

ÎÎÎÎ

500 450

stg

Storage Temperature

– 65 to + 150

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions

beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. †Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C

TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

DC Supply Voltage

4.5

5.5

DC Input Voltage

5.5

ÎÎ

out

ОООООООООООО

DC Output Voltage Outputs in 3–State

High or Low State

0 0

5.5

Operating Temperature

– 40

+ 85

tr, t

Input Rise and Fall Time VCC =5.0V ±0.5V

ns/V

DC ELECTRICAL CHARACTERISTICS

TA = 25°C

TA ≤ 85°C

TA ≤ 125°C

Symbol

Parameter

Test Conditions

(V)

Min

Typ

Max

Min

Max

Min

Max

Unit

ОООООО

Minimum High–Level Input Voltage

ОООООÎÎ

3.0

4.5

5.5

1.2

2.0

ÎÎÎÎÎ

1.2

2.0

ÎÎÎ

1.2

2.0

ÎÎÎ

ОООООО

Maximum Low–Level Input Voltage

ОООООÎÎ

3.0

4.5

5.5

ÎÎÎÎÎ

0.53

0.8

ÎÎÎ

0.53

0.8

ÎÎÎ

0.53

0.8

ОООООО

Minimum High–Level Output Voltage

ООООО

VIN = VIH or V

IOH = – 50µA

3.0

4.5

2.9

4.4

3.0

4.5

ÎÎÎ

2.9

4.4

ÎÎÎ

2.9

4.4

ÎÎÎ

ÎÎОООООО

VIN = VIH or V

ООООО

VIN = VIH or V

IOH = – 4mA IOH = – 8mA

3.0

4.5

2.58

3.94

ÎÎÎÎÎ

2.48

3.80

ÎÎÎ

2.34

3.66

ÎÎÎ

Maximum Low–Level Output Voltage

VIN = VIH or V

IOL = 50µA

3.0

4.5

0.0

0.1

ÎÎОООООО

VIN = VIH or V

ООООО

VIN = VIH or V

IOL = 4mA IOL = 8mA

3.0

4.5

ÎÎÎÎÎ

0.36

ÎÎÎ

0.44

ÎÎÎ

0.52

ОООООО

Maximum Input Leakage Current

ООООО

Vin = 5.5 V or GND

0 to 5.5

ÎÎÎÎÎ

± 0.1

ÎÎÎ

± 1.0

ÎÎÎ

± 1.0ÎµA

ОООООО

Maximum Quiescent Supply Current

ООООО

Vin = VCC or GND

5.5

2.0

Î20Î

Î40Î

µA

CCT

Quiescent Supply Current

Input: VIN = 3.4V

5.5

1.35

1.50

1.65

OPD

Output Leakage Current

OUT

= 5.5V

0.0

0.5

5.0

µA

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

MC74VHCT540A

VHC Data – Advanced CMOS Logic DL203 — Rev 2

3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (Input t

= tf = 3.0ns)

ÎÎООООООÎОООООООÎООООО

TA = 25°C

ÎÎÎ

TA = – 40 to

85°C

ÎÎÎ

TA ≤ 125°C

Symbol

Parameter

Test Conditions

Min

Typ

Max

Min

Max

Min

Max

Unit

PLH

PHL

ОООООО

Maximum Propagation Delay, A to Y

ООООООО

VCC = 3.3 ± 0.3V CL = 15pF

CL = 50pF

ÎÎÎ

4.8

7.3

7.0

10.5

1.0

8.5

12.0

ÎÎÎ

10.5

14.0

ÎÎОООООО

(

Figures 1 and 3

)

ООООООО

VCC = 5.0 ± 0.5V CL = 15pF

CL = 50pF

ÎÎÎ

3.7

5.2

5.0

7.0

1.0

6.0

8.0

ÎÎÎ

8.0

10.0

PZL

PZH

ОООООО

Output Enable TIme, OEn

to Y

ООООООО

VCC = 3.3 ± 0.3V CL = 15pF RL = 1kΩ CL = 50pF

ÎÎÎ

6.8

9.3

10.5

14.0

1.0

12.5

16.0

ÎÎÎ

15.0

19.0

ÎÎОООООО

(

Figures 2 and 4

)

ООООООО

VCC = 5.0 ± 0.5V CL = 15pF RL = 1kΩ CL = 50pF

ÎÎÎ

4.7

6.2

7.2

9.2

1.0

8.5

10.5

ÎÎÎ

10.5

13.0

PLZ

PHZ

Output Disable Time, OEn

to Y

VCC = 3.3 ± 0.3V CL = 50pF RL = 1kΩ

11.2

15.4

1.0

17.5

20.0

ÎÎОООООО

(

Figures 2 and 4

)

ООООООО

VCC = 5.0 ± 0.5V CL = 50pF RL = 1kΩ

ÎÎÎ

6.0

8.8

1.0

10.0

ÎÎÎ

11.5

OSLH

OSHL

ОООООО

Output to Output Skew

ООООООО

VCC = 3.3 ± 0.3V CL = 50pF (Note 1.)

ÎÎÎÎÎ

1.5

ÎÎÎ

1.5

ÎÎÎ

2.0Îns

VCC = 5.0 ± 0.5V CL = 50pF (Note 1.)

1.0

1.5

ОООООО

Maximum Input Capacitance

ОООООООÎÎÎÎ

ÎÎÎ

10ÎpF

out

ОООООО

Maximum Three–State Output Capacitance (Output in High Impedance State)

ОООООООÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Typical @ 25°C, VCC = 5.0V

Power Dissipation Capacitance (Note 2.)

1. Parameter guaranteed by design. t

OSLH

= |t

PLHm

– t

PLHn

|, t

OSHL

= |t

PHLm

– t

PHLn

2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I

CC(OPR

)

= CPD  VCC  fin + ICC/8 (per bit). CPD is used to determine the no–load

dynamic power consumption; PD = CPD  V

 fin + ICC  VCC.

NOISE CHARACTERISTICS (Input t

= tf = 3.0ns, CL = 50pF, VCC = 5.0V)

TA = 25°C

Symbol Parameter

Typ Max

Unit

OLP

Quiet Output Maximum Dynamic V

0.9 1.2 V

OLV

Quiet Output Minimum Dynamic V

– 0.9 – 1.2 V

IHD

Minimum High Level Dynamic Input Voltage 3.5 V

ILD

Maximum Low Level Dynamic Input Voltage 1.5 V

+ 5 hidden pages