Motorola MC74LCX16652DT Datasheet
SEMICONDUCTOR TECHNICAL DATA
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The MC74LCX16652 is a high performance, non–inverting 16–bit
transceiver/registered transceiver operating from a 2.7 to 3.6V supply.
The device is byte controlled. Each byte has separate control inputs
which can be tied together for full 16–bit operation. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5V allows MC74LCX16652 inputs to
be safely driven from 5V devices. The MC74LCX16652 is suitable for
memory address driving and all TTL level bus oriented transceiver
applications.
Data on the A or B bus will be clocked into the registers as the
appropriate clock pin goes from a LOW–to–HIGH logic level. Output
Enable pins (OEBAn
outputs. In the transceiver mode, data present at the high impedance port
may be stored in either the A or the B register or in both. The select
controls (SBAn, SABn) can multiplex stored and real–time (transparent
mode) data. In the isolation mode (both outputs disabled), A data may be
stored in the B register or B data may be stored in the A register. When in
the real–time mode, it is possible to store data without using the internal
registers by simultaneously enabling OEAB and OEBA
configuration, each output reinforces its input (data retention is not
guaranteed in this mode).
• Designed for 2.7 to 3.6V V
• 5.7ns Maximum t
, OEABn) are provided to control the transceiver
. In this
Operation
CC
pd
• 5V T olerant — Interface Capability With 5V TTL Logic
• Supports Live Insertion and Withdrawal
• I
Specification Guarantees High Impedance When VCC = 0V
OFF
• LVTTL Compatible
• LVCMOS Compatible
• 24mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (20µA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V; Machine Model >200V
LOW–VOLTAGE CMOS
16–BIT TRANSCEIVER/
REGISTERED TRANSCEIVER
WITH DUAL ENABLE
PLASTIC TSSOP PACKAGE
PIN NAMES
Pins
A0–A15
B0–B15
CABn, CBAn
SABn, SBAn
OEBAn
, OEABn
DT SUFFIX
CASE 1202–01
Function
Side A Inputs/Outputs
Side B Inputs/Outputs
Clock Pulse Inputs
Select Control Inputs
Output Enable Inputs
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
11/96
Motorola, Inc. 1996
1
REV 0.2
MC74LCX16652
OEAB1
V
CC
A4
A10
V
CC
A15
OEAB2
561
552
543
534
525
516
507
498
489
4710
4611
4512
4413
4314
4215
4116
4017
3918
3819
3720
3621
3522
3423
3324
3225
3126
3027
2928
OEBA1
CBA1CAB1
SBA1SAB1
GNDGND
B0A0
B1A1
V
CC
B2A2
B3A3
B4
GNDGND
B5A5
B6A6
B7A7
B8A8
B9A9
B10
GNDGND
B11A11
B12A12
B13A13
V
CC
B14A14
B15
GNDGND
SBA2SAB2
CBA2CAB2
OEBA2
MOTOROLA LCX DATA
2
BR1339 — REV 3
MC74LCX16652
CBA1
OEAB1
OEBA1
SBA1
SAB1
CAB1
55
1
56
54
3
2
A0:7
1 of 8 Channels
LOGIC DIAGRAM
C
Q
D
C
Q
D
B0:7
CBA2
OEAB2
OEBA2
SBA2
SAB2
CAB2
30
28
29
31
26
27
A8:15
To 7 Other Channels
C
Q
D
C
Q
D
B8:15
LCX DATA
BR1339 — REV 3
1 of 8 Channels
To 7 Other Channels
3 MOTOROLA
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