MOTOROLA MC74HCT574AFR2, MC74HCT574AFL2, MC74HCT574ADWR2, MC74HCT574AF, MC74HCT574AFEL Datasheet

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 8

1 Publication Order Number:

MC74HCT574A/D

MC74HCT574A

Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs

High–Performance Silicon–Gate CMOS

The MC74HCT574A is identical in pinout to the LS574. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip–flops, but when Output Enable is high, all device outputs are forced to the high–impedance state. Thus, data may be stored even when the outputs are not enabled.

The HCT574A is identical in function to the HCT374A but has the flip–flop inputs on the opposite side of the package from the outputs to facilitate PC board layout.

• Output Drive Capability: 15 LSTTL Loads

• TTL NMOS Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1.0 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 286 FETs or 71.5 Equivalent Gates

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MARKING

DIAGRAMS

1

20

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week

SOIC WIDE–20

DW SUFFIX CASE 751D

HCT574A

AWLYYWW

PDIP–20 N SUFFIX CASE 738

1

20

MC74HCT574AN

AWLYYWW

1

20

1

20

Device Package Shipping

ORDERING INFORMATION

MC74HCT574AN PDIP–20 1440 / Box MC74HCT574ADW SOIC–WIDE

38 / Rail

MC74HCT574ADWR2 SOIC–WIDE 1000 / Reel

MC74HCT574A

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2

LOGIC DIAGRAM

DATA

INPUTS

D0

219

Q0 D1 D2 D3 D4 D5 D6 D7

CLOCK

OUTPUT ENABLE

3 4 5 6 7 8 9

11

1

18 17 16 15 14 13 12

Q1

Q2

Q3

Q4

Q5

Q6

Q7

NON–

INVERTING

OUTPUTS

PIN 20 = V

CC

PIN 10 = GND

PIN ASSIGNMENT

D4

D2

D1

D0

OUTPUT

ENABLE

GND

D7

D6

D5

D3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q3

Q2

Q1

Q0

V

CC

CLOCK

Q7

Q6

Q5

Q4

FUNCTION TABLE

Inputs Output

OE Clock D Q

LHH LLL L L,H, X No Change HXXZ

X = don’t care Z = high impedance

ОООООООО

Î

Design Criteria

ÎÎ

Î

Value

Î

Units

Internal Gate Count*

71.5

ea

Internal Gate Propagation Delay

1.5

ns

ОООООООО

Î

Internal Gate Power Dissipation

ÎÎ

Î

5.0

Î

µW

ОООООООО

Î

Speed Power Product

ÎÎ

Î

0.0075

Î

pJ

*Equivalent to a two–input NAND gate.

MC74HCT574A

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3

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

ÎÎÎ

Î

750 500

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: –10 mW/_C from 65_ to 125_C

SOIC Package: –7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

4.5

ÎÎ

5.5

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

_

C

tr, t

f

Input Rise and Fall Time (Figure 1)

0

ÎÎ

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООО

Î

Parameter

ООООООО

Î

Test Conditions

ÎÎ

Î

V

CC V

ÎÎ

Î

– 55 to

25_C

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Unit

V

IH

Minimum High–Level Input Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

4.5

5.5

2.0

V

ÎÎ

Î

V

IL

ООООООО

Î

Maximum Low–Level Input Voltage

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

4.5

5.5

ÎÎ

Î

0.8

Î

0.8

ÎÎ

Î

0.8

Î

V

ÎÎ

Î

V

OH

ООООООО

Î

Minimum High–Level Output Voltage

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

4.5

5.5

ÎÎ

Î

4.4

5.4

Î

4.4

5.4

ÎÎ

Î

4.4

5.4

Î

Vin = VIH or V

IL

|I

out

| v 6.0 mA

4.5

3.98

3.84

3.7

V

ÎÎ

Î

V

OL

ООООООО

Î

Maximum Low–Level Output Voltage

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

4.5

5.5

ÎÎ

Î

0.1

Î

0.1

ÎÎ

Î

0.1

Î

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or V

IL

|I

out

| v 6.0 mA

ÎÎ

Î

4.5

ÎÎ

Î

0.26

Î

0.33

ÎÎ

Î

0.4

Î

I

in

Maximum Input Leakage Current

Vin = VCC or GND

5.5

± 0.1

± 1.0

µA

ÎÎ

Î

I

CC

ООООООО

Î

Maximum Quiescent Supply Current (per Package)

ООООООО

Î

Vin = VCC or GND I

out

= 0 µA

ÎÎ

Î

5.5

ÎÎ

Î

4.0

Î

40

ÎÎ

Î

160

Î

µA

1. Output in high–impedance state. NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.