MOTOROLA MC74HCT541AN, MC74HCT541AFL1, MC74HCT541ADWR2, MC74HCT541AF, MC74HCT541AFEL Datasheet

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 2

1 Publication Order Number:

MC74HCT541A/D

MC74HCT541A

Octal 3-State Non-Inverting
Buffer/Line Driver/
Line Receiver With
LSTTL-Compatible Inputs

High–Performance Silicon–Gate CMOS

The MC74HCT541A is identical in pinout to the LS541. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to high speed CMOS inputs.

The HCT541A is an octal non–inverting buffer/line driver/line
receiver designed to be used with 3–state memory address drivers,
clock drivers, and other bus–oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active–low output enables.

• Output Drive Capability: 15 LSTTL Loads

• TTL/NMOS–Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 4.5 to 5.5V

• Low Input Current: 1µA

• In Compliance With the JEDEC Standard No. 7A Requirements

• Chip Complexity: 134 FETs or 33.5 Equivalent Gates

18

Y1

2

A1

17

Y2

3

A2

16

Y3

4

A3

15

Y4

5

A4

14

Y5

6

A5

13

Y6

7

A6

12

Y7

8

A7

11

Y8

9

A8

OE1
OE2

1

19

Output

Enables

Data

Inputs

Non–Inverting
Outputs

PIN 20 = V

CC

PIN 10 = GND

LOGIC DIAGRAM

Pinout: 20–Lead Packages (Top View)

1920 18 17 16 15 14

21 34567

V

CC

13

8

12

9

11

10

OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND

L
L
H
X

L
L
X
H

L
H
X
X

FUNCTION TABLE

Inputs

Output Y

OE1 OE2 A

L
H
Z
Z

Z = High Impedance
X = Don’t Care

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MARKING

DIAGRAMS

1

20

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

SOIC WIDE–20

DW SUFFIX
CASE 751D

HCT541A

AWLYYWW

PDIP–20
N SUFFIX
CASE 738

1

20
MC74HCT541AN

AWLYYWW

1

20

1

20

Device Package Shipping

ORDERING INFORMATION

MC74HCT541AN PDIP–20 1440 / Box
MC74HCT541ADW SOIC–WIDE

38 / Rail

MC74HCT541ADWR2 SOIC–WIDE 1000 / Reel

MC74HCT541A

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2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

ÎÎÎ

Î

750
500

Î

Î

mW

T

stg

Storage Temperature Range

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP or SOIC Package

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

4.5

ÎÎ

5.5

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature Range, All Package Types

– 55

ÎÎ

+ 125

_

C

tr, t

f

Input Rise/Fall Time (Figure 1)

0

ÎÎ

500

ns

DC CHARACTERISTICS (Voltages Referenced to GND)

V

Guaranteed Limit

Symbol Parameter Condition

V

CC

V

–55 to 25°C ≤85°C ≤125°C Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1V or VCC – 0.1V

|I

out

| ≤ 20µA

4.5

5.5

2.0

2.0

2.0

2.0

2.0

2.0

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1V or VCC – 0.1V

|I

out

| ≤ 20µA

4.5

5.5

0.8

0.8

0.8

0.8

0.8

0.8

V

V

OH

Minimum High–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| ≤ 20µA

4.5

5.5

4.4

5.4

4.4

5.4

4.4

5.4

V

Vin = VIH or V

IL|Iout

| ≤ 6.0mA 4.5 3.98 3.84 3.70

V

OL

Maximum Low–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| ≤ 20µA

4.5

5.5

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or V

IL|Iout

| ≤ 6.0mA 4.5 0.26 0.33 0.40

I

in

Maximum Input Leakage Current Vin = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA

I

OZ

Maximum Three–State Leakage
Current

Output in High Impedance State
Vin = VIL or V

IH

V

out

= VCC or GND

5.5 ±0.5 ±5.0 ±10.0 µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0µA

5.5 4 40 160 µA

∆I

CC

Additional Quiescent Supply

Vin = 2.4V , Any One Input

p

≥ –55°C 25 to 125°C

Current

V

in

=

V

CC

or

GND, Oth

er Inputs

I

out

= 0µA

5.5

2.9 2.4

mA

1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

2. Total Supply Current = ICC + Σ∆ICC.

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HCT541A

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3

AC CHARACTERISTICS (V

CC

= 5.0V , CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol Parameter –55 to 25°C ≤85°C ≤125°C Unit

t

PLH

,

t

PHL

Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)

23 28 32 ns

t

PLZ

,

t

PHZ

Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)

30 34 38 ns

t

PZL

,

t

PZH

Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)

30 34 38 ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

12 15 18 ns

C

in

Maximum Input Capacitance 10 10 10 pF

C

out

Maximum Three–State Output Capacitance (Output in High Impedance
State)

15 15 15 pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Buffer)*

55

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Figure 1.

CL*

*Includes all probe and jig capacitance

TEST

POINT

OE1 or OE2

1.3V

3.0V

GND

OUTPUT Y

t

PZL

OUTPUT Y

t

PZH

HIGH
IMPEDANCE

V

OL

V

OH

HIGH
IMPEDANCE

10%

90%

t

PLZ

t

PHZ

1.3V

1.3V

Figure 2.

SWITCHING WAVEFORMS

DEVICE
UNDER

TEST

OUTPUT

TEST CIRCUITS

Figure 3. Figure 4.

CL*

*Includes all probe and jig capacitance

TEST

POINT

DEVICE
UNDER

TEST

OUTPUT

1kΩ

CONNECT TO VCC WHEN
TESTING t

PLZ

AND t

PZL

.
CONNECT TO GND WHEN
TESTING t

PHZ

and t

PZH

.

3.0V

GND

INPUT A

OUTPUT Y

t

PLH

t

PHL

90%

1.3V

10%

t

r

t

TLH

t

f

t

THL

90%

1.3V

10%

1.3V