MOTOROLA MC74HCT374AFL1, MC74HCT374AH, MC74HCT374AN, MC74HCT374ADWR2, MC74HCT374AF Datasheet
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Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 8
1 Publication Order Number:
MC74HCT374A/D
MC74HCT374A
Octal 3-State Noninverting
D Flip-Flop with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT374A may be used as a level converter for
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.
The HCT374A is identical in pinout to the LS374.
Data meeting the setup and hold time is clocked to the outputs with
the rising edge of Clock. The Output Enable does not affect the state of
the flip–flops, but when Output Enable is high, the outputs are forced
to the high–impedance state. Thus, data may be stored even when the
outputs are not enabled.
The HCT374A is identical in function to the HCT574A, which has
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT534A, which has
inverting outputs.
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS–Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 276 FETs or 69 Equivalent Gates
• Improvements over HCT374
— Improved Propagation Delays
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity
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MARKING
DIAGRAMS
1
20
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
SOIC WIDE–20
DW SUFFIX
CASE 751D
HCT374A
AWLYYWW
PDIP–20
N SUFFIX
CASE 738
1
20
MC74HCT374AN
AWLYYWW
TSSOP–20
DT SUFFIX
CASE 948G
1
20
1
20
1
20
Device Package Shipping
ORDERING INFORMATION
MC74HCT374AN PDIP–20 1440 / Box
MC74HCT374ADW SOIC–WIDE
38 / Rail
MC74HCT374ADWR2 SOIC–WIDE 1000 / Reel
MC74HCT374ADT TSSOP–20 75 / Rail
MC74HCT374ADTR2 TSSOP–20
2500 / Reel
HCT
374A
ALYW
1
20
MC74HCT374A
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2
LOGIC DIAGRAM
DATA
INPUTS
D0
11
CLOCK
D1
D2
D3
D4
D5
D6
D7
18
17
14
13
8
7
4
3
1
OUTPUT ENABLE
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
16
15
12
9
6
5
2
PIN 20 = V
CC
PIN 10 = GND
NONINVERTING
OUTPUTS
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
Output
Enable Clock D Q
LHH
LLL
L L,H, X No Change
HXXZ
X = don’t care
Z = high impedance
Q2
D1
D0
Q0
OUTPUT
ENABLE
GND
Q3
D3
D2
Q1 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q6
D6
D7
Q7
V
CC
CLOCK
Q4
D4
D5
Q5
Design Criteria
Value
Units
Internal Gate Count*
69
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
µW
Speed Power Product
.0075
pJ
*Equivalent to a two–input NAND gate.
MC74HCT374A
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3
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 35
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
ÎÎ
Î
P
D
ОООООООООООО
Î
Power Dissipation in Still Air, Plastic DIP†
SOIC Package†
TSSOP Package†
ÎÎÎ
Î
750
500
450
Î
Î
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
ÎÎ
Î
T
L
ОООООООООООО
Î
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
ÎÎÎ
Î
260
Î
Î
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
ÎÎ
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
4.5
ÎÎ
5.5
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
ÎÎ
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
ÎÎ
+ 125
_
C
tr, t
f
Input Rise and Fall Time (Figure 1)
0
ÎÎ
500
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
ÎÎ
Î
Symbol
ООООООО
Î
Parameter
ООООООО
Î
Test Conditions
ÎÎ
Î
V
CC
V
ÎÎ
Î
– 55 to
25_C
ÎÎÎ
Î
Î
Î
v
85_C
ÎÎ
Î
v
125_C
Î
Î
Unit
ÎÎ
Î
V
IH
ООООООО
Î
Minimum High–Level Input
Voltage
ООООООО
Î
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
4.5
5.5
ÎÎ
Î
2.0
2.0
ÎÎÎ
Î
Î
Î
2.0
2.0
ÎÎ
Î
2.0
2.0
Î
Î
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
4.5
5.5
0.8
0.8
ÎÎÎ
0.8
0.8
0.8
0.8
V
ÎÎ
Î
V
OH
ООООООО
Î
Minimum High–Level Output
Voltage
ООООООО
Î
Vin = VIH or V
IL
|I
out
| v 20 µA
ÎÎ
Î
4.5
5.5
ÎÎ
Î
4.4
5.4
ÎÎÎ
Î
Î
Î
4.4
5.4
ÎÎ
Î
4.4
5.4
Î
Î
V
ÎÎÎОООООООÎООООООО
Î
Vin = VIH or V
IL
|I
out
| v 6.0 mA
ÎÎ
Î
4.5
ÎÎ
Î
3.98
ÎÎÎ
Î
Î
Î
3.84
ÎÎ
Î
3.7
Î
Î
V
OL
Maximum Low–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
4.5
5.5
0.1
0.1
ÎÎÎ
0.1
0.1
0.1
0.1
V
ÎÎÎОООООООÎООООООО
Î
Vin = VIH or V
IL
|I
out
| v 6.0 mA
ÎÎ
Î
4.5
ÎÎ
Î
0.26
ÎÎÎ
Î
Î
Î
0.33
ÎÎ
Î
0.4
Î
Î
ÎÎ
Î
I
in
ООООООО
Î
Maximum Input Leakage
Current
ООООООО
Î
Vin = VCC or GND
ÎÎ
Î
5.5
ÎÎ
Î
± 0.1
ÎÎÎ
Î
Î
Î
± 1.0
ÎÎ
Î
± 1.0
Î
Î
µA
ÎÎ
Î
I
OZ
ООООООО
Î
Maximum Three–State
Leakage Current
ООООООО
Î
Output in High–Impedance State
Vin = VIL or V
IH
V
out
= VCC or GND
ÎÎ
Î
5.5
ÎÎ
Î
± 0.5
ÎÎÎ
Î
Î
Î
± 5.0
ÎÎ
Î
± 10
Î
Î
µA
ÎÎ
Î
I
CC
ООООООО
Î
Maximum Quiescent Supply
Current (per Package)
ООООООО
Î
Vin = VCC or GND
I
out
= 0 µA
ÎÎ
Î
5.5
ÎÎ
Î
4.0
ÎÎÎ
Î
Î
Î
40
ÎÎ
Î
160
Î
Î
µA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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