Motorola MC54HCT245AJ, MC74HCT245ASD, MC74HCT245AN, MC74HCT245ADW, MC74HCT245ADT Datasheet

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SEMICONDUCTOR TECHNICAL DATA

3–1

REV 6

 Motorola, Inc. 1995

10/95

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High–Performance Silicon–Gate CMOS

The MC54/74HCT245A is identical in pinout to the LS245. This device
may be used as a level converter for interfacing TTL or NMOS outputs to
High Speed CMOS inputs.

The MC54/74HCT245A is a 3–state noninverting transceiver that is
used for 2–way asynchronous communication between data buses. The
device has an active–low Output Enable pin, which is used to place the
I/O ports into high–impedance states. The Direction control determines
whether data flows from A to B or from B to A.

• Output Drive Capability: 15 LSTTL Loads

• TTL/NMOS Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1.0 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 304 FETs or 76 Equivalent Gates

LOGIC DIAGRAM

A

DATA

PORT

A8

A7

A6

A5

A3
A4

A2

A1

9

8

7

6

5

4

3

2

DIRECTION

OUTPUT ENABLE

1
19

PIN 20 = V

CC

PIN 10 = GND

18
17
16
15
14
13
12
11

B1
B2
B3
B4
B5
B6
B7
B8

B

DATA

PORT

Design Criteria

Value

Units

Internal Gate Count*

76

ea

Internal Gate Propagation Delay

1.0

ns

Internal Gate Power Dissipation

5.0

µW

Speed Power Product

0.005

pJ

*Equivalent to a two–input NAND gate.

FUNCTION TABLE

Control Inputs

Output
Enable

Direction

Operation

L L Data Transmitted from Bus B to Bus A
L H Data Transmitted from Bus A to Bus B
H X Buses Isolated (High–Impedance State)

X = Don’t Care



PIN ASSIGNMENT

A5

A3

A2

A1

DIRECTION

GND

A8

A7

A6

A4 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

B3

B2

B1

OUTPUT ENABLE

V

CC

B8

B7

B6

B5

B4

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ORDERING INFORMATION

MC54HCTXXXAJ
MC74HCTXXXAN
MC74HCTXXXADW
MC74HCTXXXASD
MC74HCTXXXADT

Ceramic
Plastic
SOIC
SSOP
TSSOP

DT SUFFIX

TSSOP PACKAGE

CASE 948E–02

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

1

20

1

20

SD SUFFIX

SSOP PACKAGE

CASE 940C–03

1

20

1

20

1

20

MC54/74HCT245A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

3–2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

P

D

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

SSOP or TSSOP Package†

750
500
450

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC, SSOP or TSSOP Package)

(Ceramic DIP)

260
300

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
SSOP or TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

4.5

5.5

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time (Figure 1)

0

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

4.5

5.5

2.0

2.0

2.0

2.0

2.0

2.0

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

4.5

5.5

0.8

0.8

0.8

0.8

0.8

0.8

V

V

OH

Minimum High–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

4.5

5.5

4.4

5.4

4.4

5.4

4.4

5.4

V

Vin = VIH or V

IL

|I

out

| v 6.0 mA

4.5

3.98

3.84

3.7

V

OL

Maximum Low–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

4.5

5.5

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or V

IL

|I

out

| v 6.0 mA

4.5

0.26

0.33

0.4

I

in

Maximum Input Leakage Current

Vin = VCC or GND, Pins 1 or 19

5.5

± 0.1

± 1.0

± 1.0

µA

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC54/74HCT245A

High–Speed CMOS Logic Data
DL129 — Rev 6

3–3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

V

CC

V

Test Conditions

Parameter

Symbol

Unit

v

125_C

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

5.5

4.0

40

160

µA

I

OZ

Maximum Three–State
Leakage Current

Output in High–Impedance State
Vin = VIL or V

IH

V

out

= VCC or GND, I/O Pins

5.5

± 0.5

± 5.0

± 10

µA

∆I

CC

Additional Quiescent Supply

Vin = 2.4 V, Any One Input

≥ –55_C

25_C to 125_C

Current

Vin = VCC or GND, Other Inputs
l

out

= 0 µA

5.5

2.9

2.4

mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (V

CC

= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

Symbol

Parameter

– 55 to

25_C

v

85_C

v

125_C

Unit

t

PLH

,

t

PHL

Maximum Propagation Delay, A to B or B to A

(Figures 1 and 3)

22

28

33

ns

t

PLZ

,

t

PHZ

Maximum Propagation Delay, Output Enable to A or B

(Figures 2 and 4)

30

36

42

ns

t

PZL

,

t

PZH

Maximum Propagation Delay, Output Enable to A or 8

(Figures 2 and 4)

30

36

42

ns

t

TLH

,

t

THL

Maximum Output Transition Time. any Output

(Figures 1 and 3)

12

15

18

ns

C

in

Maximum Input Capacitance (Pin 1 or 19)

10

10

10

pF

C

out

Maximum Three–State I/O Capacitance, (I/O in High–Impedance State)

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Enabled Output)*

97

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).