MOTOROLA MC74HCT244ADT, MC74HCT244AH, MC74HCT244AF, MC74HCT244AFEL, MC74HCT244AFL1 Datasheet

 Semiconductor Components Industries, LLC, 2000

May, 2000 – Rev. 9

1 Publication Order Number:

MC74HCT244A/D

MC74HCT244A Octal 3-State Noninverting

Buffer/Line Driver/ Line Receiver with LSTTL-Compatible Inputs

High–Performance Silicon–Gate CMOS

The MC74HCT244A is identical in pinout to the LS244. This device may be used as a level converter for interfacing TTL or NMOS outputs to High–Speed CMOS inputs. The HCT244A is an octal noninverting buffer line driver line receiver designed to be used with 3–state memory address drivers, clock drivers, and other bus–oriented systems. The device has non–inverted outputs and two active–low output enables.

The HCT244A is the noninverting version of the HCT240. See also HCT241.

• Output Drive Capability: 15 LSTTL Loads

• TTL NMOS–Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 112 FETs or 28 Equivalent Gates

LOGIC DIAGRAM

DATA INPUTS

A1

A2

A3

A4

B1

B2

B3

B4

17

15

13

11

8

6

4

218

16

14

12

9

7

5

3

YB4

YB3

YB2

YB1

YA4

YA3

YA2

YA1

NONINVERTING OUTPUTS

PIN 20 = V

CC

PIN 10 = GND

OUTPUT

ENABLES

ENABLE A ENABLE B

1 19

FUNCTION TABLE

Inputs Outputs

Enable A, Enable B A, B YA, YB

LLL LHH HXZ

Z = high impedance, X = don’t care

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MARKING

DIAGRAMS

1

20

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week

SOIC WIDE–20

DW SUFFIX CASE 751D

HCT244A

AWLYYWW

PDIP–20 N SUFFIX CASE 738

1

20 MC74HCT244AN

AWLYYWW

TSSOP–20 DT SUFFIX

CASE 948E

1

20

1

20

1

20

Device Package Shipping

ORDERING INFORMATION

MC74HCT244AN PDIP–20 1440 / Box MC74HCT244ADW SOIC–WIDE

38 / Rail MC74HCT244ADWR2 SOIC–WIDE 1000 / Reel MC74HCT244ADT TSSOP–20 75 / Rail MC74HCT244ADTR2 TSSOP–20

2500 / Reel

HCT

244A

ALYW

1

20

PIN ASSIGNMENT

A3

A2

YB4

A1

ENABLE A

GND

YB1

A4

YB2

YB3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

YA2

B4

YA1

ENABLE B

V

CC

B1

YA4

B2

YA3

B3

MC74HCT244A

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2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎ

Î

750 500 450

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC, SSOP or TSSOP Package)

ÎÎÎ

Î

260

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

4.5

ÎÎ

5.5

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

_

C

tr, t

f

Input Rise and Fall Time (Figure 1)

0

ÎÎ

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООО

Î

Parameter

ООООООО

Î

Test Conditions

ÎÎ

Î

V

CC V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Unit

ÎÎ

Î

V

IH

ООООООО

Î

Minimum High–Level Input Voltage

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

4.5

5.5

ÎÎ

Î

2 2

ÎÎÎ

Î

2 2

ÎÎ

Î

2 2

Î

V

IL

Maximum Low–Level Input Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

4.5

5.5

0.8

ÎÎÎ

0.8

V

ÎÎ

Î

V

OH

ООООООО

Î

Minimum High–Level Output Voltage

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

4.5

5.5

ÎÎ

Î

4.4

5.4

ÎÎÎ

Î

4.4

5.4

ÎÎ

Î

4.4

5.4

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or V

IL

|I

out

| v 6 mA

ÎÎ

Î

4.5

ÎÎ

Î

3.98

ÎÎÎ

Î

3.84

ÎÎ

Î

3.7

Î

V

OL

Maximum Low–Level Output Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

4.5

5.5

0.1

ÎÎÎ

0.1

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or V

IL

|I

out

| v 6 mA

ÎÎ

Î

4.5

ÎÎ

Î

0.26

ÎÎÎ

Î

0.33

ÎÎ

Î

0.4

Î

ÎÎ

Î

I

in

ООООООО

Î

Maximum Input Leakage Current

ООООООО

Î

Vin = VCC or GND

ÎÎ

Î

5.5

ÎÎ

Î

± 0.1

ÎÎÎ

Î

± 1.0

ÎÎ

Î

± 1.0

Î

µA

ÎÎ

Î

I

OZ

ООООООО

Î

Maximum Three–State Leakage Current

ООООООО

Î

Output in High–Impedance State Vin = VIL or V

IH

V

out

= VCC or GND

ÎÎ

Î

5.5

ÎÎ

Î

± 0.5

ÎÎÎ

Î

± 5.0

ÎÎ

Î

± 10

Î

µA

ÎÎ

Î

I

CC

ООООООО

Î

Maximum Quiescent Supply Current (per Package)

ООООООО

Î

Vin = VCC or GND I

out

= 0 µA

ÎÎ

Î

5.5

ÎÎ

Î

4

ÎÎÎ

Î

40

ÎÎ

Î

160

Î

µA

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

MC74HCT244A

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3

∆I

CC

Additional Quiescent Supply

Vin = 2.4 V, Any One Input

p

≥ –55_C

25_C to 125_C

Current

V

i

n

=

V

CC

or

GND, Other In uts

l

out

= 0 µA

5.5

2.9

2.4

mA

NOTES:

1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

2. Total Supply Current = ICC + Σ∆ICC.

AC ELECTRICAL CHARACTERISTICS (V

CC

= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

– 55 to

25_C

v

85_C

v

125_C

Unit

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООООО

Î

Maximum Propagation Delay, A to YA or B to YB

(Figures 1 and 3)

ÎÎ

Î

20

ÎÎ

Î

25

ÎÎ

Î

30

Î

ns

ÎÎÎ

Î

t

PLZ

,

t

PHZ

ОООООООООООООООО

Î

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

ÎÎ

Î

26

ÎÎ

Î

33

ÎÎ

Î

39

Î

ns

ÎÎÎ

Î

t

PZL

,

t

PZH

ОООООООООООООООО

Î

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

ÎÎ

Î

22

ÎÎ

Î

28

ÎÎ

Î

33

Î

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

12

15

18

ns

C

in

Maximum Input Capacitance

10

pF

ÎÎÎ

Î

C

out

ОООООООООООООООО

Î

Maximum Three–State Output Capacitance (Output in High–Impedance State)

ÎÎ

Î

15

ÎÎ

Î

15

ÎÎ

Î

15

Î

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Enabled Output)*

55

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

SWITCHING W AVEFORMS

Figure 1. Figure 2.

3 V

GND

t

f

t

r

INPUT

A OR B

OUTPUT

YA OR YB

0.3 V

1.3 V

2.7 V

10%

1.3 V

90%

t

TLH

t

PLH

t

PHL

t

THL

ENABLE

A OR B

OUTPUT Y

1.3 V

90%

10%

t

PZL

t

PLZ

t

PZHtPHZ

3 V

GND HIGH

IMPEDANCE V

OL

V

OH

HIGH IMPEDANCE