SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1995
10/95
" !
High–Performance Silicon–Gate CMOS
The MC54/74HC86A i s identical in pinout to the LS86; this device is
similar in function to the MM74C86 and L86, but has a different pinout. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 56 FETs or 14 Equivalent Gates
LOGIC DIAGRAM
Y1
Y2
Y3
Y4
A1
B1
A2
B2
A3
B3
A4
B4
1
2
4
5
9
10
12
13
3
6
8
11
PIN 14 = V
CC
PIN 7 = GND
Y = A ⊕ B
= A
B + AB
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
FUNCTION TABLE
PIN ASSIGNMENT
A
L
L
H
H
11
12
13
14
8
9
105
4
3
2
1
7
6
B3
Y4
A4
B4
V
CC
Y3
A3
A2
Y1
B1
A1
GND
Y2
B2
Inputs Output
B
L
H
L
H
Y
L
H
H
L
D SUFFIX
SOIC PACKAGE
CASE 751A–03
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ORDERING INFORMATION
MC54HCXXAJ
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
Ceramic
Plastic
SOIC
TSSOP
1
14
1
14
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
1
14
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
1
14
MC54/74HC86A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
TSSOP Package†
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Minimum High–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
Minimum High–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
Vin = VIH or VIL|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.