MOTOROLA MC74HC74AFL2, MC74HC74AFR1, MC74HC74AFR2, MC74HC74ADTR2, MC74HC74AF Datasheet

...

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 8

1 Publication Order Number:

MC74HC74A/D

MC74HC74A

Dual D Flip-Flop with Set and Reset

High–Performance Silicon–Gate CMOS

The MC74HC74A is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of two D flip–flops with individual Set, Reset, and Clock inputs. Information at a D–input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q

outputs are available from each flip–flop. The Set

and Reset inputs are asynchronous.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 128 FETs or 32 Equivalent Gates

LOGIC DIAGRAM

RESET 1

DATA 1

CLOCK 1

SET 1

RESET 2

DATA 2

CLOCK 2

SET 2

2 3

12 11

5 6

9 8

PIN 14 = VCC PIN 7 = GND

FUNCTION TABLE

Inputs Outputs

Set Reset Clock Data Q Q

LH XX HL HL XX LH L L X X H* H* HH H HL HH L LH H H L X No Change H H H X No Change H H X No Change

*Both outputs will remain high as long as Set and Reset are low, but the output

states are unpredictable if Set and Reset go high simultaneously.

Device Package Shipping

ORDERING INFORMATION

MC74HC74AN PDIP–14 2000 / Box MC74HC74AD SOIC–14

http://onsemi.com

55 / Rail

MC74HC74ADR2 SOIC–14 2500 / Reel

MARKING

DIAGRAMS

A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

MC74HC74ADT TSSOP–14 96 / Rail MC74HC74ADTR2 TSSOP–14

2500 / Reel

TSSOP–14 DT SUFFIX

CASE 948G

74A

ALYW

PDIP–14

N SUFFIX

CASE 646

MC74HC74AN

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

HC74A

AWLYWW

PIN ASSIGNMENT

SET 1

CLOCK 1

DATA 1

RESET 1

105

SET 2

CLOCK 2

DATA 2

RESET 2

GND

MC74HC74A

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MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

DC Input Current, per Pin

± 20

out

DC Output Current, per Pin

± 25

DC Supply Current, VCC and GND Pins

± 50

ÎÎ

ОООООООООООО

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎ

750 500 450

stg

Storage Temperature

– 65 to + 150

ÎÎ

ОООООООООООО

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

ÎÎÎ

260 300

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

DC Supply Voltage (Referenced to GND)

2.0

ÎÎ

6.0

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎ

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

ÎÎ

tr, t

ООООООООООООО

Input Rise and Fall Time VCC = 2.0 V

(Figures 1, 2, 3) VCC = 3.0 V

VCC = 4.5 V VCC = 6.0 V

0 0 0 0

ÎÎ

1000

600 500 400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Symbol

ООООООО

Parameter

ООООООО

Test Conditions

ÎÎ

CC V

ÎÎ

– 55 to

25_C

ÎÎÎ

85_C

ÎÎ

125_C

Unit

ÎÎ

ООООООО

Minimum High–Level Input Voltage

ООООООО

out

= 0.1 V or VCC – 0.1 V

out

| v 20 µA

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

1.5

2.1

3.15

4.2

ÎÎÎ

1.5

2.1

3.15

4.2

ÎÎ

1.5

2.1

3.15

4.2

ÎÎ

ООООООО

Maximum Low–Level Input Voltage

ООООООО

out

= 0.1 V or VCC – 0.1 V

out

| v 20 µA

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

0.5

0.9

1.35

1.8

ÎÎÎ

0.5

0.9

1.35

1.8

ÎÎ

0.5

0.9

1.35

1.8

ÎÎ

ООООООО

Minimum High–Level Output Voltage

ООООООО

Vin = VIH or V

out

| v 20 µA

ÎÎ

2.0

4.5

6.0

ÎÎ

1.9

4.4

5.9

ÎÎÎ

1.9

4.4

5.9

ÎÎ

1.9

4.4

5.9

ÎÎÎОООООООÎООООООО

Vin = VIH or VIL|I

out

| v 2.4 mA

out

| v 4.0 mA

out

| v 5.2 mA

ÎÎ

3.0

4.5

6.0

ÎÎ

2.48

3.98

5.48

ÎÎÎ

2.34

3.84

5.34

ÎÎ

2.2

3.7

5.2

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

MC74HC74A

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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

Test Conditions

Parameter

Symbol

Unit

125_C

ÎÎÎ

85_C

– 55 to

25_C

Test Conditions

Parameter

Symbol

ÎÎ

ООООООО

Maximum Low–Level Output Voltage

ООООООО

Vin = VIH or V

out

| v 20 µA

ÎÎ

2.0

4.5

6.0

ÎÎ

0.1

ÎÎÎ

0.1

ÎÎ

0.1

ÎÎÎОООООООÎООООООО

Vin = VIH or VIL|I

out

| v 2.4 mA

out

| v 4.0 mA

out

| v 5.2 mA

ÎÎ

3.0

4.5

6.0

ÎÎ

0.26

ÎÎÎ

0.33

ÎÎ

0.4

ÎÎ

ООООООО

Maximum Input Leakage Current

ООООООО

Vin = VCC or GND

ÎÎ

6.0

ÎÎ

± 0.1

ÎÎÎ

± 1.0

ÎÎ

± 1.0

µA

Maximum Quiescent Supply Current (per Package)

Vin = VCC or GND I

out

= 0 µA

6.0

2.0

ÎÎÎ

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

= 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

ÎÎÎ

Symbol

ОООООООООООООО

Parameter

ÎÎ

CC V

ÎÎ

– 55 to

25_C

ÎÎÎ

85_C

ÎÎ

125_C

Unit

ÎÎÎ

max

ОООООООООООООО

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

6.0 15 30 35

ÎÎÎ

4.8 10 24 28

ÎÎ

4.0

8.0 20 24

MHz

ÎÎÎ

PLH

PHL

ОООООООООООООО

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

100

75 20 17

ÎÎÎ

125

90 25 21

ÎÎ

150 120

30 26

ÎÎÎ

PLH

PHL

ОООООООООООООО

Maximum Propagation Delay, Set or Reset to Q or Q

(Figures 2 and 4)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

105

80 21 18

ÎÎÎ

130

95 26 22

ÎÎ

160 130

32 27

ÎÎÎ

TLH

THL

ОООООООООООООО

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

75 30 15 13

ÎÎÎ

95 40 19 16

ÎÎ

110

55 22 19

Maximum Input Capacitance

—

ÎÎÎ

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

Power Dissipation Capacitance (Per Flip–Flop)*

*Used to determine the no–load dynamic power consumption: PD = CPD V

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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