MOTOROLA MC74HC74AFL2, MC74HC74AFR1, MC74HC74AFR2, MC74HC74ADTR2, MC74HC74AF Datasheet

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 8

1 Publication Order Number:

MC74HC74A/D

MC74HC74A

Dual D Flip-Flop with Set
and Reset

High–Performance Silicon–Gate CMOS

The MC74HC74A is identical in pinout to the LS74. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.

This device consists of two D flip–flops with individual Set, Reset,
and Clock inputs. Information at a D–input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q

outputs are available from each flip–flop. The Set

and Reset inputs are asynchronous.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 128 FETs or 32 Equivalent Gates

LOGIC DIAGRAM

RESET 1

DATA 1

CLOCK 1

SET 1

RESET 2

DATA 2

CLOCK 2

SET 2

1

2
3

4

13

12
11

10

5
6

9
8

Q1

Q1

Q2

Q2

PIN 14 = VCC
PIN 7 = GND

FUNCTION TABLE

Inputs Outputs

Set Reset Clock Data Q Q

LH XX HL
HL XX LH
L L X X H* H*
HH H HL
HH L LH
H H L X No Change
H H H X No Change
H H X No Change

*Both outputs will remain high as long as Set and Reset are low, but the output

states are unpredictable if Set and Reset go high simultaneously.

Device Package Shipping

ORDERING INFORMATION

MC74HC74AN PDIP–14 2000 / Box
MC74HC74AD SOIC–14

http://onsemi.com

55 / Rail

MC74HC74ADR2 SOIC–14 2500 / Reel

MARKING

DIAGRAMS

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

MC74HC74ADT TSSOP–14 96 / Rail
MC74HC74ADTR2 TSSOP–14

2500 / Reel

TSSOP–14
DT SUFFIX

CASE 948G

HC

74A

ALYW

1

14

1

14

PDIP–14

N SUFFIX

CASE 646

MC74HC74AN

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

1

14

HC74A

AWLYWW

PIN ASSIGNMENT

SET 1

CLOCK 1

DATA 1

RESET 1

11

12

13

14

8

9

105

4

3

2

1

7

6

SET 2

CLOCK 2

DATA 2

RESET 2

V

CC

Q2

Q2

GND

Q1

Q1

MC74HC74A

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2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎ

Î

750
500
450

Î

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

ÎÎÎ

Î

260
300

Î

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

ÎÎ

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

_

C

ÎÎ

Î

ÎÎ

Î

tr, t

f

ООООООООООООО

Î

ООООООООООООО

Î

Input Rise and Fall Time VCC = 2.0 V

(Figures 1, 2, 3) VCC = 3.0 V

VCC = 4.5 V
VCC = 6.0 V

Î

Î

Î

Î

0
0
0
0

ÎÎ

ÎÎ

ÎÎ

1000

600
500
400

Î

Î

Î

Î

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООО

Î

Parameter

ООООООО

Î

Test Conditions

ÎÎ

Î

V

CC
V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

Î

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎ

Î

ÎÎ

Î

V

IH

ООООООО

Î

ООООООО

Î

Minimum High–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

ÎÎÎ

Î

Î

Î

Î

Î

Î

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

Î

Î

Î

Î

V

ÎÎ

Î

ÎÎ

Î

V

IL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.8

ÎÎÎ

Î

Î

Î

Î

Î

Î

0.5

0.9

1.35

1.8

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.8

Î

Î

Î

Î

V

ÎÎ

Î

ÎÎ

Î

V

OH

ООООООО

Î

ООООООО

Î

Minimum High–Level Output
Voltage

ООООООО

Î

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.9

4.4

5.9

ÎÎÎ

Î

Î

Î

Î

Î

Î

1.9

4.4

5.9

ÎÎ

Î

ÎÎ

Î

1.9

4.4

5.9

Î

Î

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

2.48

3.98

5.48

ÎÎÎ

Î

Î

Î

2.34

3.84

5.34

ÎÎ

Î

2.2

3.7

5.2

Î

Î

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC74A

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3

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

V

CC

V

Test Conditions

Parameter

Symbol

Unit

v

125_C

ÎÎÎ

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

ÎÎ

Î

ÎÎ

Î

V

OL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Output
Voltage

ООООООО

Î

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

0.1

0.1

0.1

ÎÎÎ

Î

Î

Î

Î

Î

Î

0.1

0.1

0.1

ÎÎ

Î

ÎÎ

Î

0.1

0.1

0.1

Î

Î

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

0.26

0.26

0.26

ÎÎÎ

Î

Î

Î

0.33

0.33

0.33

ÎÎ

Î

0.4

0.4

0.4

Î

Î

ÎÎ

Î

I

in

ООООООО

Î

Maximum Input Leakage
Current

ООООООО

Î

Vin = VCC or GND

ÎÎ

Î

6.0

ÎÎ

Î

± 0.1

ÎÎÎ

Î

Î

Î

± 1.0

ÎÎ

Î

± 1.0

Î

Î

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

2.0

ÎÎÎ

20

80

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

ÎÎÎ

Î

Symbol

ОООООООООООООО

Î

Parameter

ÎÎ

Î

V

CC
V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

Î

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎÎ

Î

ÎÎÎ

Î

f

max

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

6.0
15
30
35

ÎÎÎ

Î

Î

Î

Î

Î

Î

4.8
10
24
28

ÎÎ

Î

ÎÎ

Î

4.0

8.0
20
24

Î

Î

Î

Î

MHz

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

100

75
20
17

ÎÎÎ

Î

Î

Î

125

90
25
21

ÎÎ

Î

150
120

30
26

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Propagation Delay, Set or Reset to Q or Q

(Figures 2 and 4)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

105

80
21
18

ÎÎÎ

Î

Î

Î

Î

Î

Î

130

95
26
22

ÎÎ

Î

ÎÎ

Î

160
130

32
27

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

TLH

,

t

THL

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

75
30
15
13

ÎÎÎ

Î

Î

Î

Î

Î

Î

95
40
19
16

ÎÎ

Î

ÎÎ

Î

110

55
22
19

Î

Î

Î

Î

ns

C

in

Maximum Input Capacitance

—

10

ÎÎÎ

10

10

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Flip–Flop)*

32

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

MC74HC74A

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4

TIMING REQUIREMENTS (Input t

r

= tf = 6.0 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

ÎÎÎ

v

85_Cv 125_C

Unit

ÎÎÎ

Î

ÎÎÎ

Î

t

su

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Setup Time, Data to Clock

(Figure 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

80
35
16
14

ÎÎÎ

Î

Î

Î

Î

Î

Î

100

45
20
17

ÎÎ

Î

ÎÎ

Î

120

55
24
20

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

h

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Hold Time, Clock to Data

(Figure 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

3.0

3.0

3.0

3.0

ÎÎÎ

Î

Î

Î

Î

Î

Î

3.0

3.0

3.0

3.0

ÎÎ

Î

ÎÎ

Î

3.0

3.0

3.0

3.0

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

rec

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Recovery Time, Set or Reset Inactive to Clock

(Figure 2)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

8.0

8.0

8.0

8.0

ÎÎÎ

Î

Î

Î

Î

Î

Î

8.0

8.0

8.0

8.0

ÎÎ

Î

ÎÎ

Î

8.0

8.0

8.0

8.0

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

w

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Pulse Width, Clock

(Figure 1)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

60
25
12
10

ÎÎÎ

Î

Î

Î

Î

Î

Î

75
30
15
13

ÎÎ

Î

ÎÎ

Î

90
40
18
15

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

t

w

ОООООООООООООО

Î

ОООООООООООООО

Î

Minimum Pulse Width, Set or Reset

(Figure 2)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

60
25
12
10

ÎÎÎ

Î

Î

Î

Î

Î

Î

75
30
15
13

ÎÎ

Î

ÎÎ

Î

90
40
18
15

Î

Î

Î

Î

ns

ÎÎÎ

Î

ÎÎÎ

Î

tr, t

f

ОООООООООООООО

Î

ОООООООООООООО

Î

Maximum Input Rise and Fall Times

(Figures 1, 2, 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1000

800
500
400

ÎÎÎ

Î

Î

Î

Î

Î

Î

1000

800
500
400

ÎÎ

Î

ÎÎ

Î

1000

800
500
400

Î

Î

Î

Î

ns

MC74HC74A

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5

SWITCHING W AVEFORMS

Figure 1.

Figure 2.

50%

50%

50%

50%

V

CC

V

CC

GND

GND

SET OR

RESET

Q

OR Q

Q OR Q

CLOCK

t

PLH

t

PHL

50%

DATA

CLOCK

V

CC

V

CC

GND

Figure 3.

VALID

GND

t

su

t

h

t

rec

t

w

EXPANDED LOGIC DIAGRAM

SET

DATA

RESET

4, 10

2, 12

1, 13

CLOCK

3, 11

5, 9

6, 8

Q

Q

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

Figure 4.

1/f

max

CLOCK

Q or Q

t

f

t

r

V

CC

GND

90%

50%

10%

90%

50%

10%

t

PLH

t

PHL

t

TLH

t

THL

t

w

50%

MC74HC74A

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6

P ACKAGE DIMENSIONS

PDIP–14

N SUFFIX

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

4. ROUNDED CORNERS OPTIONAL.

17

14 8

B

A

F

HG D

K

C

N

L

J

M

SEATING
PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78

G 0.100 BSC 2.54 BSC

H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC

M 0 10 0 10

N 0.015 0.039 0.39 1.01

____

SOIC–14

D SUFFIX

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

G

P

7 PL

14 8

71

M

0.25 (0.010) B

M

S

B

M

0.25 (0.010) A

S

T

–T–

F

R

X 45

SEATING
PLANE

D 14 PL

K

C

J

M

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

____

MC74HC74A

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7

P ACKAGE DIMENSIONS

TSSOP–14

DT SUFFIX

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V

S

T

L

–U–

SEATING
PLANE

0.10 (0.004)

–T–

SECTION N–N

DETAIL E

J

J1

K

K1

DETAIL E

F

M

–W–

0.25 (0.010)

8

14

7

1

PIN 1
IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

–V–

14X REFK

N

N

MC74HC74A

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8

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