Motorola MC74HC595ADT, MC74HC595AD Datasheet



SEMICONDUCTOR TECHNICAL DATA

REV 7

 Motorola, Inc. 1997

3/97

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High–Performance Silicon–Gate CMOS

The MC54/74HC595A is identical in pinout to the LS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The HC595A consists of an 8–bit shift register and an 8–bit D–type latch with three–state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8–bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register.

The HC595A directly interfaces with the Motorola SPI serial data port on CMOS MPUs and MCUs.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 328 FETs or 82 Equivalent Gates

• Improvements over HC595

— Improved Propagation Delays — 50% Lower Quiescent Power — Improved Input Noise and Latchup Immunity

LOGIC DIAGRAM

SERIAL

DATA

INPUT

12 13

SHIFT

CLOCK RESET

LATCH

CLOCK

OUTPUT

ENABLE

SHIFT

LATCH

1 2 3

4 5 6 7

VCC = PIN 16 GND = PIN 8

PARALLEL

DATA

OUTPUTS

SERIAL

DATA

OUTPUT



PIN ASSIGNMENT

125

LATCH CLOCK

OUTPUT ENABLE

RESET

SHIFT CLOCK

GND

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT

Ceramic Plastic SOIC TSSOP

DT SUFFIX

TSSOP PACKAGE

CASE 948F–01

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

MC54/74HC595A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

DC Input Current, per Pin

± 20

out

DC Output Current, per Pin

± 35

DC Supply Current, VCC and GND Pins

± 75

ОООООООООООО

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎ

750 500 450

stg

Storage Temperature

– 65 to + 150

ОООООООООООО

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

(Ceramic DIP)

ÎÎÎÎ

260 300

*Maximum Ratings are those values beyond which damage to the device may occur .

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

DC Supply Voltage (Referenced to GND)

2.0

6.0

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

Operating Temperature, All Package Types

– 55

+ 125

ÎÎ

tr, t

ОООООООООООО

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

0 0 0

1000

500 400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Symbol

ООООООО

Parameter

ООООООО

Test Conditions

ÎÎ

– 55 to

25_C

ÎÎ

85_C

ÎÎ

125_C

Unit

ÎÎ

ООООООО

Minimum High–Level Input Voltage

ООООООО

out

= 0.1 V or VCC – 0.1 V

out

| v 20 µA

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

1.5

2.1

3.15

4.2

ÎÎ

1.5

2.1

3.15

4.2

ÎÎ

1.5

2.1

3.15

4.2

ÎÎ

ООООООО

Maximum Low–Level Input Voltage

ООООООО

out

= 0.1 V or VCC – 0.1 V

out

| v 20 µA

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

0.5

0.9

1.35

1.8

ÎÎ

0.5

0.9

1.35

1.8

ÎÎ

0.5

0.9

1.35

1.8

ÎÎ

ООООООО

Minimum High–Level Output Voltage, QA – Q

ООООООО

Vin = VIH or V

out

| v 20 µA

ÎÎ

2.0

4.5

6.0

ÎÎ

1.9

4.4

5.9

ÎÎ

1.9

4.4

5.9

ÎÎ

1.9

4.4

5.9

ÎÎÎОООООООÎООООООО

Vin = VIH or VIL|I

out

| v 2.4 mA

out

| v 6.0 mA

out

| v 7.8 mA

ÎÎ

3.0

4.5

6.0

ÎÎ

2.48

3.98

5.48

ÎÎ

2.34

3.84

5.34

ÎÎ

2.2

3.7

5.2

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

MC54/74HC595A

High–Speed CMOS Logic Data DL129 — Rev 6

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

Test Conditions

Parameter

Symbol

Unit

125_C

85_C

– 55 to

25_C

Test Conditions

Parameter

Symbol

ÎÎ

ООООООО

Maximum Low–Level Output Voltage, QA – Q

ООООООО

Vin = VIH or V

out

| v 20 µA

ÎÎ

2.0

4.5

6.0

ÎÎ

0.1

ÎÎ

0.1

ÎÎ

0.1

ÎÎÎОООООООÎООООООО

Vin = VIH or VIL|I

out

| v 2.4 mA

out

| v 6.0 mA

out

| v 7.8 mA

ÎÎ

3.0

4.5

6.0

ÎÎ

0.26

ÎÎ

0.33

ÎÎ

0.4

ÎÎ

ООООООО

Minimum High–Level Output Voltage, SQ

ООООООО

Vin = VIH or V

out

I v 20 µA

ÎÎ

2.0

4.5

6.0

ÎÎ

1.9

4.4

5.9

ÎÎ

1.9

4.4

5.9

ÎÎ

1.9

4.4

5.9

ÎÎ

ООООООО

Vin = VIH or VIL|I

out

| v 2.4 mA

outI v

4.0 mA

out

Iv 5.2 mA

ÎÎ

3.0

4.5

6.0

ÎÎ

2.98

3.98

5.48

ÎÎ

2.34

3.84

5.34

ÎÎ

2.2

3.7

5.2

ÎÎ

ООООООО

Maximum Low–Level Output Voltage, SQ

ООООООО

Vin = VIH or V

out

I v 20 µA

ÎÎ

2.0

4.5

6.0

ÎÎ

0.1

ÎÎ

0.1

ÎÎ

0.1

ÎÎÎОООООООÎООООООО

Vin = VIH or VIL|I

out

| v 2.4 mA

outI v

4.0 mA

out

Iv 5.2 mA

ÎÎ

3.0

4.5

6.0

ÎÎ

0.26

ÎÎ

0.33

ÎÎ

0.4

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

µA

ÎÎ

ООООООО

Maximum Three–State Leakage Current, QA – Q

ООООООО

Output in High–Impedance State Vin = VIL or V

out

= VCC or GND

ÎÎ

6.0

ÎÎ

± 0.5

ÎÎ

± 5.0

ÎÎ

± 10

µA

ÎÎ

ООООООО

Maximum Quiescent Supply Current (per Package)

ООООООО

Vin = VCC or GND l

out

= 0 µA

ÎÎ

6.0

ÎÎ

4.0

ÎÎ

160

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

= 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

ÎÎ

Symbol

ООООООООООООООО

Parameter

ÎÎ

– 55 to

25_C

ÎÎ

85_C

ÎÎ

125_C

Unit

ÎÎ

max

ООООООООООООООО

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 7)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

6.0 15 30 35

ÎÎ

4.8 10 24 28

ÎÎ

4.0

8.0 20 24

MHz

ÎÎ

PLH

PHL

ООООООООООООООО

Maximum Propagation Delay, Shift Clock to SQ

(Figures 1 and 7)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

140 100

28 24

ÎÎ

175 125

35 30

ÎÎ

210 150

42 36

ÎÎ

PHL

ООООООООООООООО

Maximum Propagation Delay, Reset to SQ

(Figures 2 and 7)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

145 100

29 25

ÎÎ

180 125

36 31

ÎÎ

220 150

44 38

ÎÎ

PLH

PHL

ООООООООООООООО

Maximum Propagation Delay, Latch Clock to QA – Q

(Figures 3 and 7)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

140 100

28 24

ÎÎ

175 125

35 30

ÎÎ

210 150

42 36

ÎÎ

PLZ

PHZ

ООООООООООООООО

Maximum Propagation Delay, Output Enable to QA – Q

(Figures 4 and 8)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

150 100

30 26

ÎÎ

190 125

38 33

ÎÎ

225 150

45 38

ÎÎ

PZL

PZH

ООООООООООООООО

Maximum Propagation Delay, Output Enable to QA – Q

(Figures 4 and 8)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

135

90 27 23

ÎÎ

170 110

34 29

ÎÎ

205 130

41 35

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