Motorola MC74HC574AN, MC74HC574ADW Datasheet
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC54/74HC574A is identical in pinout to the LS574. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising edge
of the Clock. The Output Enable input does not affect the states of the
flip–flops, but when Output Enable is high, all device outputs are forced to
the high–impedance state. Thus, data may be stored even when the outputs
are not enabled.
The HC574A is identical in function to the HCT374A but has the flip–flop
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
The HC574A is the noninverting version of the HC564.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 266 FETs or 66.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0
2 19
Q0
D1
D2
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
3
4
5
6
7
8
9
11
1
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NON–
INVERTING
OUTPUTS
PIN 20 = V
CC
PIN 10 = GND
Design Criteria
Value
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Units
Internal Gate Count*
66.5
ÎÎÎ
ÎÎÎ
ÎÎÎ
ea
Internal Gate Propagation Delay
1.5
ÎÎÎ
ÎÎÎ
ÎÎÎ
ns
Internal Gate Power Dissipation
5.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
µW
Speed Power Product
0.0075
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
pJ
*Equivalent to a two–input NAND gate.
PIN ASSIGNMENT
D4
D2
D1
D0
OUTPUT
ENABLE
GND
D7
D6
D5
D3 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
V
CC
CLOCK
Q7
Q6
Q5
Q4
FUNCTION TABLE
Inputs Output
OE Clock D Q
L H H
L L L
L L,H, X No Change
H X X Z
X = Don’t Care
Z = High Impedance
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Ceramic
Plastic
SOIC
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
1
20
MC54/74HC574A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 35
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
P
D
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: –10 mW/_C from 65_ to 125_C
Ceramic DIP: –10 mW/_C from 100_ to 125_C
SOIC Package: –7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_C
v
125_C
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
Vin = VIH or V
IL
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or V
IL
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
V
OH
V
OL
Minimum High–Level Output
Voltage
Maximum Low–Level Output
Voltage
V
V
Loading...