MOTOROLA MC74HC574AFEL, MC74HC574AFL1, MC74HC574AFR1, MC74HC574AH, MC74HC574AF Datasheet

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 8

1 Publication Order Number:

MC74HC574A/D

MC74HC574A

Octal 3-State Noninverting D Flip-Flop

High–Performance Silicon–Gate CMOS

The MC74HC574A is identical in pinout to the LS574. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip–flops, but when Output Enable is high, all device outputs are forced to the high–impedance state. Thus, data may be stored even when the outputs are not enabled.

The HC574A is identical in function to the HC374A but has the flip–flop inputs on the opposite side of the package from the outputs to facilitate PC board layout.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 266 FETs or 66.5 Equivalent Gates

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MARKING

DIAGRAMS

1

20

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week

SOIC WIDE–20

DW SUFFIX CASE 751D

HC574A

AWLYYWW

PDIP–20 N SUFFIX CASE 738

1

20

MC74HC574AN

AWLYYWW

1

20

1

20

Device Package Shipping

ORDERING INFORMATION

MC74HC574AN PDIP–20 1440 / Box MC74HC574ADW SOIC–WIDE

38 / Rail

MC74HC574ADWR2 SOIC–WIDE 1000 / Reel

MC74HC574A

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2

LOGIC DIAGRAM

DATA

INPUTS

D0

219

Q0 D1 D2 D3 D4 D5 D6 D7

CLOCK

OUTPUT ENABLE

3 4 5 6 7 8 9

11

1

18 17 16 15 14 13 12

Q1

Q2

Q3

Q4

Q5

Q6

Q7

NON–

INVERTING

OUTPUTS

PIN 20 = V

CC

PIN 10 = GND

PIN ASSIGNMENT

D4

D2

D1

D0

OUTPUT

ENABLE

GND

D7

D6

D5

D3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q3

Q2

Q1

Q0

V

CC

CLOCK

Q7

Q6

Q5

Q4

FUNCTION TABLE

Inputs Output

OE Clock D Q

LHH LLL L L,H, X No Change HXXZ

X = Don’t Care Z = High Impedance

ОООООООО

Î

Design Criteria

ÎÎ

Î

Value

Î

Units

ОООООООО

Î

Internal Gate Count*

ÎÎ

Î

66.5

Î

ea

Internal Gate Propagation Delay

1.5

ns

Internal Gate Power Dissipation

5.0

µW

ОООООООО

Î

Speed Power Product

ÎÎ

Î

0.0075

Î

pJ

*Equivalent to a two–input NAND gate.

MC74HC574A

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3

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

P

D

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

750 500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

ÎÎÎ

Î

260

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: –10 mW/_C from 65_ to 125_C

SOIC Package: –7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

ÎÎ

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

_

C

ÎÎ

Î

tr, t

f

ООООООООООООО

Î

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

Î

0 0 0

ÎÎ

1000

500 400

Î

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООО

Î

Parameter

ООООООО

Î

Test Conditions

ÎÎ

Î

V

CC V

ÎÎ

Î

– 55 to

25_C

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Unit

ÎÎ

Î

ÎÎ

Î

V

IH

ООООООО

Î

ООООООО

Î

Minimum High–Level Input Voltage

ООООООО

Î

ООООООО

Î

V

out

= VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

Î

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

Î

V

ÎÎ

Î

ÎÎ

Î

V

IL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Input Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.8

Î

0.5

0.9

1.35

1.8

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.8

Î

V

ÎÎ

Î

V

OH

ООООООО

Î

Minimum High–Level Output Voltage

ООООООО

Î

Vin = V

IH

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

1.9

4.4

5.9

Î

1.9

4.4

5.9

ÎÎ

Î

1.9

4.4

5.9

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = V

IH

|I

out

| v 2.4 mA

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

2.48

3.98

5.48

Î

2.34

3.84

5.34

ÎÎ

Î

2.2

3.7

5.2

Î

ÎÎ

Î

ÎÎ

Î

V

OL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Output Voltage

ООООООО

Î

ООООООО

Î

Vin = V

IL

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

0.1

Î

0.1

ÎÎ

Î

ÎÎ

Î

0.1

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = V

IL

|I

out

| v 2.4 mA

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

0.26

Î

0.33

ÎÎ

Î

0.4

Î

ÎÎ

Î

I

in

ООООООО

Î

Maximum Input Leakage Current

ООООООО

Î

Vin = VCC or GND

ÎÎ

Î

6.0

ÎÎ

Î

± 0.1

Î

± 1.0

ÎÎ

Î

± 1.0

Î

µA

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.