MOTOROLA MC74HC573ADW, MC74HC573AF, MC74HC573AFEL, MC74HC573ADTEL, MC74HC573ADT Datasheet

 Semiconductor Components Industries, LLC, 2000

May, 2000 – Rev. 9

1 Publication Order Number:

MC74HC573A/D

MC74HC573A

Octal 3-State Noninverting Transpar ent Latch

High–Performance Silicon–Gate CMOS

The MC74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.

The HC573A is identical in function to the HC373A but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 218 FETs or 54.5 Equivalent Gates

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MARKING

DIAGRAMS

1

20

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week

SOIC WIDE–20

DW SUFFIX CASE 751D

HC573A

AWLYYWW

PDIP–20 N SUFFIX CASE 738

1

20

MC74HC573AN

AWLYYWW

TSSOP–20 DT SUFFIX

CASE 948E

1

20

1

20

1

20

Device Package Shipping

ORDERING INFORMATION

MC74HC573AN PDIP–20 1440 / Box MC74HC573ADW SOIC–WIDE

38 / Rail MC74HC573ADWR2 SOIC–WIDE 1000 / Reel MC74HC573ADT TSSOP–20 75 / Rail MC74HC573ADTR2 TSSOP–20

2500 / Reel

HC

573A

ALYW

1

20

MC74HC573A

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2

LOGIC DIAGRAM

DATA

INPUTS

D0 D1 D2 D3 D4 D5 D6 D7

LATCH ENABLE

OUTPUT ENABLE

11 1

9

8

7

6

5

4

3

219

18 17 16 15 14 13 12

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

PIN 20 = V

CC

PIN 10 = GND

NONINVERTING

OUTPUTS

PIN ASSIGNMENT

D4

D2

D1

D0

OUTPUT

ENABLE

GND

D7

D6

D5

D3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q3

Q2

Q1

Q0

V

CC

LATCH ENABLE

Q7

Q6

Q5

Q4

FUNCTION TABLE

Inputs Output

Output Latch Enable Enable D Q

LHHH LHLL L L X No Change HXXZ

X = Don’t Care Z = High Impedance

ОООООООО

Î

Design Criteria

ÎÎ

Î

Value

Î

Units

Internal Gate Count*

54.5

ea.

Internal Gate Propagation Delay

1.5

ns

Internal Gate Power Dissipation

5.0

µW

ОООООООО

Î

Speed Power Product

ÎÎ

Î

0.0075

Î

pJ

*Equivalent to a two–input NAND gate.

MC74HC573A

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3

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎ

Î

750 500 450

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, TSSOP or SOIC Package)

ÎÎÎ

Î

260

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: –10 mW/_C from 65_ to 125_C

SOIC Package: –7 mW/_C from 65_ to 125_C TSSOP Package: –6.1 mW/°C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

ÎÎ

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

_

C

ÎÎ

Î

tr, t

f

ООООООООООООО

Î

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

Î

0 0 0

ÎÎ

1000

500 400

Î

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC V

– 55 to

25_C

v

85_Cv 125_C

Unit

ÎÎ

Î

ÎÎ

Î

V

IH

ООООООО

Î

ООООООО

Î

Minimum High–Level Input Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

Î

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

Î

V

ÎÎ

Î

ÎÎ

V

IL

ООООООО

Î

ООООООО

Maximum Low–Level Input Voltage

ООООООО

Î

ООООООО

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

Î

ÎÎ

0.5

0.9

1.35

1.8

Î

0.5

0.9

1.35 1 8

ÎÎ

Î

ÎÎ

0.5

0.9

1.35

1.8

Î

V

ÎÎ

Î

ÎÎ

Î

V

OH

ООООООО

Î

ООООООО

Î

Minimum High–Level Output Voltage

ООООООО

Î

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.9

4.4

5.9

Î

1.9

4.4

5.9

ÎÎ

Î

ÎÎ

Î

1.9

4.4

5.9

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or VIL|I

out

| ≤ 2.4mA

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

Î

2.48

3.98

5.48

Î

2.34

3.84

5.34

ÎÎ

Î

2.2

3.7

5.2

Î

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.