Motorola MC74HC4514DW, MC74HC4514N Datasheet

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SEMICONDUCTOR TECHNICAL DATA

1

REV 6

 Motorola, Inc. 1995

10/95

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!  

High–Performance Silicon–Gate CMOS

The MC74HC4514 is identical in pinout to the MC14514B metal–gate
CMOS device. The device inputs are compatible with standard CMOS
outputs, with pullup resistors; they are compatible with LSTTL outputs.

This device consists of a 4–bit storage latch with a Latch Enable and Chip
Select input. When a low signal is applied to the Latch Enable input, the
Address is stored, and decoded. When the Chip Select input is high, all
sixteen outputs are forced to a low level.

The Chip Select input is provided to facilitate the chip–select, demultiplex­ing, and cascading functions.

The demultiplexing function is accomplished by using the Address inputs
to select the desired device output, and then by using the Chip Select as a
data input.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 268 FETs or 67 Equivalent Gates

LOGIC DIAGRAM

BINARY

ADDRESS

INPUTS

A0
A1
A2
A3

21

3

2

1LATCH

ENABLE

CHIP

SELECT

PIN 24 = V

CC

PIN 12 = GND

4–BIT

STORAGE

LATCH

4–TO–16

LINE

DECODER

11
9

10
8
7
6
5
4
18
17
20
19
14
13
16
15

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15

ACTIVE–HIGH
OUTPUTS



PIN ASSIGNMENT

Y5

Y7

A1

A0

LATCH

ENABLE

Y3

Y4

Y6 Y10

A2

A3

CHIP
SELECT

V

CC

Y15

Y14

Y9

5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

13

11
12

21

22

23

24

Y13

Y12

Y8

Y11

Y0

GND

Y2

Y1

N SUFFIX

PLASTIC PACKAGE

CASE 724–03

ORDERING INFORMATION

MC74HCXXXXN
MC74HCXXXXDW

Plastic
SOIC

1

24

DW SUFFIX

SOIC PACKAGE

CASE 751E–04

1

24

MC74HC4514

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

P

D

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

750
500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

0
0
0

1000

500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

v

85_C

v

125_C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

V

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin = VIH or VIL|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

Vin = VIH or VIL|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

0.26

0.26

0.33

0.33

0.40

0.40

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

8

80

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

V

OH

V

OL

Minimum High–Level Output
Voltage

Maximum Low–Level Output
Voltage

V

V

MC74HC4514

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_C

v

125_C

Unit

t

PLH

,

t

PHL

Maximum Propagation Delay, Chip Select to Output Y

(Figures 1 and 5)

2.0

4.5

6.0

175

35
30

220

44
37

265

53
45

ns

t

PLH

2.0

4.5

6.0

230

46
39

290

58
49

345

69
59

t

PHL

2.0

4.5

6.0

175

35
30

220

44
37

265

53
45

t

PLH

2.0

4.5

6.0

230

46
39

290

58
49

345

69
59

t

PHL

2.0

4.5

6.0

175

35
30

220

44
37

265

53
45

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

2.0

4.5

6.0

75
15
13

95
19
16

110

22
19

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

70

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input t

r

= tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_C

v

125_C

Unit

t

su

Minimum Setup Time, Input A to Latch Enable

(Figure 4)

2.0

4.5

6.0

100

20
17

125

25
21

150

30
26

ns

t

h

Minimum Hold Time, Latch Enable to Input A

(Figure 4)

2.0

4.5

6.0

5
5
5

5
5
5

5
5
5

ns

t

w

Minimum Pulse Width, Latch Enable

(Figure 3)

2.0

4.5

6.0

80
16
14

100

20
17

120

24
20

ns

tr, t

f

Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

1000

500
400

1000

500
400

1000

500
400

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Maximum Propagation Delay, Input A to Output Y

(Figures 2 and 5)

Maximum Propagation Delay, Latch Enable to Output Y

(Figures 3 and 5)

ns

ns

C

PD

Power Dissipation Capacitance (Per Package)*

pF