Motorola MC74HC4511D, MC74HC4511N Datasheet



SEMICONDUCTOR TECHNICAL DATA

1

REV 6

 Motorola, Inc. 1995

10/95

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 # "

High–Performance Silicon–Gate CMOS

The MC74HC4511 is identical in pinout t o the MC14511 metal–gate
CMOS d ecoder/driver. The device inputs are c ompatible with standard
CMOS outputs; with pullup resistors, they are compatible with LSTTL
outputs.

The HC4511 provides the functions of a 4–bit storage latch, a BCD–to–
seven–segment decoder, and a display driver. It can be used either directly
or indirectly with seven–segment light–emitting diode (LED), incandescent,
fluorescent, g as discharge, or liquid–crystal readouts. Lamp test (LT),
blanking (BI), and latch enable (LE) inputs are used to test the display , to turn
off or pulse modulate the brightness of the display , and to store a BCD code,
respectively.

• Latch Storage of BCD Inputs

• Blanking Input

• Lamp Test Input

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 264 FETs or 66 Equivalent Gates

LOGIC DIAGRAM

4–BIT

TRANSPARENT

LATCH

DECODER

AND

OUTPUT

CONTROL

7
1
2
6

13
12
11
10

9
15
14

D (MSB)

C

B

A (LSB) a

b

c
d
e
f
g

5
4
3

LT

BI

LE

PIN 16 = V

CC

PIN 8 = GND

BCD

INPUTS

CONTROL

INPUTS

SEVEN–
SEGMENT
DISPLAY–
DRIVER
OUTPUTS



PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

b

a

g

f

V

CC

e

d

c

BI

LT

C

B

GND

A

D

LE

a

b

c

d

e

f g

DISPLAY

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

1

16

1

16

ORDERING INFORMATION

MC74HCXXXXN
MC74HCXXXXD

Plastic
SOIC

MC74HC4511

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 70

mA

P

D

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

750
500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time VCC = 2.0 V

(Figure 3) VCC = 4.5 V

VCC = 6.0 V

0
0
0

1000

500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

V

V

OH

Minimum High–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin = VIH or VIL|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

V

OL

Maximum Low–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or VIL|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

0.26

0.26

0.33

0.33

0.40

0.40

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

8

80

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC4511

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

t

PLH

,

t

PHL

Maximum Propagation Delay, Input A, B, C, or D to Output

(Figures 1 and 6)

2.0

4.5

6.0

600
120
102

750
150
129

900
180
153

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Latch Enable to Output

(Figures 2 and 6)

2.0

4.5

6.0

600
120
102

750
150
129

900
180
153

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Blanking Input to Output

(Figures 3 and 6)

2.0

4.5

6.0

600
120
102

750
150
129

900
180
153

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Lamp Test to Output

(Figures 4 and 6)

2.0

4.5

6.0

600
120
102

750
150
129

900
180
153

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 3 and 6)

2.0

4.5

6.0

75
15
13

95
19
16

110

22
19

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Package)*

70

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input t

r

= tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

t

su

Minimum Setup Time, Input A, B, C, or D to Latch Enable

(Figure 5)

2.0

4.5

6.0

100

20
17

125

25
21

150

30
26

ns

t

h

Minimum Hold Time, Latch Enable to Input A, B, C, or D

(Figure 5)

2.0

4.5

6.0

0
0
0

0
0
0

0
0
0

ns

t

w

Minimum Pulse Width, Latch Enable

(Figure 2)

2.0

4.5

6.0

80
16
14

100

20
17

120

24
20

ns

tr, t

f

Maximum Input Rise and Fall Times

(Figure 3)

2.0

4.5

6.0

1000

500
400

1000

500
400

1000

500
400

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).