SEMICONDUCTOR TECHNICAL DATA
1
REV 7
Motorola, Inc. 1997
2/97
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High–Performance Silicon–Gate CMOS
The MC54/74HC244A is identical in pinout to the LS244. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed to be
used with 3–state memory address drivers, clock drivers, and other
bus–oriented systems. The device has noninverting outputs and two
active–low output enables.
The HC244A is similar in function to the HC240A and HC241A.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 136 FETs or 34 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
A1
A2
A3
A4
B1
B2
B3
B4
17
15
13
11
8
6
4
218
16
14
12
9
7
5
3
YB4
YB3
YB2
YB1
YA4
YA3
YA2
YA1
NONINVERTING
OUTPUTS
PIN 20 = V
CC
PIN 10 = GND
OUTPUT
ENABLES
ENABLE A
ENABLE B
1
19
PIN ASSIGNMENT
A3
A2
YB4
A1
ENABLE A
GND
YB1
A4
YB2
YB3 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
YA2
B4
YA1
ENABLE B
V
CC
B1
YA4
B2
YA3
B3
FUNCTION TABLE
Inputs Outputs
Enable A,
Enable B A, B YA, YB
LLL
LHH
HXZ
Z = high impedance
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
MC74HCXXXASD
MC74HCXXXADT
Ceramic
Plastic
SOIC
SSOP
TSSOP
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
SD SUFFIX
SSOP PACKAGE
CASE 940C–03
1
20
1
20
1
20
MC54/74HC244A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
SSOP or TSSOP Package†
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
(Ceramic DIP)
_
C
*Maximum Ratings are those values beyond which damage to the device may occur .
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
SSOP or TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Minimum High–Level Input
Voltage
V
out
= VCC – 0.1 V
|I
out
| v 20 µA
Maximum Low–Level Input
Voltage
V
out
= 0.1 V
|I
out
| v 20 µA
Minimum High–Level Output
Voltage
Vin = V
IH
|I
out
| v 20 µA
Vin = V
IH
|I
out
| v 2.4 mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC54/74HC244A
High–Speed CMOS Logic Data
DL129 — Rev 6
3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Maximum Low–Level Output
Voltage
Vin = V
IL
|I
out
| v 20 µA
Vin = V
IL
|I
out
| v 2.4 mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
Maximum Input Leakage Current
Maximum Three–State Leakage
Current
Output in High–Impedance State
Vin = VIL or V
IH
V
out
= VCC or GND
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0 µA
µA
NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Maximum Propagation Delay, A to YA or B to YB
(Figures 1 and 3)
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
Maximum Input Capacitance
Maximum Three–State Output Capacitance (Output in
High–Impedance State)
pF
NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Buffer)*
34
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).