Motorola MC68EC020FG16, MC68EC020FG25, MC68EC020RP16, MC68EC020RP25, MC68020RP16 Datasheet

...

Download

MC68020

MC68EC020

MICROPROCESSORS

USER’S MANUAL

First Edition

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

PREFACE

The

M68020 User’s Manual

MC68020 32-bit, second-generation, enhanced microprocessor and the MC68EC020 32bit, second-generation, enhanced embedded microprocessor.

Throughout this manual, “MC68020/EC020” is used when information applies to both the MC68020 and the MC68EC020. “MC68020” and “MC68EC020” are used when information applies only to the MC68020 or MC68EC020, respectively.

For detailed information on the MC68020 and MC68EC020 instruction set, refer to M68000PM/AD,

This manual consists of the following sections: Section 1 Introduction

Section 2 Processing States Section 3 Signal Description Section 4 On-Chip Cache Memory Section 5 Bus Operation Section 6 Exception Processing Section 7 Coprocessor Interface Description Section 8 Instruction Execution Timing Section 9 Applications Information Section 10 Electrical Characteristics Section 11 Ordering Information and Mechanical Data Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three- Wire

M68000 Family Programmer’s Reference Manual

Bus Arbitration Protocol

describes the capabilities, operation, and programming of the

NOTE

In this manual, signal to a particular state. In particular, refer to a signal that is active or true; indicate a signal that is inactive or false. These terms are used independently of the voltage level (high or low) that they represent.

assert

and

negate

are used to specify forcing a

assertion

negation

and

assert

negate

MOTOROLA M68020 USER’S MANUAL iii

9/29/95 SECTION 1: OVERVIEW UM Rev 1

Paragraph Page

Number Title Number

Section 1

Introduction

1.1 Features .................................................................................................. 1-2

1.2 Programming Model ................................................................................ 1-4

1.3 Data Types and Addressing Modes Overview ........................................ 1-8

1.4 Instruction Set Overview ......................................................................... 1-10

1.5 Virtual Memory and Virtual Machine Concepts....................................... 1-10

1.5.1 Virtual Memory .................................................................................... 1-10

1.5.2 Virtual Machine.................................................................................... 1-12

1.6 Pipelined Architecture ............................................................................. 1-12

1.7 Cache Memory........................................................................................ 1-13

Section 2

Processing States

2.1 Privilege Levels....................................................................................... 2-2

2.1.1 Supervisor Privilege Level ................................................................... 2-2

2.1.2 User Privilege Level............................................................................. 2-3

2.1.3 Changing Privilege Level..................................................................... 2-3

2.2 Address Space Types ............................................................................. 2-4

2.3 Exception Processing.............................................................................. 2-5

2.3.1 Exception Vectors................................................................................ 2-5

2.3.2 Exception Stack Frame ....................................................................... 2-6

Section 3

Signal Description

3.1 Signal Index ............................................................................................ 3-2

3.2 Function Code Signals (FC2–FC0)......................................................... 3-2

3.3 Address Bus (A31–A0, MC68020)(A23–A0, MC68EC020) .................... 3-2

3.4 Data Bus (D31–D0)................................................................................. 3-2

3.5 Transfer Size Signals (SIZ1, SIZ0) ......................................................... 3-2

3.6 Asynchronous Bus Control Signals......................................................... 3-4

3.7 Interrupt Control Signals.......................................................................... 3-5

3.8 Bus Arbitration Control Signals ............................................................... 3-6

3.9 Bus Exception Control Signals................................................................ 3-6

3.10 Emulator Support Signal ......................................................................... 3-7

3.11 Clock (CLK)............................................................................................. 3-7

MOTOROLA M68020 USER’S MANUAL vii

9/29/95 SECTION 1: OVERVIEW UM Rev.1.0

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

3.12 Power Supply Connections..................................................................... 3-7

3.13 Signal Summary...................................................................................... 3-8

Section 4

On-Chip Cache Memory

4.1 On-Chip Cache Organization and Operation .......................................... 4-1

4.2 Cache Reset ........................................................................................... 4-3

4.3 Cache Control ......................................................................................... 4-3

4.3.1 Cache Control Register (CACR) ......................................................... 4-3

4.3.2 Cache Address Register (CAAR) ........................................................ 4-4

Section 5

Bus Operation

5.1 Bus Transfer Signals............................................................................... 5-1

5.1.1 Bus Control Signals............................................................................. 5-2

5.1.2 Address Bus........................................................................................ 5-3

5.1.3 Address Strobe.................................................................................... 5-3

5.1.4 Data Bus................................ .............................................................. 5-3

5.1.5 Data Strobe ......................................................................................... 5-4

5.1.6 Data Buffer Enable .............................................................................. 5-4

5.1.7 Bus Cycle Termination Signals............................................................ 5-4

5.2 Data Transfer Mechanism....................................................................... 5-5

5.2.1 Dynamic Bus Sizing ............................................................................ 5-5

5.2.2 Misaligned Operands........................................................................... 5-14

5.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment ................ 5-20

5.2.4 Address, Size, and Data Bus Relationships........................................ 5-21

5.2.5 Cache Interactions .............................................................................. 5-22

5.2.6 Bus Operation ..................................................................................... 5-24

5.2.7 Synchronous Operation with

5.3 Data Transfer Cycles .............................................................................. 5-25

5.3.1 Read Cycle.......................................................................................... 5-26

5.3.2 Write Cycle .......................................................................................... 5-33

5.3.3 Read-Modify-Write Cycle..................................................................... 5-39

5.4 CPU Space Cycles ................................................................................. 5-44

5.4.1 Interrupt Acknowledge Bus Cycles...................................................... 5-45

5.4.1.1 Interrupt Acknowledge Cycle—Terminated Normally...................... 5-45

5.4.1.2 Autovector Interrupt Acknowledge Cycle......................................... 5-48

5.4.1.3 Spurious Interrupt Cycle .................................................................. 5-48

5.4.2 Breakpoint Acknowledge Cycle........................................................... 5-50

5.4.3 Coprocessor Communication Cycles .................................................. 5-53

5.5 Bus Exception Control Cycles................................................................. 5-53

5.5.1 Bus Errors ........................................................................................... 5-55

DSACK1/DSACK0............................... 5-24

viii M68020 USER’S MANUAL MOTOROLA

9/29/95 SECTION 1: OVERVIEW UM Rev 1

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

5.5.2 Retry Operation ................................................................................... 5-56

5.5.3 Halt Operation...................................................................................... 5-60

5.5.4 Double Bus Fault................................................................................. 5-60

5.6 Bus Synchronization................................................................................ 5-62

5.7 Bus Arbitration......................................................................................... 5-62

5.7.1 MC68020 Bus Arbitration .................................................................... 5-63

5.7.1.1 Bus Request (MC68020) ................................................................. 5-66

5.7.1.2 Bus Grant (MC68020)...................................................................... 5-66

5.7.1.3 Bus Grant Acknowledge (MC68020) ............................................... 5-66

5.7.1.4 Bus Arbitration Control (MC68020).................................................. 5-67

5.7.2 MC68EC020 Bus Arbitration ............................................................... 5-70

5.7.2.1 Bus Request (MC68EC020) ............................................................ 5-71

5.7.2.2 Bus Grant (MC68EC020)................................................................. 5-71

5.7.2.3 Bus Arbitration Control (MC68EC020)............................................. 5-73

5.8 Reset Operation ...................................................................................... 5-76

Section 6

Exception Processing

6.1 Exception Processing Sequence ............................................................ 6-1

6.1.1 Reset Exception................................................................................... 6-4

6.1.2 Bus Error Exception............................................................................. 6-4

6.1.3 Address Error Exception...................................................................... 6-6

6.1.4 Instruction Trap Exception................................................................... 6-6

6.1.5 Illegal Instruction and Unimplemented Instruction Exceptions ............ 6-7

6.1.6 Privilege Violation Exception ............................................................... 6-8

6.1.7 Trace Exception................................................................................... 6-9

6.1.8 Format Error Exception ....................................................................... 6-10

6.1.9 Interrupt Exceptions............................................................................. 6-11

6.1.10 Breakpoint Instruction Exception......................................................... 6-17

6.1.11 Multiple Exceptions.............................................................................. 6-17

6.1.12 Return from Exception......................................................................... 6-19

6.2 Bus Fault Recovery................................................................................. 6-21

6.2.1 Special Status Word (SSW)................................................................. 6-21

6.2.2 Using Software to Complete the Bus Cycles....................................... 6-23

6.2.3 Completing the Bus Cycles with RTE.................................................. 6-24

6.3 Coprocessor Considerations................................................................... 6-25

6.4 Exception Stack Frame Formats............................................................. 6-25

MOTOROLA M68020 USER’S MANUAL ix

9/29/95 SECTION 1: OVERVIEW UM Rev.1.0

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

Section 7

Coprocessor Interface Description

7.1 Introduction ............................................................................................. 7-1

7.1.1 Interface Features ............................................................................... 7-2

7.1.2 Concurrent Operation Support ............................................................ 7-2

7.1.3 Coprocessor Instruction Format.......................................................... 7-3

7.1.4 Coprocessor System Interface ............................................................ 7-4

7.1.4.1 Coprocessor Classification .............................................................. 7-4

7.1.4.2 Processor-Coprocessor Interface.................................................... 7-5

7.1.4.3 Coprocessor Interface Register Selection ....................................... 7-6

7.2 Coprocessor Instruction Types ............................................................... 7-7

7.2.1 Coprocessor General Instructions....................................................... 7-8

7.2.1.1 Format ............................................................................................. 7-8

7.2.1.2 Protocol............................................................................................ 7-9

7.2.2 Coprocessor Conditional Instructions.................................................. 7-10

7.2.2.1 Branch on Coprocessor Condition Instruction ................................. 7-12

7.2.2.1.1 Format .......................................................................................... 7-12

7.2.2.1.2 Protocol........................................................................................ 7-12

7.2.2.2 Set on Coprocessor Condition Instruction ....................................... 7-13

7.2.2.2.1 Format .......................................................................................... 7-13

7.2.2.2.2 Protocol........................................................................................ 7-14

7.2.2.3 Test Coprocessor Condition, Decrement, and Branch Instruction... 7-14

7.2.2.3.1 Format .......................................................................................... 7-14

7.2.2.3.2 Protocol........................................................................................ 7-15

7.2.2.4 Trap on Coprocessor Condition Instruction ..................................... 7-15

7.2.2.4.1 Format .......................................................................................... 7-15

7.2.2.4.2 Protocol........................................................................................ 7-16

7.2.3 Coprocessor Context Save and Restore Instructions ......................... 7-16

7.2.3.1 Coprocessor Internal State Frames................................................. 7-17

7.2.3.2 Coprocessor Format Words............................................................. 7-18

7.2.3.2.1 Empty/Reset Format Word........................................................... 7-18

7.2.3.2.2 Not-Ready Format Word .............................................................. 7-19

7.2.3.2.3 Invalid Format Word ..................................................................... 7-19

7.2.3.2.4 Valid Format Word ....................................................................... 7-20

7.2.3.3 Coprocessor Context Save Instruction ............................................ 7-20

7.2.3.3.1 Format .......................................................................................... 7-20

7.2.3.3.2 Protocol........................................................................................ 7-21

7.2.3.4 Coprocessor Context Restore Instruction........................................ 7-22

7.2.3.4.1 Format .......................................................................................... 7-22

7.2.3.4.2 Protocol........................................................................................ 7-23

7.3 Coprocessor Interface Register Set........................................................ 7-24

x M68020 USER’S MANUAL MOTOROLA

9/29/95 SECTION 1: OVERVIEW UM Rev 1

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

7.3.1 Response CIR ..................................................................................... 7-24

7.3.2 Control CIR.......................................................................................... 7-24

7.3.3 Save CIR ............................................................................................. 7-25

7.3.4 Restore CIR ......................................................................................... 7-25

7.3.5 Operation Word CIR ............................................................................ 7-25

7.3.6 Command CIR..................................................................................... 7-25

7.3.7 Condition CIR ...................................................................................... 7-26

7.3.8 Operand CIR ....................................................................................... 7-26

7.3.9 Register Select CIR ............................................................................. 7-27

7.3.10 Instruction Address CIR....................................................................... 7-27

7.3.11 Operand Address CIR ......................................................................... 7-27

7.4 Coprocessor Response Primitives .......................................................... 7-27

7.4.1 ScanPC ............................................................................................... 7-28

7.4.2 Coprocessor Response Primitive General Format.............................. 7-28

7.4.3 Busy Primitive ...................................................................................... 7-30

7.4.4 Null Primitive........................................................................................ 7-31

7.4.5 Supervisor Check Primitive ................................................................. 7-33

7.4.6 Transfer Operation Word Primitive ...................................................... 7-33

7.4.7 Transfer from Instruction Stream Primitive .......................................... 7-34

7.4.8 Evaluate and Transfer Effective Address Primitive ............................. 7-35

7.4.9 Evaluate Effective Address and Transfer Data Primitive..................... 7-35

7.4.10 Write to Previously Evaluated Effective Address Primitive.................. 7-37

7.4.11 Take Address and Transfer Data Primitive.......................................... 7-39

7.4.12 Transfer to/from Top of Stack Primitive ............................................... 7-40

7.4.13 Transfer Single Main Processor Register Primitive ............................. 7-40

7.4.14 Transfer Main Processor Control Register Primitive ........................... 7-41

7.4.15 Transfer Multiple Main Processor Registers Primitive......................... 7-42

7.4.16 Transfer Multiple Coprocessor Registers Primitive ............................. 7-42

7.4.17 Transfer Status Register and ScanPC Primitive.................................. 7-44

7.4.18 Take Preinstruction Exception Primitive .............................................. 7-45

7.4.19 Take Midinstruction Exception Primitive.............................................. 7-47

7.4.20 Take Postinstruction Exception Primitive ............................................ 7-48

7.5 Exceptions............................................................................................... 7-49

7.5.1 Coprocessor-Detected Exceptions...................................................... 7-49

7.5.1.1 Coprocessor-Detected Protocol Violations ...................................... 7-50

7.5.1.2 Coprocessor-Detected Illegal Command or Condition Words ......... 7-51

7.5.1.3 Coprocessor Data-Processing-Related Exceptions......................... 7-51

7.5.1.4 Coprocessor System-Related Exceptions ....................................... 7-51

7.5.1.5 Format Errors ................................................................................... 7-52

7.5.2 Main-Processor-Detected Exceptions ................................................. 7-52

7.5.2.1 Protocol Violations ........................................................................... 7-52

7.5.2.2 F-Line Emulator Exceptions............................................................. 7-54

MOTOROLA M68020 USER’S MANUAL xi

9/29/95 SECTION 1: OVERVIEW UM Rev.1.0

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

7.5.2.3 Privilege Violations........................................................................... 7-55

7.5.2.4 cpTRAPcc Instruction Traps ............................................................ 7-55

7.5.2.5 Trace Exceptions ............................................................................. 7-55

7.5.2.6 Interrupts.......................................................................................... 7-56

7.5.2.7 Format Errors................................................................................... 7-57

7.5.2.8 Address and Bus Errors................................................................... 7-57

7.5.3 Coprocessor Reset.............................................................................. 7-58

7.6 Coprocessor Summary ........................................................................... 7-58

Section 8

Instruction Execution Timing

8.1 Timing Estimation Factors ...................................................................... 8-1

8.1.1 Instruction Cache and Prefetch ........................................................... 8-1

8.1.2 Operand Misalignment ........................................................................ 8-2

8.1.3 Bus/Sequencer Concurrency............................................................... 8-2

8.1.4 Instruction Execution Overlap ............................................................. 8-3

8.1.5 Instruction Stream Timing Examples................................................... 8-4

8.2 Instruction Timing Tables........................................................................ 8-9

8.2.1 Fetch Effective Address ...................................................................... 8-13

8.2.2 Fetch Immediate Effective Address..................................................... 8-14

8.2.3 Calculate Effective Address ................................................................ 8-16

8.2.4 Calculate Immediate Effective Address............................................... 8-17

8.2.5 Jump Effective Address....................................................................... 8-19

8.2.6 MOVE Instruction ................................................................................ 8-20

8.2.7 Special-Purpose MOVE Instruction..................................................... 8-29

8.2.8 Arithmetic/Logical Instructions............................................................. 8-30

8.2.9 Immediate Arithmetic/Logical Instructions........................................... 8-31

8.2.10 Binary-Coded Decimal Operations...................................................... 8-32

8.2.11 Single-Operand Instructions................................................................ 8-33

8.2.12 Shift/Rotate Instructions ...................................................................... 8-34

8.2.13 Bit Manipulation Instructions ............................................................... 8-35

8.2.14 Bit Field Manipulation Instructions....................................................... 8-36

8.2.15 Conditional Branch Instructions........................................................... 8-37

8.2.16 Control Instructions.............................................................................. 8-38

8.2.17 Exception-Related Instructions............................................................ 8-39

8.2.18 Save and Restore Operations............................................................. 8-40

Section 9

Applications Information

9.1 Floating-Point Units................................................................................. 9-1

9.2 Byte Select Logic for the MC68020/EC020............................................. 9-5

9.3 Power and Ground Considerations......................................................... 9-9

xii M68020 USER’S MANUAL MOTOROLA

9/29/95 SECTION 1: OVERVIEW UM Rev 1

TABLE OF CONTENTS (Concluded)

Paragraph Page

Number Title Number

9.4 Clock Driver............................................................................................. 9-10

9.5 Memory Interface .................................................................................... 9-11

9.6 Access Time Calculations ....................................................................... 9-12

9.7 Module Support....................................................................................... 9-14

9.7.1 Module Descriptor................................................................................ 9-14

9.7.2 Module Stack Frame ........................................................................... 9-16

9.8 Access Levels ......................................................................................... 9-17

9.8.1 Module Call.......................................................................................... 9-18

9.8.2 Module Return ..................................................................................... 9-19

Section 10

Electrical Characteristics

10.1 Maximum Ratings ................................................................................. 10-1

10.2 Thermal Considerations ........................................................................ 10-1

10.2.1 MC68020 Thermal Characteristics and

DC Electrical Characteristics ........................................................... 10-2

10.2.2 MC68EC020 Thermal Characteristics and

DC Electrical Characteristics ........................................................... 10-4

10.3 AC Electrical Characteristics................................................................. 10-5

Section 11

Ordering Information and Mechanical Data

11.1 Standard Ordering Information.............................................................. 11-1

11.1.1 Standard MC68020 Ordering Information.......................................... 11-1

11.1.2 Standard MC68EC020 Ordering Information .................................... 11-1

11.2 Pin Assignments and Package Dimensions.......................................... 11-2

11.2.1 MC68020 RC and RP Suffix—Pin Assignment ................................. 11-2

11.2.2 MC68020 RC Suffix—Package Dimensions ..................................... 11-3

11.2.3 MC68020 RP Suffix—Package Dimensions...................................... 11-4

11.2.4 MC68020 FC and FE Suffix—Pin Assignment.................................. 11-5

11.2.5 MC68020 FC Suffix—Package Dimensions...................................... 11-6

11.2.6 MC68020 FE Suffix—Package Dimensions ...................................... 11-7

11.2.7 MC68EC020 RP Suffix—Pin Assignment.......................................... 11-8

11.2.8 MC68EC020 RP Suffix—Package Dimensions................................. 11-9

11.2.9 MC68EC020 FG Suffix—Pin Assignment.......................................... 11-10

11.2.10 MC68EC020 FG Suffix—Package Dimensions................................. 11-11

Appendix A

Interfacing an MC68EC020 to a DMA Device That

Supports a Three-Wire Bus Arbitration Protocol

MOTOROLA M68020 USER’S MANUAL xiii

9/29/95 SECTION 1: OVERVIEW UM Rev.1.0

LIST OF ILLUSTRATIONS

Figure Page

Number Title Number

1-1 MC68020/EC020 Block Diagram ..................................................................... 1-3

1-2 User Programming Model ................................................................................ 1-5

1-3 Supervisor Programming Model Supplement .................................................. 1-6

1-4 Status Register (SR)........................................................................................ 1-7

1-5 Instruction Pipe ................................................................................................ 1-13

2-1 General Exception Stack Frame...................................................................... 2-6

3-1 Functional Signal Groups................................................................................. 3-1

4-1 MC68020/EC020 On-Chip Cache Organization .............................................. 4-2

4-2 Cache Control Register.................................................................................... 4-3

4-3 Cache Address Register.................................................................................. 4-4

5-1 Relationship between External and Internal Signals........................................ 5-2

5-2 Input Sample Window ...................................................................................... 5-2

5-3 Internal Operand Representation..................................................................... 5-6

5-4 MC68020/EC020 Interface to Various Port Sizes............................................ 5-6

5-5 Long-Word Operand Write to Word Port Example........................................... 5-10

5-6 Long-Word Operand Write to Word Port Timing.............................................. 5-11

5-7 Word Operand Write to Byte Port Example ..................................................... 5-12

5-8 Word Operand Write to Byte Port Timing......................................................... 5-13

5-9 Misaligned Long-Word Operand Write to Word Port Example ........................ 5-14

5-10 Misaligned Long-Word Operand Write to Word Port Timing............................ 5-15

5-11 Misaligned Long-Word Operand Read from Word Port Example .................... 5-16

5-12 Misaligned Word Operand Write to Word Port Example.................................. 5-16

5-13 Misaligned Word Operand Write to Word Port Timing..................................... 5-17

5-14 Misaligned Word Operand Read from Word Bus Example.............................. 5-18

5-15 Misaligned Long-Word Operand Write to Long-Word Port Example ............... 5-18

5-16 Misaligned Long-Word Operand Write to Long-Word Port Timing .................. 5-19

5-17 Misaligned Long-Word Operand Read from Long-Word Port Example........... 5-20

5-18 Byte Enable Signal Generation for 16- and 32-Bit Ports.................................. 5-23

5-19 Long-Word Read Cycle Flowchart................................................................... 5-26

5-20 Byte Read Cycle Flowchart.............................................................................. 5-27

5-21 Byte and Word Read Cycles—32-Bit Port ....................................................... 5-28

5-22 Long-Word Read—8-Bit Port ........................................................................... 5-29

5-23 Long-Word Read—16- and 32-Bit Ports.......................................................... 5-30

xiv M68020 USER’S MANUAL MOTOROLA

9/29/95 SECTION 1: OVERVIEW UM Rev 1

LIST OF ILLUSTRATIONS (Continued)

Figure Page

Number Title Number

5-24 Write Cycle Flowchart ...................................................................................... 5-33

5-25 Read-Write-Read Cycles—32-Bit Port............................................................. 5-34

5-26 Byte and Word Write Cycles—32-Bit Port........................................................ 5-35

5-27 Long-Word Operand Write—8-Bit Port ............................................................ 5-36

5-28 Long-Word Operand Write—16-Bit Port........................................................... 5-37

5-29 Read-Modify-Write Cycle Flowchart................................................................. 5-40

5-30 Byte Read-Modify-Write Cycle—32-Bit Port (TAS Instruction) ........................ 5-41

5-31 MC68020/EC020 CPU Space Address Encoding............................................ 5-45

5-32 Interrupt Acknowledge Cycle Flowchart........................................................... 5-46

5-33 Interrupt Acknowledge Cycle Timing................................................................ 5-47

5-34 Autovector Operation Timing ........................................................................... 5-49

5-35 Breakpoint Acknowledge Cycle Flowchart ....................................................... 5-50

5-36 Breakpoint Acknowledge Cycle Timing............................................................ 5-51

5-37 Breakpoint Acknowledge Cycle Timing (Exception Signaled).......................... 5-52

5-38 Bus Error without 5-39 Late Bus Error with

5-40 Late Retry......................................................................................................... 5-59

5-41 Halt Operation Timing ...................................................................................... 5-61

5-42 MC68020 Bus Arbitration Flowchart for Single Request.................................. 5-64

5-43 MC68020 Bus Arbitration Operation Timing for Single Request...................... 5-65

5-44 MC68020 Bus Arbitration State Diagram......................................................... 5-67

5-45 MC68020 Bus Arbitration Operation Timing—Bus Inactive ............................. 5-69

5-46 MC68EC020 Bus Arbitration Flowchart for Single Request............................. 5-71

5-47 MC68EC020 Bus Arbitration Operation Timing for Single Request................. 5-72

5-48 MC68EC020 Bus Arbitration State Diagram .................................................... 5-73

5-49 MC68EC020 Bus Arbitration Operation Timing—Bus Inactive ........................ 5-75

5-50 Interface for Three-Wire to Two-Wire Bus Arbitration ...................................... 5-76

5-51 Initial Reset Operation Timing.......................................................................... 5-77

5-52 RESET Instruction Timing................................................................................ 5-78

DSACK1/DSACK0 ............................................................. 5-57

DSACK1/DSACK0 .......................................................... 5-58

6-1 Reset Operation Flowchart .............................................................................. 6-5

6-2 Interrupt Pending Procedure ............................................................................ 6-12

6-3 Interrupt Recognition Examples ....................................................................... 6-13

6-4 Assertion of

6-5 Interrupt Exception Processing Flowchart........................................................ 6-15

6-6 Breakpoint Instruction Flowchart...................................................................... 6-18

6-7 RTE Instruction for Throwaway Four-Word Frame .......................................... 6-20

6-8 Special Status Word Format ............................................................................ 6-22

7-1 F-Line Coprocessor Instruction Operation Word.............................................. 7-3

7-2 Asynchronous Non-DMA M68000 Coprocessor Interface Signal Usage......... 7-5

7-3 MC68020/EC020 CPU Space Address Encodings.......................................... 7-6

MOTOROLA M68020 USER’S MANUAL xv

IPEND (MC68020 Only)............................................................... 6-14

9/29/95 SECTION 1: OVERVIEW UM Rev.1.0

LIST OF ILLUSTRATIONS (Continued)

Figure Page

Number Title Number

7-4 Coprocessor Address Map in MC68020/EC020 CPU Space .......................... 7-7

7-5 Coprocessor Interface Register Set Map......................................................... 7-7

7-6 Coprocessor General Instruction Format (cpGEN).......................................... 7-8

7-7 Coprocessor Interface Protocol for General Category Instructions.................. 7-10

7-8 Coprocessor Interface Protocol for Conditional Category Instructions ............ 7-11

7-9 Branch on Coprocessor Condition Instruction Format (cpBcc.W) ................... 7-12

7-10 Branch on Coprocessor Condition Instruction Format (cpBcc.L)..................... 7-12

7-11 Set on Coprocessor Condition Instruction Format (cpScc).............................. 7-13

7-12 Test Coprocessor Condition, Decrement, and Branch

Instruction Format (cpDBcc)........................................................................... 7-14

7-13 Trap on Coprocessor Condition Instruction Format (cpTRAPcc)..................... 7-15

7-14 Coprocessor State Frame Format in Memory.................................................. 7-17

7-15 Coprocessor Context Save Instruction Format (cpSAVE) ............................... 7-20

7-16 Coprocessor Context Save Instruction Protocol .............................................. 7-21

7-17 Coprocessor Context Restore Instruction Format (cpRESTORE)................... 7-22

7-18 Coprocessor Context Restore Instruction Protocol.......................................... 7-23

7-19 Control CIR Format .......................................................................................... 7-25

7-20 Condition CIR Format ...................................................................................... 7-26

7-21 Operand Alignment for Operand CIR Accesses .............................................. 7-26

7-22 Coprocessor Response Primitive Format ........................................................ 7-28

7-23 Busy Primitive Format...................................................................................... 7-30

7-24 Null Primitive Format........................................................................................ 7-31

7-25 Supervisor Check Primitive Format.................................................................. 7-33

7-26 Transfer Operation Word Primitive Format ...................................................... 7-33

7-27 Transfer from Instruction Stream Primitive Format .......................................... 7-34

7-28 Evaluate and Transfer Effective Address Primitive Format.............................. 7-35

7-29 Evaluate Effective Address and Transfer Data Primitive Format..................... 7-35

7-30 Write to Previously Evaluated Effective Address Primitive Format.................. 7-37

7-31 Take Address and Transfer Data Primitive Format.......................................... 7-39

7-32 Transfer to/from Top of Stack Primitive Format ............................................... 7-40

7-33 Transfer Single Main Processor Register Primitive Format ............................. 7-40

7-34 Transfer Main Processor Control Register Primitive Format ........................... 7-41

7-35 Transfer Multiple Main Processor Registers Primitive Format......................... 7-42

7-36 Register Select Mask Format........................................................................... 7-42

7-37 Transfer Multiple Coprocessor Registers Primitive Format.............................. 7-43

7-38 Operand Format in Memory for Transfer to –(An) ........................................... 7-44

7-39 Transfer Status Register and ScanPC Primitive Format.................................. 7-44

7-40 Take Preinstruction Exception Primitive Format.............................................. 7-45

7-41 MC68020/EC020 Preinstruction Stack Frame................................................. 7-46

7-42 Take Midinstruction Exception Primitive Format.............................................. 7-47

7-43 MC68020/EC020 Midinstruction Stack Frame................................................. 7-47

7-44 Take Postinstruction Exception Primitive Format............................................. 7-48

xvi M68020 USER’S MANUAL MOTOROLA

9/29/95 SECTION 1: OVERVIEW UM Rev 1

LIST OF ILLUSTRATIONS (Concluded)

Figure Page

Number Title Number

7-45 MC68020/EC020 Postinstruction Stack Frame................................................ 7-48

8-1 Concurrent Instruction Execution..................................................................... 8-3

8-2 Instruction Execution for Instruction Timing Purposes ..................................... 8-3

8-3 Processor Activity for Example 1 ..................................................................... 8-5

8-4 Processor Activity for Example 2 ..................................................................... 8-6

8-5 Processor Activity for Example 3 ..................................................................... 8-7

8-6 Processor Activity for Example 4 ..................................................................... 8-8

9-1 32-Bit Data Bus Coprocessor Connection........................................................ 9-2

9-2 Chip Select Generation PAL ............................................................................ 9-3

9-3 Chip Select PAL Equations.............................................................................. 9-4

9-4 Bus Cycle Timing Diagram............................................................................... 9-4

9-5 Example MC68020/EC020 Byte Select PAL System Configuration ................ 9-7

9-6 MC68020/EC020 Byte Select PAL Equations.................................................. 9-8

9-7 High-Resolution Clock Controller ..................................................................... 9-11

9-8 Alternate Clock Solution................................................................................... 9-11

9-9 Access Time Computation Diagram................................................................. 9-12

9-10 Module Descriptor Format................................................................................ 9-15

9-11 Module Entry Word .......................................................................................... 9-15

9-12 Module Call Stack Frame................................................................................. 9-16

9-13 Access Level Control Bus Registers ................................................................ 9-17

10-1 Drive Levels and Test Points for AC Specifications ....................................... 10-6

10-2 Clock Input Timing Diagram ........................................................................... 10-7

10-3 Read Cycle Timing Diagram .......................................................................... 10-11

10-4 Write Cycle Timing Diagram........................................................................... 10-12

10-5 Bus Arbitration Timing Diagram ..................................................................... 10-13

A-1 Bus Arbitration Circuit—MC68EC020 (Two-Wire) to DMA (Three-Wire) ......... A-1

MOTOROLA M68020 USER’S MANUAL xvii

9/29/95 SECTION 1: OVERVIEW UM Rev.1.0

LIST OF TABLES

Table Page

Number Title Number

1-1 Addressing Modes ........................................................................................... 1-9

1-2 Instruction Set .................................................................................................. 1-11

2-1 Address Space Encodings............................................................................... 2-4

3-1 Signal Index ..................................................................................................... 3-3

3-2 Signal Summary............................................................................................... 3-8

5-1 DSACK1/DSACK0 Encodings and Results .................................................... 5-5

5-2 SIZ1, SIZ0 Signal Encoding............................................................................. 5-7

5-3 Address Offset Encodings ............................................................................... 5-7

5-4 Data Bus Requirements for Read Cycles ........................................................ 5-8

5-5 MC68020/EC020 Internal to External Data Bus Multiplexer—

Write Cycles ................................................................................................... 5-9

5-6 Memory Alignment and Port Size Influence on Read/Write Bus Cycles.......... 5-20

5-7 Data Bus Byte Enable Signals for Byte, Word, and Long-Word Ports............. 5-22

5-8

6-1 Exception Vector Assignments ........................................................................ 6-3

6-2 Tracing Control ................................................................................................ 6-9

6-3 Interrupt Levels and Mask Values.................................................................... 6-12

6-4 Exception Priority Groups ................................................................................ 6-18

6-5 Exception Stack Frames.................................................................................. 6-26

7-1 cpTRAPcc Opmode Encodings........................................................................ 7-16

7-2 Coprocessor Format Word Encodings............................................................. 7-18

7-3 Null Coprocessor Response Primitive Encodings............................................ 7-32

7-4 Valid Effective Address Field Codes................................................................ 7-36

7-5 Main Processor Control Register Select Codes............................................... 7-41

7-6 Exceptions Related to Primitive Processing .................................................... 7-53

DSACK1/DSACK0, BERR, HALT Assertion Results..................................... 5-54

8-1 Examples 1–4 Instruction Stream Execution Comparison............................... 8-8

8-2 Instruction Timings from Timing Tables ........................................................... 8-11

8-3 Observed Instruction Timings .......................................................................... 8-11

xviii M68020 USER’S MANUAL MOTOROLA

9/29/95 SECTION 1: OVERVIEW UM Rev 1

LIST OF TABLES (Continued)

Table Page

Number Title Number

9-1 Data Bus Activity for Byte, Word, and Long-Word Ports.................................. 9-6

9-2 V 9-3 V

9-4 Memory Access Time Equations at 16.67 and 25 MHz ................................... 9-13

9-5 Calculated t

9-6 Access Status Register Codes......................................................................... 9-18

and GND Pin Assignments—MC68EC020 PPGA (RP Suffix) ................. 9-10

and GND Pin Assignments—MC68EC020 PQFP (FG Sufffix)................. 9-10

Values for Operation at Frequencies

AVDV

Less Than or Equal to the CPU Maximum Frequency Rating........................ 9-14

10-1 θ

vs. Airflow—MC68020 CQFP Package ................................................... 10-3

10-2 Power vs. Rated Frequency (at T 10-3 Temperature Rise of Board vs. P 10-4 θ

vs. Airflow—MC68EC020 PQFP Package .............................................. 10-4

Maximum = 110°C) ................................. 10-3

—MC68020 CQFP Package ................... 10-3

MOTOROLA M68020 USER’S MANUAL xix

MC68020/EC020 ACRONYM LIST

BCD — Binary-Coded Decimal

CAAR — Cache Address Register

CACR — Cache Control Register

CCR — Condition Code Register

CIR — Coprocessor Interface Register

CMO S — Complementary Metal Oxide Semiconductor

CPU — Central Processing Unit

CQFP — Ceramic Quad Flat Pack

DDMA — Dual-Channel Direct Memory Access

DFC — Destination Function Code Register

DMA — Direct Memory Access

DRAM — Dynamic Random Access Memory

FPCP — Floating-Point Coprocessor

HCMOS — High-Density Complementary Metal Oxide Semiconductor

IEEE — Institute of Electrical and Electronic Engineers

ISP — Interrupt Stack Pointer

LMB — Lower Middle Byte

LRAR — Limited Rate Auto Request

LS B — Least Significant Byte

MMU — Memory Management Unit

MPU — Microprocessor Unit MS B — Most Significant Byte MS P — Master Stack Pointer

NMO S — n-Type Metal Oxide Semiconductor

PAL — Programmable Array Logic

PC — Program Counter

PGA — Pin Grid Array

PMMU — Paged Memory Management Unit

PPGA — Plastic Pin Grid Array

PQFP — Plastic Quad Flat Pack

RAM — Random Access Memory

SF C — Source Function Code Register

S P — Stack Pointer SR — Status Register

S S P — Supervisor Stack Pointer

S SW — Special Status Word

UMB — Upper Middle Byte

US P — User Stack Pointer

VBR — Vector Base Register

VLS I — Very Large Scale Integration

MOTOROLA M68020 USER’S MANUAL v

SECTION 1 INTRODUCTION

The MC68020 is the first full 32-bit implementation of the M68000 family of microprocessors from Motorola. Using VLSI technology, the MC68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes.

The MC68020 is object-code compatible with earlier members of the M68000 family and has the added features of new addressing modes in support of high-level languages, an on-chip instruction cache, and a flexible coprocessor interface with full IEEE floating-point support (the MC68881 and MC68882). The internal operations of this microprocessor operate in parallel, allowing multiple instructions to be executed concurrently.

The asynchronous bus structure of the MC68020 uses a nonmultiplexed bus with 32 bits of address and 32 bits of data. The processor supports a dynamic bus sizing mechanism that allows the processor to transfer operands to or from external devices while automatically determining device port size on a cycle-by-cycle basis. The dynamic bus interface allows access to devices of differing data bus widths, in addition to eliminating all data alignment restrictions.

The MC68EC020 is an economical high-performance embedded microprocessor based on the MC68020 and has been designed specifically to suit the needs of the embedded microprocessor market. The major differences in the MC68EC020 and the MC68020 are that the MC68EC020 has a 24-bit address bus and does not implement the following signals: frequencies differ for the MC68020 and MC68EC020 (see Section 11 Ordering Information and Mechanical Data .) Unless otherwise stated, information in this manual applies to both the MC68020 and the MC68EC020.

ECS, OCS, DBEN, IPEND, and BGACK. Also, the available packages and

MOTOROLA M68020 USER’S MANUAL 1-1

1.1 FEATURES

The main features of the MC68020/EC020 are as follows:

• Object-Code Compatible with Earlier M68000 Microprocessors

• Addressing Mode Extensions for Enhanced Support of High-Level Languages

• New Bit Field Data Type Accelerates Bit-Oriented Applications—e.g., Video Graphics

• An On-Chip Instruction Cache for Faster Instruction Execution

• Coprocessor Interface to Companion 32-Bit Peripherals—the MC68881 and MC68882 Floating-Point Coprocessors and the MC68851 Paged Memory Management Unit

• Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple Instructions To Be Executed Concurrently

• High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32 Bits

• Dynamic Bus Sizing Efficiently Supports 8-/16-/32-Bit Memories and Peripherals

• Full Support of Virtual Memory and Virtual Machine

• Sixteen 32-Bit General-Purpose Data and Address Registers

• Two 32-Bit Supervisor Stack Pointers and Five Special-Purpose Control Registers

• Eighteen Addressing Modes and Seven Data Types

• 4-Gbyte Direct Addressing Range for the MC68020

• 16-Mbyte Direct Addressing Range for the MC68EC020

• Selection of Processor Speeds for the MC68020: 16.67, 20, 25, and 33.33 MHz

• Selection of Processor Speeds for the MCEC68020: 16.67 and 25 MHz

A block diagram of the MC68020/EC020 is shown in Figure 1-1.

1-2 M68020 USER’S MANUAL MOTOROLA

SEQUENCER AND CONTROL

CONTROL

STORE

CONTROL

INSTRUCTION

STAGE

CACHE

INTERNAL D BUSINSTRUCTION PIPE

INSTRUCTION

ADDRESS

PROGRAM

DATA

EXECUTION UNIT

MISALIGNMENT

SIZE

WRITE PENDING

PREFETCH PENDING

MICROBUS

BUS CONTROLLER

BUS CONTROL

ADDRESS

DATA

DATA 3

ADDRESS 3

LOGIC

HOLDING

EGISTE (CAHR)

ATA

2-BI

BUS

PADS

BUFFER

CONTROL LOGIC

ADDRES

BUFFER

COUNTE

SECTION

CACHE

ECTIO

MULTIPLEXER

2-BI

BUS

PADS

ULTIPLEXE

MOTOROLA M68020 USER’S MANUAL 1-3

SIGNALS

24-Bit for MC68EC020

Figure 1-1. MC68020/EC020 Block Diagram

1.2 PROGRAMMING MODEL

The programming model of the MC68020/EC020 consists of two groups of registers, the user model and the supervisor model, that correspond to the user and supervisor privilege levels, respectively. User programs executing at the user privilege level use the registers of the user model. System software executing at the supervisor level uses the control registers of the supervisor level to perform supervisor functions.

As shown in the programming models (see Figures 1-2 and 1-3), the MC68020/EC020 has 16 32-bit general-purpose registers, a 32-bit PC two 32-bit SSPs, a 16-bit SR, a 32-bit VBR, two 3-bit alternate function code registers, and two 32-bit cache handling (address and control) registers.

The user programming model remains unchanged from earlier M68000 family microprocessors. The supervisor programming model supplements the user programming model and is used exclusively by MC68020/EC020 system programmers who utilize the supervisor privilege level to implement sensitive operating system functions. The supervisor programming model contains all the controls to access and enable the special features of the MC68020/EC020. All application software, written to run at the nonprivileged user level, migrates to the MC68020/EC020 from any M68000 platform without modification.

Registers D7–D0 are data registers used for bit and bit field (1 to 32 bits), byte (8 bit), word (16 bit), long-word (32 bit), and quad-word (64 bit) operations. Registers A6–A0 and the USP, ISP, and MSP are address registers that may be used as software stack pointers or base address registers. Register A7 (shown as A7 in Figure 1-2 and as A7 ′ and A7 ″ in Figure 1-3) is a register designation that applies to the USP in the user privilege level and to either the ISP or MSP in the supervisor privilege level. In the supervisor privilege level, the active stack pointer (interrupt or master) is called the SSP. In addition, the address registers may be used for word and long-word operations. All of the 16 general-purpose registers (D7–D0, A7–A0) may be used as index registers.

The PC contains the address of the next instruction to be executed by the MC68020/EC020. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC, as appropriate.

1-4 M68020 USER’S MANUAL MOTOROLA

78151631D0D1D2D3D4D5D6D7

D R

151631A0A1A2A3A4A5

A R

151631

)

CCR

8031

P C

U P

ATA EGISTER

DDRESS EGISTER

7 (USP

SER STACK OINTER

ROGRAM OUNTER

ONDITION COD EGISTER

Figure 1-2. User Programming Model

MOTOROLA M68020 USER’S MANUAL 1-5

78151631SRVBR031

CACR

CAAR031

C R

151615

(

)0233131SFC

)

I P

M P

S R

V R

DFC

A F R

7' (ISP

7'' (MSP

CCR

Figure 1-3. Supervisor Programming Model Supplement

NTERRUPT STACK

OINTER

ASTER STACK

OINTER

TATUS EGISTER

ECTOR BASE EGISTER

LTERNATE

UNCTION CODE

EGISTERS

ACHE CONTRO EGISTER

ACHE ADDRESS EGISTER

1-6 M68020 USER’S MANUAL MOTOROLA

The SR (see Figure 1-4) stores the processor status. It contains the condition codes that

(

)

ZERO

reflect the results of a previous operation and can be used for conditional instruction execution in a program. The condition codes are extend (X), negative (N), zero (Z), overflow (V), and carry (C). The user byte, which contains the condition codes, is the only portion of the SR information available in the user privilege level, and it is referenced as the CCR in user programs. In the supervisor privilege level, software can access the entire SR, including the interrupt priority mask (three bits) and control bits that indicate whether the processor is in:

1. One of two trace modes (T1, T0)

2. Supervisor or user privilege level (S)

3. Master or interrupt mode (M)

USER BYTE

TRACE

NABL

T0T1

SYSTEM BYTE

INTERRUPT

PRIORITY MASK

CONDITION CODE REGISTER

015

ARR

VERFLOW

SUPERVISOR/USER LEVE

MASTER/INTERRUPT MOD

EGATIV

XTEN

Figure 1-4. Status Register (SR)

The VBR contains the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table.

The alternate function code registers, SFC and DFC, contain 3-bit function codes. For the MC68020, function codes can be considered extensions of the 32-bit linear address that optionally provide as many as eight 4-Gbyte address spaces; for the MC68EC020, function codes can be considered extensions of the 24-bit linear address that optionally provide as many as eight 16-Mbyte address spaces. Function codes are automatically generated by the processor to select address spaces for data and program at the user and supervisor privilege levels and to select a CPU address space for processor functions (e.g., coprocessor communications). Registers SFC and DFC are used by certain instructions to explicitly specify the function codes for operations.

The CACR controls the on-chip instruction cache of the MC68020/EC020. The CAAR stores an address for cache control functions.

MOTOROLA M68020 USER’S MANUAL 1-7

1.3 DATA TYPES AND ADDRESSING MODES OVERVIEW

For detailed information on the data types and addressing modes supported by the MC68020/EC020, refer to M68000PM/AD,

Manual

The MC68020/EC020 supports seven basic data types:

In addition, the MC68020/EC020 instruction set supports operations on other data types such as memory addresses. The coprocessor mechanism allows direct support of floatingpoint operations with the MC68881 and MC68882 floating-point coprocessors as well as specialized user-defined data types and functions.

1. Bits

2. Bit Fields (Fields of consecutive bits, 1–32 bits long)

3. BCD Digits (Packed: 2 digits/byte, Unpacked: 1 digit/byte)

4. Byte Integers (8 bits)

5. Word Integers (16 bits)

6. Long-Word Integers (32 bits)

7. Quad-Word Integers (64 bits)

M68000 Family Programmer’s Reference

The 18 addressing modes listed in Table 1-1 include nine basic types:

1. Register Direct

2. Register Indirect

3. Register Indirect with Index

4. Memory Indirect

5. PC Indirect with Displacement

6. PC Indirect with Index

7. PC Memory Indirect

8. Absolute

9. Immediate

The register indirect addressing modes have postincrement, predecrement, displacement, and index capabilities. The PC modes have index and offset capabilities. Both modes are extended to provide indirect reference through memory. In addition to these addressing modes, many instructions implicitly specify the use of the CCR, stack pointer, and/or PC.

1-8 M68020 USER’S MANUAL MOTOROLA

Table 1-1. Addressing Modes

Addressing Modes Syntax

Data Address

Address Address with Postincrement Address with Predecrement Address with Displacement

Address Register Indirect with Index

8-Bit Displacement Base Displacement

Memory Indirect

Postindexed

Preindexed PC Indirect with Displacement (d16, PC) PC Indirect with Index

8-Bit Displacement

Base Displacement PC Indirect

Postindexed

Preindexed Absolute Data Addressing

Short

Long Immediate #<data>

NOTE:

Dn = Data Register, D7–D0

An = Address Register, A7–A0

, d16= A twos complement or sign-extended displacement added as part

Xn = Address or data register used as an index register; form is

bd = A twos-complement base displacement; when present, size can be

od = Outer displacement added as part of effective address calculation

PC = Program Counter

<data> = Immediate value of 8, 16, or 32 bits

( ) = Effective Address [ ] = Use as indirect access to long-word address.

of the effective address calculation; size is 8 (d when omitted, assemblers use a value of zero.

Xn.SIZE size) and SCALE is 1, 2, 4, or 8 (index register is multiplied by SCALE); use of SIZE and/or SCALE is optional.

16 or 32 bits.

after any memory indirection; use is optional with a size of 16 or 32 bits.

SCALE, where SIZE is .W or .L (indicates index register

) or 16 (d16) bits;

(An) (An)+ –(An)

, An)

, An, Xn)

(bd, An, Xn)

([bd, An], Xn, od) ([bd, An, Xn], od)

, PC, Xn)

(bd, PC, Xn)

([bd, PC], Xn, od) ([bd, PC, Xn], od)

(xxx).W

(xxx).L

MOTOROLA M68020 USER’S MANUAL 1-9

1.4 INSTRUCTION SET OVERVIEW

For detailed information on the MC68020/EC020 instruction set, refer to M68000PM/AD,

M68000 Family Programmer’s Reference Manual

The instructions in the MC68020/EC020 instruction set are listed in Table 1-2. The instruction set has been tailored to support structured high-level languages and sophisticated operating systems. Many instructions operate on bytes, words, or long words, and most instructions can use any of the 18 addressing modes.

1.5 VIRTUAL MEMORY AND VIRTUAL MACHINE CONCEPTS

The full addressing range of the MC68020 is 4 Gbytes (4,294,967,296 bytes) in each of eight address spaces; the full addressing range of the MC68EC020 is 16 Mbytes (16,777,216 bytes) in each of the eight address spaces. Even though most systems implement a smaller physical memory, the system can be made to appear to have a full 4 Gbytes (MC68020) or 16 Mbytes (MC68EC020) of memory available to each user program by using virtual memory techniques.

In a virtual memory system, a user program can be written as if it has a large amount of memory available, although the physical memory actually present is much smaller. Similarly, a system can be designed to allow user programs to access devices that are not physically present in the system, such as tape drives, disk drives, printers, terminals, and so forth. With proper software emulation, a physical system can appear to be any other M68000 computer system to a user program, and the program can be given full access to all of the resources of that emulated system. Such an emulated system is called a virtual machine.

1.5.1 Virtual Memory

A system that supports virtual memory has a limited amount of high-speed physical memory that can be accessed directly by the processor and maintains an image of a much larger virtual memory on a secondary storage device such as a large-capacity disk drive. When the processor attempts to access a location in the virtual memory map that is not resident in physical memory, a page fault occurs. The access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory. The suspended access is then either restarted or continued.

The MC68020/EC020 uses instruction continuation to support virtual memory. When a bus cycle is terminated with a bus error, the microprocessor suspends the current instruction and executes the virtual memory bus error handler. When the bus error handler has completed execution, it returns control to the program that was executing when the error was detected, reruns the faulted bus cycle (when required), and continues the suspended instruction.

1-10 M68020 USER’S MANUAL MOTOROLA

Table 1-2. Instruction Set

Mnemonic Description Mnemonic Description

ABCD Add Decimal with Extend MOVE USP Move User Stack Pointer ADD Add MOVEC Move Control Register ADDA Add Address MOVEM Move Multiple Registers ADDI Add Immediate MOVEP Move Peripheral ADDQ Add Quick MOVEQ Move Quick ADDX Add with Extend MOVES Move Alternate Address Space AND Logical AND MULS Signed Multiply ANDI Logical AND Immediate MULU Unsigned Multiply

ASL, ASR Arithmetic Shift Left and Right NBCD Negate Decimal with Extend Bcc Branch Conditionally NEG Negate

BCHG Test Bit and Change NEGX Negate with Extend BCLR Test Bit and Clear NOP No Operation BFCHG Test Bit Field and Change NO T Logical Complement

BFCLR Test Bit Field and Clear OR Logical Inclusive OR BFEXTS Signed Bit Field Extract ORI Logical Inclusive OR Immediate BFEXTU Unsigned Bit Field Extract ORI CCR Logical Inclusive Or Immediate to Condition Codes BFFFO Bit Field Find First One ORI SR Logical Inclusive OR Immediate to Status Register

BFINS Bit Field Insert PACK Pack BCD BFSET Test Bit Field and Set PEA Push Effective Address

BFTST Test Bit Field RESET Reset External Devices BKPT Breakpoint ROL, ROR Rotate Left and Right BRA Branch Always ROXL,ROXR Rotate with Extend Left and Right BSET Test Bit and Set RTD Return and Deallocate BSR Branch to Subroutine RTE Return from Exception BTST Test Bit RTM Return from Module

CALLM Call Module RTR Return and Restore Codes CAS Compare and Swap Operands RTS Return from Subroutine

CAS2 Compare and Swap Dual Operands SBCD Subtract Decimal with Extend CHK Check Register Against Bound Scc Set Conditionally CHK2 Check Register Against Upper and Lower Bound STOP Stop CLR Clear SUB Subtract CMP Compare SUBA Subtract Address CMPA Compare Address SUBI Subtract Immediate CMPI Compare Immediate SUBQ Subtract Quick CMPM Compare Memory to Memory SUBX Subtract with Extend CMP2 Compare Register Against Upper and Lower Bounds SWAP Swap Register Words

DBcc Test Condition, Decrement and Branch TAS Test and Set an Operand DIVS, DIVSL Signed Divide TRAP Trap DIVU, DIVUL Unsigned Divide TRAPcc Trap Conditionally

EOR Logical Exclusive OR TRAPV Trap on Overflow EORI Logical Exclusive Or Immediate TST Test Operand

EXG Exchange Registers UNLK Unlink EXT, EXTB Sign Extend UNPK Unpack BCD

ILLEGAL Take Illegal Instruction Trap JMP Jump COPROCESSOR INSTRUCTIONS JSR Jump to Subroutine Mnemonic Description LEA Load Effective Address cpBcc Branch Conditionally

LINK Link and Allocate cpDBcc Test Coprocessor Condition, Decrement and Branch LSL, LSR Logical Shift Left and Right cpGEN Coprocessor General Instruction

MOVE Move cpRESTORE Restore Internal State of Coprocessor MOVEA Move Address cpSAVE Save Internal State of Coprocessor MOVE CCR Move Condition Code Register cpScc Set Conditionally MOVE SR Move Status Register cpTRAPcc Trap Conditionally

MOTOROLA M68020 USER’S MANUAL 1-11

1.5.2 Virtual Machine

A typical use for a virtual machine system is the development of software, such as an operating system, for a new machine also under development and not yet available for programming use. In a virtual machine system, a governing operating system emulates the hardware of the new machine and allows the new software to be executed and debugged as though it were running on the new hardware. Since the new software is controlled by the governing operating system, it is executed at a lower privilege level than the governing operating system. Thus, any attempts by the new software to use virtual resources that are not physically present (and should be emulated) are trapped to the governing operating system and performed by its software.

In the MC68020/EC020 implementation of a virtual machine, the virtual application runs at the user privilege level. The governing operating system executes at the supervisor privilege level and any attempt by the new operating system to access supervisor resources or execute privileged instructions causes a trap to the governing operating system.

Instruction continuation is used to support virtual I/O devices in memory-mapped input/output systems. Control and data registers for the virtual device are simulated in the memory map. An access to a virtual register causes a fault, and the function of the register is emulated by software.

1.6 PIPELINED ARCHITECTURE

The MC68020/EC020 contains a three-word instruction pipe where instruction opcodes are decoded. As shown in Figure 1-5, instruction words (instruction operation words and all extension words) enter the pipe at stage B and proceed to stages C and D. An instruction word is completely decoded when it reaches stage D of the pipe. Each stage has a status bit that reflects whether the word in the stage was loaded with data from a bus cycle that was terminated abnormally. Stages of the pipe are only filled in response to specific prefetch requests issued by the sequencer.

Words are loaded into the instruction pipe from the cache holding register. Although the individual stages of the pipe are only 16 bits wide, the cache holding register is 32 bits wide and contains the entire long word. This long word is obtained from the instruction cache or the external bus in response to a prefetch request from the sequencer. When the sequencer requests an even-word (long-word-aligned) prefetch, the entire long word is accessed from the instruction cache or the external bus and loaded into the cache holding register, and the high-order word is also loaded into stage B of the pipe. The instruction word for the next sequential prefetch can then be accessed directly from the cache holding register, and no external bus cycle or instruction cache access is required. The cache holding register provides instruction words to the pipe regardless of whether the instruction cache is enabled or disabled.

1-12 M68020 USER’S MANUAL MOTOROLA

INSTRUCTION PIPE

CACHE

HOLDING

INSTRUCTION

FLOW FROM CACHE AND

MEMORY

SEQUENCER

CONTROL

UNIT

EXECUTION

UNIT

STAGE

Figure 1-5. Instruction Pipe

The sequencer is either executing microinstructions or awaiting completion of accesses that are necessary to continue executing microcode. The bus controller is responsible for all bus activity. The sequencer controls the bus controller, instruction execution, and internal processor operations such as the calculation of effective addresses and the setting of condition codes. The sequencer initiates instruction word prefetches and controls the validation of instruction words in the instruction pipe.

Prefetch requests are simultaneously submitted to the cache holding register, the instruction cache, and the bus controller. Thus, even if the instruction cache is disabled, an instruction prefetch may hit in the cache holding register and cause an external bus cycle to be aborted.

1.7 CACHE MEMORY

Due to locality of reference, instructions that are used in a program have a high probability of being reused within a short time. Additionally, instructions that reside in proximity to the instructions currently in use also have a high probability of being utilized within a short period. To exploit these locality characteristics, the MC68020/EC020 contains an on-chip instruction cache.

The cache improves the overall performance of the system by reducing the number of bus cycles required by the processor to fetch information from memory and by increasing the bus bandwidth available for other bus masters in the system.

MOTOROLA M68020 USER’S MANUAL 1-13

SECTION 2 PROCESSING STATES

This section describes the processing states of the MC68020/EC020. It describes the functions of the bits in the supervisor portion of the SR and the actions taken by the processor in response to exception conditions.

Unless the processor has halted, it is always in either the normal or the exception processing state. Whenever the processor is executing instructions or fetching instructions or operands, it is in the normal processing state. The processor is also in the normal processing state while it is storing instruction results or communicating with a coprocessor.

NOTE

Exception processing refers specifically to the transition from normal processing of a program to normal processing of system routines, interrupt routines, and other exception handlers. Exception processing includes all stacking operations, the fetch of the exception vector, and the filling of the instruction pipe caused by an exception. Exception processing has completed when execution of the first instruction of the exception handler routine begins.

The processor enters the exception processing state when an interrupt is acknowledged, when an instruction is traced or results in a trap, or when some other exception condition arises. Execution of certain instructions or unusual conditions occurring during the execution of any instruction can cause exceptions. External conditions, such as interrupts, bus errors, and some coprocessor responses, also cause exceptions. Exception processing provides an efficient transfer of control to handlers and routines that process the exceptions.

A catastrophic system failure occurs whenever the processor receives a bus error or generates an address error while in the exception processing state. This type of failure halts the processor. For example, if during the exception processing of one bus error another bus error occurs, the MC68020/EC020 has not completed the transition to normal processing and has not completed saving the internal state of the machine; therefore, the processor assumes that the system is not operational and halts. Only an external reset can restart a halted processor. (When the processor executes a STOP instruction, it is in a special type of normal processing state—one without bus cycles. It is stopped, not halted.)

MOTOROLA M68020 USER’S MANUAL 2-1

2.1 PRIVILEGE LEVELS

The processor operates at one of two privilege levels: the user level or the supervisor level . The supervisor level has higher privileges than the user level. Not all processor or coprocessor instructions are permitted to execute at the lower privileged user level, but all are available at the supervisor level. This arrangement allows a separation of supervisor and user so the supervisor can protect system resources from uncontrolled access. The S-bit in the SR is used to select either the user or supervisor privilege level and either the USP or an SSP for stack operations. The processor identifies a bus access (supervisor or user mode) via the function codes so that differentiation between supervisor level and user level can be maintained.

In many systems, the majority of programs execute at the user level. User programs can access only their own code and data areas and can be restricted from accessing other information. The operating system typically executes at the supervisor privilege level. It has access to all resources, performs the overhead tasks for the user-level programs, and coordinates user-level program activities.

2.1.1 Supervisor Privilege Level

The supervisor level is the higher privilege level. The privilege level is determined by the S-bit of the SR; if the S-bit is set, the supervisor privilege level applies, and all instructions are executable. The bus cycles for instructions executed at the supervisor level are normally classified as supervisor references, and the values of the FC2–FC0 signals refer to supervisor address spaces.

In a multitasking operating system, it is more efficient to have a supervisor stack space associated with each user task and a separate stack space for interrupt-associated tasks. The MC68020/EC020 provides two supervisor stacks, master and interrupt; the M bit of the SR selects which of the two is active. When the M-bit is set, references to the SSP implicitly or to address register seven (A7) explicitly, access the MSP. The operating system sets the MSP for each task to point to a task-related area of supervisor data space. This arrangement separates task-related supervisor activity from asynchronous, I/O-related supervisor tasks that may be only coincidental to the currently executing task. The MSP can separately maintain task control information for each currently executing user task, and the software updates the MSP when a task switch is performed, providing an efficient means for transferring task-related stack items. The other supervisor stack pointer, the ISP, can be used for interrupt control information and workspace area as interrupt handling routines require.

When the M-bit is clear, the MC68020/EC020 is in the interrupt mode of the supervisor privilege level, and operation is the same as supervisor mode in the MC68000, MC68HC001, MC68008, and MC68010. (The processor is in this mode after a reset operation.) All SSP references access the ISP in this mode.

2-2 M68020 USER’S MANUAL MOTOROLA

The value of the M-bit in the SR does not affect execution of privileged instructions; both master and interrupt modes are at the supervisor privilege level. Instructions that affect the M-bit are MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, and RTE. Also, the processor automatically saves the M-bit value and clears it in the SR as part of exception processing for interrupts.

All exception processing is performed at the supervisor privilege level. All bus cycles generated during exception processing are supervisor references, and all stack accesses use the active SSP.

2.1.2 User Privilege Level

The user level is the lower privilege level. The privilege level is determined by the S-bit of the SR; if the S-bit is clear, the processor executes instructions at the user privilege level.

Most instructions execute at either privilege level, but some instructions that have important system effects are privileged and can only be executed at the supervisor level. For instance, user programs are not allowed to execute the STOP instruction or the RESET instruction. To prevent a user program from entering the supervisor privilege level except in a controlled manner, instructions that can alter the S-bit in the SR are privileged. The TRAP #n instruction provides controlled access to operating system services for user programs.

The bus cycles for an instruction executed at the user privilege level are classified as user references, and the values of the FC2–FC0 signals specify user address spaces. While the processor is at the user level, references to the system stack pointer implicitly, or to address register seven (A7) explicitly, refer to the USP.

2.1.3 Changing Privilege Level

To change from the user to the supervisor privilege level, one of the conditions that causes the processor to perform exception processing must occur. This causes a change from the user level to the supervisor level and can cause a change from the master mode to the interrupt mode. Exception processing saves the current values of the S and M bits of the SR (along with the rest of the SR) on the active supervisor stack, and then sets the S-bit, forcing the processor into the supervisor privilege level. When the exception being processed is an interrupt and the M-bit is set, the M-bit is cleared, putting the processor into the interrupt mode. Execution of instructions continues at the supervisor level to process the exception condition.

To return to the user privilege level, a system routine must execute one of the following instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE. These instructions execute at the supervisor privilege level and can modify the S-bit of the SR. After these instructions execute, the instruction pipeline is flushed and is refilled from the appropriate address space.

The RTE instruction returns to the program that was executing when the exception occurred. It restores the exception stack frame saved on the supervisor stack. If the frame

MOTOROLA M68020 USER’S MANUAL 2-3

on top of the stack was generated by an interrupt, trap, or instruction exception, the RTE instruction restores the SR and PC to the values saved on the supervisor stack. The processor then continues execution at the restored PC address and at the privilege level determined by the S-bit of the restored SR. If the frame on top of the stack was generated by a bus fault (bus error or address error exception), the RTE instruction restores the entire saved processor state from the stack.

2.2 ADDRESS SPACE TYPES

The processor specifies a target address space for every bus cycle with the FC2–FC0 signals according to the type of access required. In addition to distinguishing between supervisor/user and program/data, the processor can identify special processor cycles, such as the interrupt acknowledge cycle, and the memory management unit can control accesses and translate addresses appropriately. Table 2-1 lists the types of accesses defined for the MC68020/EC020 and the corresponding values of the FC2–FC0 signals.

Table 2-1. Address Space Encodings

FC2 FC1 FC0 Address Space

0 0 0 (Undefined, Reserved)* 0 0 1 User Data Space 0 1 0 User Program Space 0 1 1 (Undefined, Reserved)* 1 0 0 (Undefined, Reserved)* 1 0 1 Supervisor Data Space 1 1 0 Supervisor Program Space 1 1 1 CPU Space

* Address space 3 is reserved for user definition; 0 and 4 are reserved

for future use by Motorola.

The memory locations of user program and data accesses are not predefined; neither are the locations of supervisor data space. During reset, the first two long words beginning at memory location zero in the supervisor program space are used for processor initialization. No other memory locations are explicitly defined by the MC68020/EC020.

A function code of $7 selects the CPU address space. This is a special address space that does not contain instructions or operands but is reserved for special processor functions. The processor uses accesses in this space to communicate with external devices for special purposes. For example, all M68000 processors use the CPU space for interrupt acknowledge cycles. The MC68020/EC020 also generate CPU space accesses for breakpoint acknowledge and coprocessor operations.

Supervisor programs can use the MOVES instruction to access all address spaces, including the user spaces and the CPU address space. Although the MOVES instruction can be used to generate CPU space cycles, this may interfere with proper system operation. Thus, the use of MOVES to access the CPU space should be done with caution.

2-4 M68020 USER’S MANUAL MOTOROLA

2.3 EXCEPTION PROCESSING

An exception is defined as a special condition that preempts normal processing. Both internal and external conditions can cause exceptions. External conditions that cause exceptions are interrupts from external devices, bus errors, coprocessor-detected errors, and reset. Instructions, address errors, tracing, and breakpoints are internal conditions that cause exceptions. The TRAP, TRAPcc, TRAPV, cpTRAPcc, CHK, CHK2, RTE, BKPT, CALLM, RTM, cp RESTORE, DIVS and DIVU instructions can generate exceptions as part of their normal execution. In addition, illegal instructions, privilege violations, and coprocessor protocol violations cause exceptions.

Exception processing, which is the transition from the normal processing of a program to the processing required for the exception condition, involves the exception vector table and an exception stack frame. The following paragraphs describe the exception vectors and a generalized exception stack frame. Exception processing is discussed in detail in Section 6 Exception Processing . Coprocessor-detected exceptions are discussed in detail in Section 7 Coprocessor Interface Description.

2.3.1 Exception Vectors

The VBR contains the base address of the 1024-byte exception vector table, which consists of 256 exception vectors. Exception vectors contain the memory addresses of routines that begin execution at the completion of exception processing. These routines perform a series of operations appropriate for the corresponding exceptions. Because the exception vectors contain memory addresses, each consists of one long word, except for the reset vector. The reset vector consists of two long words: the address used to initialize the ISP and the address used to initialize the PC.

The address of an exception vector is derived from an 8-bit vector number and the VBR. The vector numbers for some exceptions are obtained from an external device; others are supplied automatically by the processor. The processor multiplies the vector number by four to calculate the vector offset, which it adds to the VBR. The sum is the memory address of the vector. All exception vectors are located in supervisor data space, except the reset vector, which is located in supervisor program space. Only the initial reset vector is fixed in the processor's memory map; once initialization is complete, there are no fixed assignments. Since the VBR provides the base address of the vector table, the vector table can be located anywhere in memory; it can even be dynamically relocated for each task that is executed by an operating system. Details of exception processing are provided in Section 6 Exception Processing, and Table 6-1 lists the exception vector assignments.

MOTOROLA M68020 USER’S MANUAL 2-5

2.3.2 Exception Stack Frame

15SSP

Exception processing saves the most volatile portion of the current processor context on the top of the supervisor stack. This context is organized in a format called the exception stack frame. This information always includes a copy of the SR, the PC, the vector offset of the vector, and the frame format field. The frame format field identifies the type of stack frame. The RTE instruction uses the value in the format field to properly restore the information stored in the stack frame and to deallocate the stack space. The general form of the exception stack frame is illustrated in Figure 2-1. Refer to Section 6 Exception Processing for a complete list of exception stack frames.

TATUS REGISTE

PROGRAM COUNTER

FORMAT

DDITIONAL PROCESSOR STATE INFORMATIO

(2, 6, 12, OR 42 WORDS, IF NEEDED)

ECTOR OFFSE

Figure 2-1. General Exception Stack Frame

2-6 M68020 USER’S MANUAL MOTOROLA

SECTION 3

SIZ0

SIZ1

OCS

ECS

R/WRMCASDS

DBEN

CDIS

GND

CLK

BERR

HALT

BGBRAVEC

IPL2

IPL1

IPL0

SIGNAL DESCRIPTION

This section contains brief descriptions of the input and output signals in their functional groups, as shown in Figure 3-1. Each signal is explained in a brief paragraph with reference to other sections that contain more detail about the signal and the related operations.

NOTE

In this section and in the remainder of the manual,

negate

In particular, or true;

are used to specify forcing a signal to a particular state.

assertion

negation

and

negate

assert

refer to a signal that is active

indicate a signal that is inactive or

assert

and

false. These terms are used independently of the voltage level (high or low) that they represent.

C2–FC

31–A

31–D

* *

MC68020

NTER

PEN

GAC

ESE

ONT

US A ONT

US E ONT

FUNCTION CODE

ADDRESS BU

ATA BU

RANSFER SIZ

ASYNCHRONOU

BUS CONTRO

SACK SACK

EMULATOR SUPPOR

Figure 3-1. Functional Signal Groups

MOTOROLA M68020 USER’S MANUAL 3-1

3.1 SIGNAL INDEX

The input and output signals for the MC68020/EC020 are listed in Table 3-1. Both the names and mnemonics are shown along with brief signal descriptions. Signals that are implemented in the MC68020, but not in the MC68EC020, have an asterisk (*) preceding the signal name in Table 3-1. Also, note that the address bus is 32 bits wide for the MC68020 and 24 bits wide for the MC68EC020. For more detail on each signal, refer to the paragraph in this section named for the signal and the reference in that paragraph to a description of the related operations.

Timing specifications for the signals listed in Table 3-1 can be found in Section 10

Electrical Characteristics.

3.2 FUNCTION CODE SIGNALS (FC2–FC0)

These three-state outputs identify the address space of the current bus cycle. Table 2-1 shows the relationships of the function code signals to the privilege levels and the address spaces. Refer to Section 2 Processing States for more information.

3.3 ADDRESS BUS (A31–A0, MC68020)(A23–A0, MC68EC020)

These three-state outputs provide the address for the current bus cycle, except in the CPU address space. Refer to Section 2 Processing States for more information on the CPU address space. A31 is the most significant address signal for the MC68020; A23 is the most significant address signal for the MC68EC020. The upper eight bits (A31–A24) are used internally by the MC68EC020 to access the internal instruction cache address tag. Refer to Section 5 Bus Operation for information on the address bus and its relationship to bus operation.

3.4 DATA BUS (D31–D0)

These three-state bidirectional signals provide the general-purpose data path between the MC68020/EC020 and all other devices. The data bus can transfer 8, 16, 24, or 32 bits of data per bus cycle. D31 is the most significant bit of the data bus. Refer to Section 5 Bus

Operation for more information on the data bus and its relationship to bus operation.

3.5 TRANSFER SIZE SIGNALS (SIZ1, SIZ0)

These three-state outputs indicate the number of bytes remaining to be transferred for the current bus cycle. Signals A1, A0, of bits transferred on the data bus. Refer to Section 5 Bus Operation for more information on SIZ1 and SIZ0 and their use in dynamic bus sizing.

3-2 M68020 USER’S MANUAL MOTOROLA

DSACK1, DSACK0, SIZ1, and SIZ0 define the number

Table 3-1. Signal Index

Signal Name Mnemonic Function

Function Codes FC2–FC0 3-bit function code used to identify the address space of each bus cycle. Address Bus

MC68020 MC68EC020

Data Bus D31–D0 32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus

Size SIZ1, SIZ0 Indicates the number of bytes remaining to be transferred for this cycle.

*External Cycle Start ECS Provides an indication that a bus cycle is beginning. *Operand Cycle Start OCS Identical operation to that of ECS except that OCS is asserted only during

Read/Write R/W Defines the bus transfer as a processor read or write. Read-Modify-Write Cycle RMC Provides an indicator that the current bus cycle is part of an indivisible

Address Strobe AS Indicates that a valid address is on the bus. Data Strobe DS Indicates that valid data is to be placed on the data bus by an external

*Data Buffer Enable DBEN Provides an enable signal for external data buffers.

Data Transfer and Size Acknowledge

Interrupt Priority Level IPL2–IPL0 Provides an encoded interrupt level to the processor.

*Interrupt Pending IPEND Indicates that an interrupt is pending.

Autovector AVEC Requests an autovector during an interrupt acknowledge cycle. Bus Request BR Indicates that an external device requires bus mastership. Bus Grant BG Indicates that an external device may assume bus mastership.

*Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus mastership.

Reset RESET System reset. Halt HALT Indicates that the processor should suspend bus activity or that the

Bus Error BERR Indicates that an erroneous bus operation is being attempted. Cache Disable CDIS Statically disables the on-chip cache to assist emulator support. Clock CLK Clock input to the processor. Power Supply V Ground GND Ground connection.

*This signal is implemented in the MC68020 and not implemented in the MC68EC020.

A31–A0 A23–A0

DSACK1,

DSACK0

32-bit address bus 24-bit address bus

cycle.

These signals, together with A1 and A0, define the active sections of the data bus.

the first bus cycle of an operand transfer.

read-modify-write operation.

device or has been placed on the data bus by the MC68020/EC020.

Bus response signals that indicate the requested data transfer operation has completed. In addition, these two lines indicate the size of the external bus port on a cycle-by-cycle basis and are used for asynchronous transfers.

processor has halted due to a double bus fault.

Power supply.

MOTOROLA M68020 USER’S MANUAL 3-3

3.6 ASYNCHRONOUS BUS CONTROL SIGNALS

The following signals control synchronous bus transfer operations for the MC68020/EC020. Note that implemented in the MC68EC020.

OCS, ECS, and DBEN are implemented in MC68020 and not

Operand Cycle Start

This output signal indicates the beginning of the first external bus cycle for an instruction prefetch or a data operand transfer. performed due to dynamic bus sizing or operand misalignment. Refer to Section 5 Bus

Operation for information about the relationship of

(OCS, MC68020 only)

OCS is not asserted for subsequent cycles that are

OCS to bus operation.

OCS is not implemented in the MC68EC020.

External Cycle Start

This output signal indicates the beginning of a bus cycle of any type. Refer to Section 5 Bus Operation for information about the relationship of

(ECS, MC68020 only)

ECS to bus operation.

ECS is not implemented in the MC68EC020.

Read/Write (R/

This three-state output signal defines the type of bus cycle. A high level indicates a read cycle; a low level indicates a write cycle. Refer to Section 5 Bus Operation for information about the relationship of R/

Read-Modify-Write Cycle

This three-state output signal identifies the current bus cycle as part of an indivisible read-modify-write operation; it remains asserted during all bus cycles of the readmodify-write operation. Refer to Section 5 Bus Operation for information about the relationship of

W to bus operation.

(RMC)

RMC to bus operation.

Address Strobe

This three-state output signal indicates that a valid address is on the address bus. The FC2–FC0, SIZ1, SIZ0, and R

Section 5 Bus Operation for information about the relationship of

Data Strobe

During a read cycle, this three-state output signal indicates that an external device should place valid data on the data bus. During a write cycle, MC68020/EC020 has placed valid data on the bus. During two-clock synchronous write cycles, the MC68020/EC020 does not assert more information about the relationship of

3-4 M68020 USER’S MANUAL MOTOROLA

(AS)

/W signals are also valid when AS is asserted. Refer to

AS to bus operation.

(DS)

DS indicates that the

DS. Refer to Section 5 Bus Operation for

DS to bus operation.

Data Buffer Enable (DBEN, MC68020 only)

This output signal is an enable signal for external data buffers. This signal may not be required in all systems. Refer to Section 5 Bus Operation for more information about the relationship of

DBEN to bus operation.

DBEN is not implemented in the MC68EC020.

Data Transfer and Size Acknowledge

These input signals indicate the completion of a requested data transfer operation. In addition, they indicate the size of the external bus port at the completion of each cycle. These signals apply only to asynchronous bus cycles. Refer to Section 5 Bus Operation for more information on these signals and their relationship to dynamic bus sizing.

(DSACK1, DSACK0)

3.7 INTERRUPT CONTROL SIGNALS

The following signals are the interrupt control signals for the MC68020/EC020. Note that

IPEND is implemented in the MC68020 and not implemented in the MC68EC020.

Interrupt Priority Level Signals

These input signals provide an indication of an interrupt condition and the encoding of the interrupt level from a peripheral or external prioritizing circuitry. significant bit of the level number. For example, since the

IPL2–IPL0 equal to $5 corresponds to an interrupt request at interrupt level 2.

low, Refer to Section 6 Exception Processing for information on MC68020/EC020 interrupts.

Interrupt Pending

This output signal indicates that an interrupt request exceeding the current interrupt priority mask in the SR has been recognized internally. This output is for use by external devices (coprocessors and other bus masters, for example) to predict processor operation on the following instruction boundaries. Refer to Section 6 Exception Processing for interrupt information. Also, refer to Section 5 Bus Operation for bus information related to interrupts.

(IPEND, MC68020 only)

(IPL2–IPL0)

IPL2 is the most

IPL2–IPL0 signals are active

IPEND is not implemented in the MC68EC020.

Autovector

This input signal indicates that the MC68020/EC020 should generate an automatic vector during an interrupt acknowledge cycle. Refer to Section 5 Bus Operation for more information about automatic vectors.

MOTOROLA M68020 USER’S MANUAL 3-5

(AVEC)

3.8 BUS ARBITRATION CONTROL SIGNALS

The following signals are the bus arbitration control signals used to determine which device in a system is the bus master. Note that and not implemented in the MC68EC020.

BGACK is implemented in the MC68020

Bus Request

This input signal indicates that an external device needs to become the bus master. BR is typically a “wire-ORed” input (but does not need to be constructed from open-collector devices). Refer to Section 5 Bus Operation for more information on MC68020 bus arbitration. Refer to Section 5 Bus Operation and Appendix A Interfacing an

MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol for more information on MC68EC020 bus arbitration.

Bus Grant

This output signal indicates that the MC68020/EC020 will release ownership of the bus when the current processor bus cycle completes. Refer to Section 5 Bus Operation for more information on MC68020 bus arbitration. Refer to Section 5 Bus Operation and

Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a ThreeWire Bus Arbitration Protocol for more information on MC68EC020 bus arbitration.

Bus Grant Acknowledge

This input signal indicates that an external device has become the bus master. Refer to

Section 5 Bus Operation for more information on MC68020 bus arbitration. Refer to Section 5 Bus Operation and Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol for more information

on MC68EC020 bus arbitration.

(BR)

(BG)

(BGACK, MC68020 only)

BGACK is not implemented in the MC68EC020.

3.9 BUS EXCEPTION CONTROL SIGNALS

The following signals are the bus exception control signals for the MC68020/EC020.

Reset

(RESET)

This bidirectional open-drain signal is used to initiate a system reset. An external reset signal resets the MC68020/EC020 as well as all external devices. A reset signal from the processor (asserted as part of the RESET instruction) resets external devices only; the internal state of the processor is not altered. Refer to Section 5 Bus Operation for a description of reset bus operation and Section 6 Exception Processing for information about the reset exception.

3-6 M68020 USER’S MANUAL MOTOROLA

Halt (HALT)

The assertion of this bidirectional open-drain signal indicates that the processor should suspend bus activity or, when used with current cycle. Refer to Section 5 Bus Operation for a description of the effects of

BERR, that the processor should retry the

HALT on bus operations. When the processor has stopped executing instructions due

to a double bus fault condition, the external devices that the processor has stopped.

HALT line is asserted by the processor to indicate to

Bus Error

This input signal indicates that an invalid bus operation is being attempted or, when used with

Bus Operation for a description of the effects of

(BERR)

HALT, that the processor should retry the current cycle. Refer to Section 5

BERR on bus operations.

3.10 EMULATOR SUPPORT SIGNAL

The following signal supports emulation by providing a means for an emulator to disable the on-chip cache by supplying internal status information to an emulator. Refer to Section 7 Coprocessor Interface Description for more detailed information on emulation support.

Cache Disable

This input signal statically disables the on-chip cache to assist emulator support. Refer to Section 4 On-Chip Cache Memory for information about the cache; refer to Section

9 Applications Information for a description of the use of this signal by an emulator.

(CDIS)

CDIS does not flush the instruction cache; entries remain unaltered and become

available again when

CDIS is negated.

3.11 CLOCK (CLK)

The CLK signal is the clock input to the MC68020/EC020. This TTL-compatible signal should not be gated off at any time while power is applied to the processor. Refer to

Section 9 Applications Information for suggestions on clock generation. Refer to Section 10 Electrical Characteristics for electrical characteristics.

3.12 POWER SUPPLY CONNECTIONS

The MC68020/EC020 requires connection to a VCC power supply, positive with respect to ground. The V sections of the processor. The ground connections are similarly grouped. Section 11 Ordering Information and Mechanical Data describes the groupings of V connections, and Section 9 Applications Information describes a typical power supply interface.

MOTOROLA M68020 USER’S MANUAL 3-7

connections are grouped to supply adequate current for the various

and ground

3.13 SIGNAL SUMMARY

Table 3-2 provides a summary of the characteristics of the signals discussed in this section. Signal names preceded by an asterisk (*) are implemented in the MC68020 and not implemented in the MC68EC020.

Table 3-2. Signal Summary

Signal Function Signal Name Input/Output Active State Three-State

Function Codes FC2–FC0 Output High Yes Address Bus

MC68020

MC68EC020 Data Bus D31–D0 Input/Output High Yes Transfer Size SIZ1, SIZ0 Output High Yes *Operand Cycle Start OCS Output Low No *External Cycle Start ECS Output Low No Read/Write R/W Output High/Low Yes Read-Modify-Write Cycle RMC Output Low Yes Address Strobe AS Output Low Yes Data Strobe DS Output Low Yes *Data Buffer Enable DBEN Output Low Yes Data Transfer and Size Acknowledge DSACK1, DSACK0 Input Low — Interrupt Priority Level IPL2–IPL0 Input Low — *Interrupt Pending IPEND Output Low No Autovector AVEC Input Low — Bus Request BR Input Low — Bus Grant BG Output Low No *Bus Grant Acknowledge BGACK Input Low — Reset RESET Input/Output Low No** Halt HALT Input/Output Low No** Bus Error BERR Input Low — Cache Disable CDIS Input Low — Clock CLK Input — — Power Supply V Ground GND Input — —

A31–A0 A23–A0

*This signal is implemented in the MC68020 and not implemented in the MC68EC020. **Open-drain

Output High Yes

Input — —

3-8 M68020 USER’S MANUAL MOTOROLA

SECTION 4 ON-CHIP CACHE MEMORY

The MC68020/EC020 incorporates an on-chip cache memory as a means of improving performance. The cache is implemented as a CPU instruction cache and is used to store the instruction stream prefetch accesses from the main memory.

An increase in instruction throughput results when instruction words required by a program are available in the on-chip cache and the time required to access them on the external bus is eliminated. In systems with more than one bus master (e.g., a processor and a DMA device), reduced external bus activity increases overall performance by increasing the availability of the bus for use by external devices without degrading the performance of the MC68020/EC020.

4.1 ON-CHIP CACHE ORGANIZATION AND OPERATION

The MC68020/EC020 on-chip instruction cache is a direct-mapped cache of 64 long-word entries. Each cache entry consists of a tag field (A31–A8 and FC2), one valid bit, and 32 bits (two words) of instruction data. Figure 4-1 shows a block diagram of the on-chip cache organization.

Externally, the MC68EC020 does not use the upper eight bits of the address ( A31–A24), and addresses $FF000000 and $00000000 from the MC68EC020 appear the same. However, the MC68EC020 does use A31–A24 internally in the instruction cache address tag, and addresses $FF000000 and $00000000 appear different in the MC68EC020 instruction cache. The MC68020, MC68030/EC030, and MC68040/EC040 use all 32 bits of the address externally. To maintain object-code upgrade compatibility when designing with the MC68EC020, the upper eight bits should be considered part of the address when assigning address spaces in hardware.

When enabled, the MC68020/EC020 instruction cache is used to store instruction prefetches (instruction words and extension words) as they are requested by the CPU. Instruction prefetches are normally requested from sequential memory addresses except when a change of program flow occurs (e.g., a branch taken) or when an instruction is executed that can modify the SR. In these cases, the instruction pipe is automatically flushed and refilled.

MOTOROLA M68020 USER’S MANUAL 4-1

F C 1

F C 0

A 3 1

A 2 3

A 2 2

A 2 1

A 2 0

A 1 9

A 1 6

A 1 5

A 1 4

A 1 3

A 1 2

A 1 1 A 10A9A8A7A6A5A4A3A2A1A 0

TAG

INDEX

TAGVWORD

WORD

SELECT

1 OF

4 SELEC

TAG REPLACE

COMPARATOR

REPLACEMENT D

TO I

CACHE C

ENTRY HIT

LINE

VALID

C68020/EC020 PREFETCH ADDRES

A 1

ATA

NSTRUCTIO

ATH

ONTRO

HIT

Figure 4-1. MC68020/EC020 On-Chip Cache Organization

When an instruction fetch occurs, the cache (if enabled) is first checked to determine if the word required is in the cache. This check is achieved by first using the index field (A7–A2) of the access address as an index into the on-chip cache. This index selects one of the 64 entries in the cache. Next, A31–A8 and FC2 are compared to the tag of the selected entry. (Note that in the MC68EC020, A31–A24 are used for internal on-chip cache tag comparison.) If there is a match and the valid bit is set, a cache hit occurs. A1 is then used to select the proper word from the cache entry, and the cycle ends. If there is no match or if the valid bit is clear, a cache miss occurs, and the instruction is fetched from external memory. This new instruction is automatically written into the cache entry, and the valid bit is set unless the F-bit in the CACR is set. Since the processor always prefetches instructions externally with long-word-aligned bus cycles, both words of the entry will be updated, regardless of which word caused the miss.

NOTE

Data accesses are not cached, regardless of their associated address space.

4–2 M68020 USER’S MANUAL MOTOROLA

4.2 CACHE RESET

31E1F2CE3C405060708

During processor reset, the cache is cleared by resetting all of the valid bits. The E and F bits in the CACR are also cleared.

4.3 CACHE CONTROL

Only the MC68020/EC020 cache control circuitry can directly access the cache array, but a supervisor program can set bits in the CACR to exercise control over cache operations. The supervisor level also has access to the CAAR, which contains the address for a cache entry to be cleared.

System hardware can assert the

CDIS signal to disable the cache. The assertion of CDIS

disables the cache, regardless of the state of the E-bit in the CACR . CDIS is primarily intended for use by in-circuit emulators.

4.3.1 Cache Control Register (CACR)

The CACR, shown in Figure 4-2, is a 32-bit register than can be written or read by the MOVEC instruction or indirectly modified by a reset. Four of the bits (3–0) control the instruction cache. Bits 31–4 are reserved for Motorola definition. They are read as zeros and are ignored when written. For future compatibility, writes should not set these bits.

Figure 4-2. Cache Control Register

C—Clear Cache

The C-bit is set to clear all entries in the instruction cache. Operating systems and other software set this bit to clear instructions from the cache prior to a context switch. The processor clears all valid bits in the instruction cache when a MOVEC instruction sets the C-bit. The C-bit is always read as a zero.

CE—Clear Entry In Cache

The CE bit is set to clear an entry in the instruction cache. The index field of the CAAR (see Figure 4-3), corresponding to the index and long-word select portion of an address, specifies the entry to be cleared. The processor clears only the specified long word by clearing the valid bit for the entry when a MOVEC instruction sets the CE bit, regardless of the states of the E and F bits. The CE bit is always read as a zero.

MOTOROLA M68020 USER’S MANUAL 4-3

F—Freeze Cache

78R

The F-bit is set to freeze the instruction cache. When the F-bit is set and a cache miss occurs, the entry (or line) is not replaced. When the F-bit is clear, a cache miss causes the entry (or line) to be filled. A reset operation clears the F-bit.

E—Enable Cache

The E-bit is set to enable the instruction cache. When it is clear, the instruction cache is disabled. A reset operation clears the E-bit. The supervisor normally enables the instruction cache, but it can clear the E-bit for system debugging or emulation, as required. Disabling the instruction cache does not flush the entries. If the cache is reenabled, the previously valid entries remain valid and may be used.

4.3.2 Cache Address Register (CAAR)

The format of the 32-bit CAAR is shown in Figure 4-3.

ESERVE

Figure 4-3. Cache Address Register

INDEX

RESERVED

Bits 31–8, 1, and 0—Reserved

These bits are reserved for use by Motorola.

Index Field

The index field contains the address for the “clear cache entry” operations. The bits of this field, which correspond to A7–A2, specify the index and a long word of a cache line.

4–4 M68020 USER’S MANUAL MOTOROLA

SECTION 5 BUS OPERATION

This section provides a functional description of the bus, the signals that control it, and the bus cycles provided for data transfer operations. It also describes the error and halt conditions, bus arbitration, and reset operation. Operation of the bus is the same whether the processor or an external device is the bus master ; the names and descriptions of bus cycles are from the point of view of the bus master. For exact timing specifications, refer to Section 10 Electrical Characteristics.

The MC68020/EC020 architecture supports byte, word, and long-word operands, allowing access to 8-, 16-, and 32-bit data ports through the use of asynchronous cycles controlled by the DSACK1 and DSACK0 input signals.

The MC68020/EC020 allows byte, word, and long-word operands to be located in memory on any byte boundary. For a misaligned transfer, more than one bus cycle may be required to complete the transfer, regardless of port size. For a port less than 32 bits wide, multiple bus cycles may be required for an operand transfer due to either misalignment or a port width smaller than the operand size. Instruction words and their associated extension words must be aligned on word boundaries. The user should be aware that misalignment of word or long-word operands can cause the MC68020/EC020 to perform multiple bus cycles for the operand transfer; therefore, processor performance is optimized if word and long-word memory operands are aligned on word or long-word boundaries, respectively.

5.1 BUS TRANSFER SIGNALS

The bus transfers information between the MC68020/EC020 and an external memory, coprocessor, or peripheral device. External devices can accept or provide 8 bits, 16 bits, or 32 bits in parallel and must follow the handshake protocol described in this section. The maximum number of bits accepted or provided during a bus transfer is defined as the port width. The MC68020/EC020 contains an address bus that specifies the address for the transfer and a data bus that transfers the data. Control signals indicate the beginning of the cycle, the address space and size of the transfer, and the type of cycle. The selected device then controls the length of the cycle with the signal(s) used to terminate the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity of the address and provide timing information for the data.

The bus operates in an asynchronous mode for any port width. The bus and control input signals are internally synchronized to the MC68020/EC020 clock, introducing a delay. This delay is the time period required for the MC68020/EC020 to sample an input signal, synchronize the input to the internal clocks of the processor, and determine whether the

MOTOROLA M68020 USER’S MANUAL 5- 1

input is high or low. Figure 5-1 shows the relationship between the clock signal, a typical

SYNC DELAY

CLK

EXT

INT

tsut

SAMPLE

CLK

EXT

input, and its associated internal signal. Furthermore, for all inputs, the processor latches the level of the input during a sample

window around the falling edge of the clock signal. This window is illustrated in Figure 5-2. To ensure that an input signal is recognized on a specific falling edge of the clock, that input must be stable during the sample window. If an input transitions during the window, the level recognized by the processor is not predictable; however, the processor always resolves the latched level to either a logic high or logic low before using it. In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this section.

Figure 5-1. Relationship between External and Internal Signals

INDOW

Figure 5-2. Input Sample Window

5.1.1 Bus Control Signals

The MC68020/EC020 initiates a bus cycle by driving the A1–A0, SIZ1, SIZ0, FC2–FC0, and R/W outputs. However, if the MC68020/EC020 finds the required instruction in the onchip cache, the processor aborts the cycle before asserting the AS.The assertion of AS ensures that the cycle has not been aborted by these internal conditions.

5-2 M68020 USER’S MANUAL MOTOROLA

When initiating a bus cycle, the MC68020 asserts ECS in addition to A1–A0, SIZ1, SIZ0, FC2–FC0, and R/W. ECS can be used to initiate various timing sequences that are eventually qualified with AS. Qualification with AS may be required since, in the case of an internal cache hit, a bus cycle may be aborted after ECS has been asserted. During the first MC68020 external bus cycle of an operand transfer, OCS is asserted with ECS. When several bus cycles are required to transfer the entire operand, OCS is asserted only at the beginning of the first external bus cycle. With respect to OCS , an “operand” is any entity required by the execution unit, whether a program or data item. Note that ECS and OCS are not implemented in the MC68EC020.

The FC2–FC0 signals select one of eight address spaces (see Table 2-1) to which the address applies. Five address spaces are presently defined. Of the remaining three, one is reserved for user definition, and two are reserved by Motorola for future use. FC2–FC0 are valid while AS is asserted.

The SIZ1 and SIZ0 signals indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles) or during a cache fill operation from a device with a port size that is less than 32 bits. Table 5-2 lists the encoding of SIZ1 and SIZ0. SIZ1 and SIZ0 are valid while AS is asserted.

The R/ W signal determines the direction of the transfer during a bus cycle. When required, this signal changes state at the beginning of a bus cycle and is valid while AS is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa. This signal may remain low for two consecutive write cycles.

The RMC signal is asserted at the beginning of the first bus cycle of a read-modify-write operation and remains asserted until completion of the final bus cycle of the operation. The RMC signal is guaranteed to be negated before the end of state 0 for a bus cycle following a read-modify-write operation.

5.1.2 Address Bus

A31–A0 (for the MC68020) or A23–A0 (for the MC68EC020) define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The processor places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted. In the MC68EC020, A31–A24 are used internally, but not externally.

5.1.3 Address Strobe

AS is a timing signal that indicates the validity of an address on the address bus and of many control signals. It is asserted one-half clock after the beginning of a bus cycle.

5.1.4 Data Bus

D31–D0 comprise a bidirectional, nonmultiplexed parallel bus that contains the data being transferred to or from the processor. A read or write operation may transfer 8, 16, 24, or 32 bits of data (one, two, three, or four bytes) in one bus cycle. During a read cycle, the data is latched by the processor on the last falling edge of the clock for that bus cycle. For

MOTOROLA M68020 USER’S MANUAL 5- 3

a write cycle, all 32 bits of the data bus are driven, regardless of the port width or operand size. The processor places the data on the data bus one-half clock cycle after AS is asserted in a write cycle.

5.1.5 Data Strobe

DS is a timing signal that applies to the data bus. For a read cycle, the processor asserts DS to signal the external device to place data on the bus. DS is asserted at the same time

as AS during a read cycle. For a write cycle, DS notifies the external device that the data to be written is valid. The processor asserts DS one full clock cycle after the assertion of AS during a write cycle.

5.1.6 Data Buffer Enable

The MC68020 DBEN signal is used to enable external data buffers while data is present on the data bus. During a read operation, DBEN is asserted one clock cycle after the beginning of the bus cycle and is negated as DS is negated. In a write operation, DBEN is asserted at the time AS is asserted and is held active for the duration of the cycle. Note that DBEN is implemented in the MC68020 and is not implemented in the MC68EC020.

5.1.7 Bus Cycle Termination Signals

During bus cycles, external devices assert DSACK1/DSACK0 as part of the bus protocol. During a read cycle, DSACK1/DSACK0 assertion signals the processor to terminate the bus cycle and to latch the data. During a write cycle, the assertion of DSACK1/DSACK0 indicates that the external device has successfully stored the data and that the cycle may terminate. DSACK1/DSACK0 also indicate to the processor the size of the port for the bus cycle just completed, as shown in Table 5-1. Refer to 5.3.1 Read Cycle for timing relationships of DSACK1/DSACK0.

The BERR signal is also a bus cycle termination indicator and can be used in the absence of DSACK1/DSACK0 to indicate a bus error condition. It can also be asserted in conjunction with DSACK1/DSACK0 to indicate a bus error condition, provided it meets the appropriate timing described in this section and in Section 10 Electrical Characteristics. Additionally, the BERR and HALT signals can be asserted together to indicate a retry termination. Again, the BERR and HALT signals can be simultaneously asserted in lieu of, or in conjunction with, the DSACK1/DSACK0 signals.

Finally, the AVEC signal can be used to terminate interrupt acknowledge cycles, indicating that the MC68020/EC020 should generate a vector number to locate an interrupt handler routine. AVEC is ignored during all other bus cycles.

5-4 M68020 USER’S MANUAL MOTOROLA

5.2 DATA TRANSFER MECHANISM

DSACK1/DSACK0

DSACK1 DSACK0

The MC68020/EC020 architecture supports byte, word, and long-word operands allowing access to 8-, 16-, and 32-bit data ports through the use of asynchronous cycles controlled by DSACK1/DSACK0 . Byte, word, and long-word operands can be located on any byte boundary, but misaligned transfers may require additional bus cycles, regardless of port size.

5.2.1 Dynamic Bus Sizing

The MC68020/EC020 dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8-, 16-, and 32-bit ports. During an operand transfer cycle, the slave device signals its port size (byte, word, or long word) and indicates completion of the bus cycle to the processor with the DSACK1/DSACK0 signals. Refer to Table 5-1 for DSACK1/DSACK0 encodings and assertion results.

Table 5-1.

Negated Negated Insert Wait States in Current Bus Cycle

Negated Asserted Complete Cycle—Data Bus Port Size is 8 Bits Asserted Negated Complete Cycle—Data Bus Port Size is 16 Bits Asserted Asserted Complete Cycle—Data Bus Port Size is 32 Bits

Encodings and Results

Result

For example, if the processor is executing an instruction that reads a long-word operand from a long-word-aligned address, it attempts to read 32 bits during the first bus cycle. (Refer to 5.2.2 Misaligned Operands for the case of a word or byte address.) If the port responds that it is 32 bits wide, the MC68020/EC020 latches all 32 bits of data and continues with the next operation. If the port responds that it is 16 bits wide, the MC68020/EC020 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits. The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the DSACK1/DSACK0 signals to indicate the port width. For instance, a 32-bit device always returns DSACK1/DSACK0 for a 32-bit port, regardless of whether the bus cycle is a byte, word, or long-word operation.

Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 32-bit port must reside on D31–D0, a 16-bit port must reside on D32–D16, and an 8-bit port must reside on D31–D24. This requirement minimizes the number of bus cycles needed to transfer data to 8- and 16-bit ports and ensures that the MC68020/EC020 correctly transfers valid data. The MC68020/EC020 always attempts to transfer the maximum amount of data on all bus cycles; for a long word operation, it always assumes that the port is 32 bits wide when beginning the bus cycle.

The bytes of operands are designated as shown in Figure 5-3. The most significant byte of a long-word operand is OP0; the least significant byte is OP3. The two bytes of a word length operand are OP2 (most significant) and OP3. The single byte of a byte-length operand is OP3. These designations are used in the figures and descriptions that follow.

MOTOROLA M68020 USER’S MANUAL 5- 5

OP0

OP1

OP2

OP3310150

OP2

OP370

LONG-WORD OPERAND

WORD OPERAND

BYTE OPERAND

OP3

Figure 5-3. Internal Operand Representation

0123ROUTING AND DUPLICATION

BYTE 0

BYTE 2

BYTE 1

BYTE 3

16-BIT PORT

MULTIPLEXER

EXTERNAL DATA BUS

ADDRESS

xxxxxxx0

INCREASING A

D31– D24

D23–D16

D15–D8

D7–D0

BYTE 0

BYTE 1

BYTE 2

BYTE 3

BYTE 0

BYTE 1

BYTE 2

8-BIT PORT

xxxxxxx0

EXTERNAL BUS

INTERNAL TO

32-BIT PORT

OP0

OP1

OP2

OP3

Figure 5-4 shows the required organization of data ports on the MC68020/EC020 bus for 8-, 16-, and 32-bit devices. The four bytes shown in Figure 5-4 are connected through the internal data bus and data multiplexer to the external data bus. This path is the means through which the MC68020/EC020 supports dynamic bus sizing and operand misalignment. Refer to 5.2.2 Misaligned Operands for the definition of misaligned operand. The data multiplexer establishes the necessary connections for different combinations of address and data sizes.

THE MC68020/EC02

xxxxxxx0

MEMORY

DDRESSE

5-6 M68020 USER’S MANUAL MOTOROLA

Figure 5-4. MC68020/EC020 Interface to Various Port Sizes

The multiplexer takes the four bytes of the 32-bit bus and routes them to their required positions. For example, OP0 can be routed to D31–D24, as would be the normal case, or it can be routed to any other byte position to support a misaligned transfer. The same is true for any of the operand bytes. The positioning of bytes is determined by the SIZ1, SIZ0, A1, and A0 outputs.

The SIZ1 and SIZ0 outputs indicate the remaining number of bytes to be transferred during the current bus cycle, as listed in Table 5-2.

Table 5-2. SIZ1, SIZ0 Signal Encoding

SIZ1 SIZ0 Size

Negated Asserted Byte Asserted Negated Word Asserted Asserted 3 Bytes

Negated Negated Long Word

The number of bytes transferred during a write or read bus cycle is equal to or less than the size indicated by the SIZ1 and SIZ0 outputs, depending on port width and operand alignment. For example, during the first bus cycle of a long-word transfer to a word port, the SIZ1 and SIZ0 outputs indicate that four bytes are to be transferred, although only two bytes are moved on that bus cycle.

A1–A0 also affect operation of the data multiplexer. During an operand transfer, A31–A2 (for the MC68020) or A23–A2 (for the MC68EC020) indicate the long-word base address of that portion of the operand to be accessed; A1 and A0 indicate the byte offset from the base. Table 5-3 lists the encodings of A1 and A0 and the corresponding byte offsets from the long-word base.

Table 5-3. Address Offset Encodings

A1 A0 Offset

Negated Negated +0 Bytes

Negated Asserted +1 Byte Asserted Negated +2 Bytes Asserted Asserted +3 Bytes

MOTOROLA M68020 USER’S MANUAL 5- 7

Table 5-4 lists the bytes required on the data bus for read cycle s. The entries shown as OP3, OP2, OP1, and OP0 are portions of the requested operand that are read or written during that bus cycle and are defined by SIZ1, SIZ0, A1, and A0 for the bus cycle.

Table 5-4. Data Bus Requirements for Read Cycles

Transfer

Size

SIZ1 SIZ0 A1 A0

Byte 0

Word 1

3 Bytes 1

100 1

0 0

000 0

1 1

100 1

1 1

AddressSize

01 1

0 1

01 1

0 1

01 1

0 1

Long-Word Port

External Data Bytes

Required

OP3 OP3

OP3

OP2 OP2

OP1 OP1

OP3 OP2

OP1

OP3 OP2

OP3OP2

OP1

OP3 OP2

OP3OP2 OP2 OP1

Word Port

External Data Bytes

OP3

OP2

OP1

Required

OP3

OP3 OP3

OP3

OP2

OP3

OP2 OP2

OP2 OP1 OP2 OP1 OP1

Byte Port

External

Data Bytes

Required

D31–D24D23–D16D31–D24D23–D16D31–D24 D7–D0D15–D8

OP3 OP3 OP3

OP2 OP2 OP2

OP1 OP1 OP1

Long Word 0

000 0

0 0

01 1

0 1

OP0 OP0

OP1 OP0

OP2 OP1 OP0

OP3

OP2 OP1 OP0

OP0

OP1 OP0 OP1 OP0 OP0

OP0 OP0 OP0

5-8 M68020 USER’S MANUAL MOTOROLA

Table 5-5 lists the combinations of SIZ1, SIZ0, A1, and A0 and the corresponding pattern of the data transfer for write cycles from the internal multiplexer of the MC68020/EC020 to the external data bus.

Table 5-5. MC68020/EC020 Internal to External Data Bus

Multiplexer—Write Cycles

Transfer

Size

SIZ1 SIZ0 A1 A0

Byte 0 1 x x

Word 1

3 Bytes 1

1 1 1

Long Word 0

0 0 0

AddressSize

100 1

01 1

1 1

000 0

01 1

0 0

D31–D24

0 1

External Data Bus

D23–D16

OP3

OP2 OP2

OP1 OP1

OP0 OP0

Connection

OP3

OP3 OP2

OP1 OP2

OP1

OP1 OP0 OP1

OP0 OP1*

OP3

OP2

OP3

OP3OP2

OP1

OP2*

OP2 OP1 OP0

D7–D0D15–D8

OP3

OP3 OP2

OP0*

OP3OP2 OP2 OP1

OP3 OP2 OP1

OP0

*Due to the current implementation, this byte is output but never used.

x = Don't care NOTE: The OP tables on the external data bus refer to a particular byte of the operand that is written on that section of the data bus.

MOTOROLA M68020 USER’S MANUAL 5- 9

Figure 5-5 shows the transfer (write) of a long-word operand to a word port. In the first bus

DATA BUS

D31

D16

LONG-WORD OPERAND

OP0

OP1

OP2

OP3310

WORD MEMORY

MSB

LSB

OP0

OP1

OP2

OP3

MC68020/EC020

SIZ1

SIZ0A1A0000 0 1010

MEMORY CONTROL

DSACK1

DSACK0

LHL

cycle, the MC68020/EC020 places the four operand bytes on the external bus. Since the address is long-word aligned in this example, the multiplexer follows the pattern in the entry of Table 5-5 corresponding to SIZ0, SIZ1, A0, A1 = 0000. The port latches the data on D31–D16, asserts DSACK1 (DSACK0 remains negated), and the processor terminates the bus cycle. It then starts a new bus cycle with SIZ1, SIZ0, A1, A0 = 1010 to transfer the remaining 16 bits. SIZ1 and SIZ0 indicate that a word remains to be transferred; A1 and A0 indicate that the word corresponds to an offset of two from the base address. The multiplexer follows the pattern corresponding to this configuration of SIZ1, SIZ0, A1, and A0 and places the two least significant bytes of the long word on the word portion of the bus (D31–D16). The bus cycle transfers the remaining bytes to the word-sized port. Figure 5-6 shows the timing of the bus transfer signals for this operation.

Figure 5-5. Long-Word Operand Write to Word Port Example

5-10 M68020 USER’S MANUAL MOTOROLA

WORD WRITE

LONG-WORD OPERAND WRITE TO 16-BIT PORT

S0S2S4S0S2S4CLK

A31–A2

A1A0FC2–FC0

SIZ1

SIZ0

R/W

ECS

OCSASDS

DSACK1

DSACK0

DBEN

D31–D24

D23–D16

WORD WRITE

OP0

OP1

OP2

OP3

********

Figure 5-6. Long-Word Operand Write to Word Port Timing

MOTOROLA M68020 USER’S MANUAL 5- 11

For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020.

Figure 5-7 shows a word write to an 8-bit bus port. Like the preceding example, this

OP2

OP3150

WORD OPERAND

D31

DATA BUS

D24

BYTE MEMORY

OP2

OP3

MC68020/EC020

SIZ1

SIZ0A1A0

1 0 0 0 0

MEMORY CONTROL

DSACK1

DSACK0

HLH

example requires two bus cycles. Each bus cycle transfers a single byte. SIZ1 and SIZ0 for the first cycle specify two bytes; for the second cycle, one byte. Figure 5-8 shows the associated bus transfer signal timing.

1 0 1

Figure 5-7. Word Operand Write to Byte Port Example

5-12 M68020 USER’S MANUAL MOTOROLA

MOTOROLA M68020 USER’S MANUAL 5- 13

BYTE WRITE

WORD OPERAND WRITE

S0S2S4S0S2S4CLK

A31–A2

A1A0FC2–FC0

SIZ1

SIZ0

R/W

ECS

OCSASDS

DSACK1

DSACK0

DBEN

D31–D24

D23–D16

BYTE WRITE

D15–D8

D7–D0

********

For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020.

Figure 5-8. Word Operand Write to Byte Port Timing

5.2.2 Misaligned Operands

DATA BUS

D31

D16

LONG-WORD OPERAND

OP0

OP1

OP2

OP3310

WORD MEMORY

MSB

LSB

XXX

OP0

OP1

OP2

MC68020/EC020

SIZ1

SIZ0A2A1000 0 1101

MEMORY CONTROL

DSACK1

DSACK0

LHLHOP3

XXXA01001100LH

Since operands may reside at any byte boundary, they may be misaligned. A byte operand is properly aligned at any address; a word operand is misaligned at an odd address; a long word is misaligned at an address that is not evenly divisible by four. The MC68000, MC68008, and MC68010 implementations allow long-word transfers on oddword boundaries but force exceptions if word or long-word operand transfers are attempted at odd-byte addresses. Although the MC68020/EC020 does not enforce any alignment restrictions for data operands (including PC relative data addresses), some performance degradation occurs when additional bus cycles are required for long-word or word operands that are misaligned. For maximum performance, data items should be aligned on their natural boundaries. All instruction words and extension words must reside on word boundaries. Attempting to prefetch an instruction word at an odd address causes an address error exception.

Figure 5-9 shows the transfer (write) of a long-word operand to an odd address in wordorganized memory, which requires three bus cycles. For the first cycle, SIZ1 and SIZ0 specify a long-word transfer, and A2–A0 = 001. Since the port width is 16 bits, only the first byte of the long word is transferred. The slave device latches the byte and acknowledges the data transfer, indicating that the port is 16 bits wide. When the processor starts the second cycle, SIZ1 and SIZ0 specify that three bytes remain to be transferred with A2–A0 = 010. The next two bytes are transferred during this cycle. The processor then initiates the third cycle, with SIZ1 and SIZ0 indicating one byte remaining to be transferred with A2–A0 = 100. The port latches the final byte, and the operation is complete. Figure 5-10 shows the associated bus transfer signal timing. Figure 5-11 shows the equivalent operation for a data read cycle.

5-14 M68020 USER’S MANUAL MOTOROLA

Figure 5-9. Misaligned Long-Word Operand Write to Word Port Example

MOTOROLA M68020 USER’S MANUAL 5- 15

BYTE WRITE

LONG-WORD OPERAND WRITE

S0S2S4S0S2S4CLK

A31–A2

A1A0FC2–FC0

SIZ1

SIZ0

R/W

ECS

OCSASDS

DSACK1

DSACK0

DBEN

D31–D24

D23–D16

WORD WRITE

D15–D8

D7–D0S0S2S4OP0

OP0

OP1

OP2

OP1

OP2

OP1

OP2

OP3

BYTE WRITE

********

For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020.

Figure 5-10. Misaligned Long-Word Operand Write to Word Port Timing

OP0

OP1

OP2

OP3310

LONG-WORD OPERAND (REGISTER)

DATA BUS

D31

D16

WORD MEMORY

MSB

LSB

XXX

OP0

OP1

OP2

OP3

XXX

MC68020/EC020

SIZ1

SIZ0A2A1

0 0 0 0 1 1

1 0 1 0

0 A0

MEMORY CONTROL

DSACK1

DSACK0

LHLHL

MC68020/EC020

SIZ1

SIZ0A2A1

1 0 0 0 1 0 A0

MEMORY CONTROL

DSACK1

DSACK0

LHLHOP2

OP3150

WORD OPERAND

DATA BUS

D31

D16

WORD MEMORY

MSB

LSB

XXX

OP3

OP2

XXX

1 1 0 0

Figure 5-11. Misaligned Long-Word Operand Read

from Word Port Example

Figures 5-12 and 5-13 show a word transfer (write ) to an odd address in word-organized memory. This example is similar to the one shown in Figures 5-9 and 5-10 except that the operand is word sized and the transfer requires only two bus cycles. Figure 5-14 shows the equivalent operation for a data read cycle.

5-16 M68020 USER’S MANUAL MOTOROLA

1 0 1 0

Figure 5-12. Misaligned Word Operand Write to Word Port Example

MOTOROLA M68020 USER’S MANUAL 5- 17

WORD OPERAND WRITE TO A1, A0 = 01

S0S2S4S0S2S4CLK

A31–A2

A1A0FC2–FC0

SIZ1

SIZ0

R/W

ECS

OCSASDS

DSACK1

DSACK0

DBEN

D31–D24

D23–D16

WORD WRITE

D15–D8

D7–D0

OP2

OP3

OP2

OP3

BYTE WRITE

********

For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020.

Figure 5-13. Misaligned Word Operand Write to Word Port Timing

MC68020/EC020

SIZ1

SIZ0A2A1

1 0 0 0 1 0

1 0 1 0

MEMORY CONTROL

DSACK1

DSACK0

LHLHOP2

OP3150

WORD OPERAND (REGISTER)

DATA BUS

D31

D16

WORD MEMORY

MSB

LSB

XXX

OP3

OP2

XXX

MC68020/EC020

SIZ1

SIZ0A2A1

0 0 0 1 1 1 A0

MEMORY CONTROL

DSACK1

DSACK0

LLL

OP0

OP1310

LONG-WORD OPERAND

DATA BUS

D31D0LONG-WORD MEMORY

MSB

UMB

XXX

OP1

OP2

XXX

OP2

OP3

XXX

OP3

OP0

XXX

LMB

LSB

Figure 5-14. Misaligned Word Operand Read from Word Bus Example

Figures 5-15 and 5-16 show an example of a long-word transfer (write) to an odd address in long-word-organized memory. In this example, a long-word access is attempted beginning at the least significant byte of a long-word-organized memory. Only one byte can be transferred in the first bus cycle. The second bus cycle then consists of a three byte access to a long-word boundary. Since the memory is long word organized, no further bus cycles are necessary. Figure 5-17 shows the equivalent operation for a data read cycle.

5-18 M68020 USER’S MANUAL MOTOROLA

1 1 0 0

Figure 5-15. Misaligned Long-Word Operand Write

to Long-Word Port Example

MOTOROLA M68020 USER’S MANUAL 5- 19

LONG-WORD OPERAND WRITE

S0S2S4S0S2S4CLK

A31–A2

A1A0FC2–FC0

SIZ1

SIZ0

R/W

ECS

OCSASDS

DSACK1

DSACK0

DBEN

D31–D24

D23–D16

BYTE WRITE

D15–D8

D7–D0

OP0

OP1

OP0

OP1

OP2

OP3

OP1

3-BYTE WRITE

********

For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020.

Figure 5-16. Misaligned Long-Word Operand Write

to Long-Word Port Timing

MC68020/EC020

SIZ1

SIZ0A2A1

0 0 0 1 1 1

1 1 0 0

MEMORY CONTROL

DSACK1

DSACK0

LLL

OP0

OP1310

LONG-WORD OPERAND (REGISTER)

DATA BUS

D31D0LONG-WORD MEMORY

MSB

UMB

XXX

OP1

OP2

XXX

OP2

OP3

XXX

OP3

OP0

XXX

LMB

LSB

Figure 5-17. Misaligned Long-Word Operand Read

from Long-Word Port Example

5.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment

The combination of operand size, operand alignment, and port size determine the number of bus cycles required to perform a particular memory access. Table 5-6 lists the number of bus cycles required for different operand sizes to different port sizes with all possible alignment conditions for read/write cycles.

Table 5-6. Memory Alignment and Port Size

Influence on Read/Write Bus Cycles

Number of Bus Cycles

(Data Port Size = 32 Bits:16 Bits:8 Bits)

A1, A0

Operand Size 00 01 10 11

Instruction* 1:2:4 N/A N/A N/A Byte Operand 1:1:1 1:1:1 1:1:1 1:1:1 Word Operand 1:1:2 1:2:2 1:1:2 2:2:2 Long-Word Operand 1:2:4 2:3:4 2:2:4 2:3:4

*Instruction prefetches are always two words from a long-word boundary

Table 5-6 reveals that bus cycle throughput is significantly affected by port size and alignment. The MC68020/EC020 system designer and programmer should be aware of and account for these effects, particularly in time-critical applications.

5-20 M68020 USER’S MANUAL MOTOROLA

Table 5-6 demonstrates that the processor always prefetches instructions by reading a long word from a long-word address (A1, A0 = 00), regardless of port size or alignment. When the required instruction begins at an odd-word boundary, the processor attempts to fetch the entire 32 bits and loads both words into the instruction cache, if possible, although the second one is the required word. Even if the instruction access is not cached, the entire 32 bits are latched into an internal cache holding register from which the two instructions words can subsequently be referenced. Refer to Section 8 Instruction Execution Timing for a complete description of the cache holding register and pipeline operation.

5.2.4 Address, Size, and Data Bus Relationships

The data transfer examples show how the MC68020/EC020 drives data onto or receives data from the correct byte sections of the data bus. Table 5-7 shows the combinations of the SIZ1, SIZ0, A1, and A0 signals that can be used to generate byte enable signals for each of the four sections of the data bus for read and write cycles if the addressed device requires them. The port size also affects the generation of these enable signals as shown in the table. The four columns on the right correspond to the four byte enable signals. Letters B, W, and L refer to port sizes: B for 8-bit ports, W for 16-bit ports, and L for 32-bit ports. The letters B, W, and L imply that the byte enable signal should be true for that port size. A dash (—) implies that the byte enable signal does not apply.

The MC68020/EC020 always drives all sections of the data bus because, at the beginning of a write cycle, the bus controller does not know the port size.

Table 5-7 reveals that the MC68020/EC020 transfers the number of bytes specified by SIZ1, SIZ0 to or from the specified address unless the operand is misaligned or unless the number of bytes is greater than the port width. In these cases, the device transfers the greatest number of bytes possible for the port. For example, if the size is four and A1, A0 = 01, a 32-bit slave can only receive three bytes in the current bus cycle. A 16- or 8-bit slave can only receive one byte. The table defines the byte enables for all port sizes. Byte data strobes can be obtained by combining the enable signals with the DS signal. Devices residing on 8-bit ports can use the data strobe by itself since there is only one valid byte for every transfer. These enable or strobe signals select only the bytes required for write or read cycles. The other bytes are not selected, which prevents incorrect accesses in sensitive areas such as I/O.

MOTOROLA M68020 USER’S MANUAL 5- 21

Table 5-7. Data Bus Byte Enable Signals for Byte, Word, and Long-Word Ports

Data Bus Active Sections

Byte (B), Word (W) , Long-Word (L) Ports

Transfer Size SIZ1 SIZ0 A1 A0 D31–D24 D23–D16 D15–D8 D7–D0

Byte 0

Word 1

3 Bytes 1

Long Word 0

0 0 0

1 1 1

0 0 0

1 1 1

0 0 0 0

1 1 1 1

0 0 0 0

0 0 1 1

0 1 0 1

B W L

B W

B W L

B W

B W L

B W

B W L

B W

—

W L

—

W L W L

W W

W L W L

W W

W L W L

W W

— —

L L

—

L L L

—

L L L

—

— — —

— —

L L

—

L L L

L L L L

Figure 5-18 shows a logic diagram of one method for generating byte enable signals for 16- and 32-bit ports from the SIZ1, SIZ0, A1, and A0 encodings and the R/W signal.

5.2.5 Cache Interactions

The organization and requirements of the on-chip instruction cache affect the interpretation of DSACK1 and DSACK0. Since the MC68020/EC020 attempts to load all instructions into the on-chip cache, the bus may operate differently when caching is enabled. Specifically, on read cycles that terminate normally, the A1, A0, SIZ1, and SIZ0 signals do not apply.

The cache can also affect the assertion of AS and the operation of a read cycle . The search of the cache by the processor begins when the sequencer requires an instruction. At this time, the bus controller may also initiate an external bus cycle in case the requested item is not resident in the instruction cache. If an internal cache hit occurs, the external cycle aborts, and AS is not asserted.

For the MC68020, if the bus is not occupied with another read or write cycle, the bus controller asserts the ECS signal (and the OCS signal, if appropriate). It is possible to have ECS asserted on multiple consecutive clock cycles. Note that there is a minimum time specified from the negation of ECS to the next assertion of ECS (refer to Section 10 Electrical Characteristics). Instruction prefetches can occur every other clock so that if, after an aborted cycle due to an instruction cache hit, the bus controller asserts ECS on the next clock, this second cycle is for a data fetch. Note that, if the bus controller is executing other cycles, these aborted cycles due to cache hits may not be seen externally.

5-22 M68020 USER’S MANUAL MOTOROLA

SIZ0

SIZ1

R/WLDUD

LLD

LMD

UMD

UUD

UUD U L L U L

UPPER UPPER DATA (32-BIT PORT) U L L U L

= = = = = =

MOTOROLA M68020 USER’S MANUAL 5- 23

PPER MIDDLE DATA (32-BIT PORT)

OWER MIDDLE DATA (32-BIT PORT)

OWER LOWER DATA (32-BIT PORT)

PPER DATA (16-BIT PORT)

OWER DATA (16-BIT PORT)

Figure 5-18. Byte Enable Signal Generation for 16- and 32-Bit Ports

5.2.6 Bus Operation

DSACK1/DSACK0

The MC68020/EC020 bus is used in an asynchronous manner allowing external devices to operate at clock frequencies different from the MC68020/EC020 clock. Bus operation uses the handshake lines ( AS, DS , DSACK0, DSACK1, BERR , and HALT) to control data transfers. AS signals the start of a bus cycle, and DS is used as a condition for valid data on a write cycle. Decoding SIZ1, SIZ0, A1, and A0 provides byte enable signals that select the active portion of the data bus. The slave device (memory or peripheral) then responds by placing the requested data on the correct portion of the data bus for a read cycle or latching the data on a write cycle and by asserting the DSACK0/DSACK1 combination that corresponds to the port size to terminate the cycle. If no slave responds or the access is invalid, external control logic asserts BERR to abort or BERR and HALT to retry the bus cycle.

DSACK1/ DSACK0 can be asserted before the data from a slave device is valid on a read cycle. The length of time that DSACK1/DSACK0 may precede data is given by parameter #31, and it must be met in any asynchronous system to ensure that valid data is latched into the processor. (Refer to Section 10 Electrical Characteristics for timing parameters.) Note that no maximum time is specified from the assertion of AS to the assertion of DSACK1/DSACK0. Although the processor can transfer data in a minimum of three clock cycles when the cycle is terminated with DSACK1/DSACK0, the processor inserts wait cycles in clock period increments until DSACK1/DSACK0 is recognized.

The BERR and/or HALT signals can be asserted after DSACK1/DSACK0 is asserted.

BERR and/or HALT must be asserted within the time given (parameter #48), after DSACK1/DSACK0 is asserted in any asynchronous system. If this maximum delay time is

violated, the processor may exhibit erratic behavior.

5.2.7 Synchronous Operation with

Although cycles terminated with DSACK1/DSACK0 are classified as asynchronous, cycles terminated with DSACK1/DSACK0 can also operate synchronously in that signals are interpreted relative to clock edges. The devices that use these synchronous cycles must synchronize the responses to the MC68020/EC020 clock. Since these devices terminate bus cycles with DSACK1/DSACK0, the dynamic bus sizing capabilities of the MC68020/EC020 are available. In addition, the minimum cycle time for these synchronous cycles is three clocks.

To support systems that use the system clock to generate DSACK1/DSACK0 and other asynchronous inputs, the asynchronous input setup time (parameter #47A) and the asynchronous input hold time (parameter #47B) are provided in Section 10 Electrical Characteristics . (Note: although a misnomer, these “asynchronous” parameters are the setup and hold times for synchronous operation.) If the setup and hold times are met for the assertion or negation of a signal, such as DSACK1/ DSACK0, the processor can be guaranteed to recognize that signal level on that specific falling edge of the system clock. If the assertion of DSACK1/DSACK0 is recognized on a particular falling edge of the clock, valid data is latched into the processor (for a read cycle) on the next falling clock edge provided the data meets the data setup time (parameter #27). In this case, parameter #31

5-24 M68020 USER’S MANUAL MOTOROLA

for asynchronous operation can be ignored. All timing parameters referred to are described in Section 10 Electrical Characteristics. If a system asserts DSACK1/DSACK0 for the required window around the falling edge of state 2 and obeys the proper bus protocol by maintaining DSACK1/ DSACK0 (and/or BERR/HALT) until and throughout the clock edge that negates AS (with the appropriate asynchronous input hold time specified by parameter #47B), no wait states are inserted. The bus cycle runs at its maximum speed of three clocks per cycle for bus cycles terminated with DSACK1/DSACK0.

To ensure proper operation in a synchronous system when BERR or BERR/ HALT is asserted after DSACK1/DSACK0, BERR (and HALT) must meet the appropriate setup time (parameter #27A) prior to the falling clock edge one clock cycle after DSACK1/DSACK0 is recognized. This setup time is critical, and the MC68020/EC020 may exhibit erratic behavior if it is violated.

When operating synchronously, the data-in setup (parameter #27) and hold (parameter #30) times for synchronous cycles may be used instead of the timing requirements for data relative to the DS signal.

5.3 DATA TRANSFER CYCLES

The transfer of data between the processor and other devices involves the following signals:

• Address Bus (A31–A0 for the MC68020) (A23–A0 for the MC68EC020)

• Data Bus (D31–D0)

• Control Signals

The address and data buses are both parallel, nonmultiplexed buses. The bus master moves data on the bus by issuing control signals, and the bus uses a handshake protocol to ensure correct movement of the data. In all bus cycles, the bus master is responsible for de-skewing all signals it issues at both the start and end of the cycle. In addition, the bus master is responsible for de-skewing DSACK1/DSACK0, D31–D0, BERR, HALT, and, for the MC68020, DBEN from the slave devices. The following paragraphs define read, write, and read-modify-write cycle operations.

Each of the bus cycles is defined as a succession of states. These states apply to the bus operation and are different from the processor states described in Section 2 Processing States. The clock cycles used in the descriptions and timing diagrams of data transfer cycles are independent of the clock frequency. Bus operations are described in terms of external bus states.

MOTOROLA M68020 USER’S MANUAL 5- 25

5.3.1 Read Cycle

PROCESSOR

ADDRESS DEVICE

1) ASSERT ECS/OCS FOR ONE-HALF CLOCK 2 3 4 5 6 7 8

ACQUIRE DATA

1) LATCH DATA 2

START NEXT CYCLE

PRESENT DATA

1) DECODE ADDRESS 2 3

TERMINATE CYCLE

1) REMOVE DATA FROM D31–D0 2

EXTERNAL DEVICE

***

During a read cycle, the processor receives data from a memory, coprocessor, or peripheral device. If the instruction specifies a long-word operation, the MC68020/EC020 attempts to read four bytes at once. For a word operation, it attempts to read two bytes at once and for a byte operation, one byte. For some operations, the processor requests a three-byte transfer. The processor properly positions each byte internally. The section of the data bus from which each byte is read depends on the operand size, A1–A0, and the port size. Refer to 5.2.1 Dynamic Bus Sizing and 5.2.2 Misaligned Operands for more information on dynamic bus sizing and misaligned operands.

Figure 5-19 is a flowchart of a long-word read cycle. Figure 5-20 is a flowchart of a byte read cycle. Figures 5-21–5-23 are read cycle timing diagrams in terms of clock periods. Figure 5-21 corresponds to byte and word read cycles from a 32-bit port. Figure 5-22 corresponds to a long-word read cycle from an 8-bit port. Figure 5-23 also applies to a long-word read cycle, but from 16- and 32-bit ports.

) SET R/W TO READ ) DRIVE ADDRESS ON A31–A0 ) DRIVE FUNCTION CODE ON FC2–FC0 ) DRIVE SIZ1, SIZ0 (FOUR BYTES) ) ASSERT AS ) ASSERT DS ) ASSERT DBEN

) NEGATE AS AND D ) NEGATE DBEN

This step does not apply to the MC68EC020. For the MC68EC020, A23–A0.

Figure 5-19. Long-Word Read Cycle Flowchart

) PLACE DATA ON D31–D0 ) ASSERT DSACK1/DSACK0

) NEGATE DSACK1/DSACK0

5-26 M68020 USER’S MANUAL MOTOROLA

ACQUIRE DATA

1) LATCH DATA 2

START NEXT CYCLE

PRESENT DATA

1) DECODE ADDRESS 2

)

TERMINATE CYCLE

1) REMOVE DATA FROM D31–D0 2

EXTERNAL DEVICE

PROCESSOR

ADDRESS DEVICE

1) ASSERT ECS/OCS FOR ONE-HALF CLOCK 2

) SET R/W TO READ

3 4 5 6 7 8

*****

) DRIVE ADDRESS ON A31–A0 ) DRIVE FUNCTION CODE ON FC2–FC0 ) DRIVE SIZ1, SIZ0 (FOUR BYTES) ) ASSERT AS ) ASSERT DS ) ASSERT DBEN

) NEGATE AS AND D ) NEGATE DBEN

This step does not apply to the MC68EC020. For the MC68EC020, A23–A0.

) PLACE DATA ON D31–D24 OR D23–D16 OR D15–D8 OR D7–D0 (BASED ON A1, A0, AND BUS WIDTH

) ASSERT DSACK1/DSACK0

) NEGATE DSACK1/DSACK0

MOTOROLA M68020 USER’S MANUAL 5- 27

Figure 5-20. Byte Read Cycle Flowchart

WORD READ

S0S2S4S0S2S4CLK

A31–A2

A1A0FC2–FC0

SIZ1

SIZ0

R/W

ECS

OCSASDS

DSACK1

DSACK0

DBEN

D31–D24

D23–D16

BYTE READ

D15–D8

D7–D0S0S2S4OP2

OP3

WORD

BYTE

BYTE READ

********

Figure 5-21. Byte and Word Read Cycles—32-Bit Port

5-28 M68020 USER’S MANUAL MOTOROLA

BYTE READ

A31–A2

A1A0FC2–FC0

SIZ1

SIZ0

R/W

ECS

OCSASDS

DSACK1

DSACK0

DBEN

D31–D24

D23–D16

D15–D8

D7–D0

OP0

OP1

OP3

LONG WORD

3-BYTE

BYTE READ

CLK

WORD

BYTE

OP2

BYTE READ

LONG-WORD OPERAND READ FROM 8-BIT PORT

S0S2S4S0S2S4S0S2S4S0S2

********

For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020.

MOTOROLA M68020 USER’S MANUAL 5- 29

Figure 5-22. Long-Word Read—8-Bit Port

WORD READ

S0S2S4S0S2S4CLK

A31–A2

A1A0FC2–FC0

SIZ1

SIZ0

R/W

ECS

OCSASDS

DSACK1

DSACK0

DBEN

D31–D24

D23–D16

WORD READ

D15–D8

D7–D0S0S2S4OP0

OP1

OP3

LONG WORD

WORD

LONG-WORD READ

OP2

OP1

OP0

OP2

LONG WORD

LONG-WORD OPERAND READ FROM 16-BIT PORT

********

For the MC68EC020, A23–A2.

This signal does not apply to the MC68EC020.

5-30 M68020 USER’S MANUAL MOTOROLA

FROM 32-BIT POR

Figure 5-23. Long-Word Read—16- and 32-Bit Ports

State 0

MC68020—The read cycle starts in state 0 (S0). The processor asserts ECS, indicating

the beginning of an external cycle. If the cycle is the first external cycle of a read operation, OCS is asserted simultaneously. During S0, the processor places a valid address on A31–A0 and valid function codes on FC2–FC0. The function codes select the address space for the cycle. The processor drives R/W high for a read cycle and negates DBEN to disable the data buffers. SIZ0 and SIZ1 become valid, indicating the number of bytes requested to be transferred.

MC68EC020—The read cycle starts in S0. During S0, the processor places a valid

address on A23–A0 and valid function codes on FC2–FC0. The function codes select the address space for the cycle. The processor drives R/ W high for a read cycle. SIZ0 and SIZ1 become valid, indicating the number of bytes requested to be transferred.

State 1

MC68020—One-half clock later in state 1 (S1), the processor asserts AS, indicating that

the address on the address bus is valid. The processor also asserts DS during S1. In addition, the ECS (and OCS, if asserted) signal is negated during S1.

MC68EC020—One-half clock later in S1, the processor asserts AS, indicating that the

address on the address bus is valid. The processor also asserts DS during S1.

State 2

MC68020—During state 2 (S2), the processor asserts DBEN to enable external data

buffers. The selected device uses R/W, SIZ1–SIZ0, A1–A0, and DS to place its information on the data bus. Any or all of the bytes (D31–D24, D23–D16, D15–D8, and D7–D0) are selected by SIZ1–SIZ0 and A1–A0. Concurrently, the selected device asserts DSACK1/DSACK0.

MC68EC020—During S2, the selected device uses R/W, SIZ1–SIZ0, A1–A0, and DS to

place its information on the data bus. Any or all of the bytes (D31–D24, D23–D16, D15–D8, and D7–D0) are selected by SIZ1–SIZ0 and A1–A0. Concurrently, the selected device asserts DSACK1/DSACK0.

State 3

MC68020/EC020—As long as at least one of the DSACK1/DSACK0 signals is

recognized by the end of S2 (meeting the asynchronous input setup time requirement), data is latched on the next falling edge of the clock, and the cycle terminates. If DSACK1/DSACK0 is not recognized by the start of state 3 (S3), the processor inserts wait states instead of proceeding to states 4 and 5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the processor continues to sample the DSACK1/DSACK0 signals on the falling edges of the clock until an assertion is recognized.

MOTOROLA M68020 USER’S MANUAL 5- 31

State 4

MC68020/EC020—At the end of state 4 (S4), the processor latches the incoming data.

State 5

MC68020—The processor negates AS, DS, and DBEN during state 5 (S5). It holds the

address valid during S5 to provide address hold time for memory systems. R/W, SIZ1– SIZ0, and FC2–FC0 also remain valid throughout S5.

The external device keeps its data and DSACK1/DSACK0 signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and negate DSACK1/DSACK0 within approximately one clock period after sensing the negation of AS or DS . DSACK1/DSACK0 signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle.

MC68EC020—The processor negates AS and DS during state S5. It holds the address

valid during S5 to provide address hold time for memory systems. R/W, SIZ1, SIZ0, and FC2–FC0 also remain valid throughout S5.

5-32 M68020 USER’S MANUAL MOTOROLA

5.3.2 Write Cycle

1) ASSERT ECS/OCS FOR ONE-HALF CLOCK 2 3 4 5 6 7 8 9

1) NEGATE AS AND DS 2 3

EXTERNAL DEVICE

PROCESSOR

1) NEGATE DSACK1/DSACK0

TERMINATE CYCLE

ACCEPT DATA

1) DECODE ADDRESS 2 3

ADDRESS DEVICE

TERMINATE OUTPUT TRANSFER

START NEXT CYCLE

*****

During a write cycle, the processor transfers data to memory or a peripheral device. Figure 5-24 is a flowchart of a write cycle operation for a long-word transfer. Figures 5-25– 5-28 are write cycle timing diagrams in terms of clock periods. Figure 5-25 shows two write cycles (between two read cycles with no idle time in between) for a 32-bit port. Figure 5-26 shows byte and word write cycles to a 32-bit port. Figure 5-27 shows a long word write cycle to an 8-bit port. Figure 5-28 shows a long-word write cycle to a 16-bit port.

) DRIVE ADDRESS ON A31–A0 ) DRIVE FUNCTION CODES ON FC2–FC0 ) DRIVE SIZ1, SIZ0 (FOUR BYTES) ) SET R/W TO WRITE ) ASSERT AS ) ASSERT DBEN ) DRIVE DATA LINES D31–D0 ) ASSERT DS

) STORE DATA FROM D31–D0 ) ASSERT DSACK1/DSACK0

) REMOVE DATA FROM D31–D0 ) NEGATE DBEN

This step does not apply to the MC68EC020. For the MC68EC020, A23–A0.

Figure 5-24. Write Cycle Flowchart

MOTOROLA M68020 USER’S MANUAL 5- 33

5-34 M68020 USER’S MANUAL MOTOROLA

WRITE

A31–A2

A1A0FC2–FC0

SIZ1

SIZ0

R/W

ECS

OCSASDS

DSACK1

DSACK0

DBEN

D31–D0

LONG WORD

CLK

WRITE

BYTE READ

S0S2S4S0S2S4S0S2S4S0S2Sw SwS4READ WITH WAIT STATES

********

For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020.

Figure 5-25. Read-Write-Read Cycles—32-Bit Port

WORD WRITE

S0S2S4S0S2S4CLK

A31-A2

A1A0FC2–FC0

SIZ1

SIZ0

R/W

ECS

OCSASDS

DSACK1

DSACK0

DBEN

D31–D24

D23–D16

BYTE WRITE

D15–D8

D7–D0S0S2S4OP2

OP3

WORD

OP3

BYTE

OP2

OP3

BYTE WRITE

********

For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020.

Figure 5-26. Byte and Word Write Cycles—32-Bit Port

MOTOROLA M68020 USER’S MANUAL 5- 35

BYTE WRITE

A31–A2

A1A0FC2–FC0

SIZ1

SIZ0

R/W

ECS

OCSASDS

DSACK1

DSACK0

DBEN

D31–D24

D23–D16

D15–D8

D7–D0

LONG WORD

3-BYTE

BYTE WRITE

CLK

WORD

BYTE

BYTE WRITE

LONG-WORD OPERAND WRITE TO 8-BIT PORT

S0S2S4S0S2S4S0S2S4S0S2S4OP0

OP3

OP2

OP1

OP3

OP1

OP2

OP3

OP2

OP3

********

For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020.

5-36 M68020 USER’S MANUAL MOTOROLA

Figure 5-27. Long-Word Operand Write—8-Bit Port

WORD WRITE

S0S2S4S0S2S4CLK

A31–A2

A1A0FC2–FC0

SIZ1

SIZ0

R/W

ECS

OCSASDS

DSACK1

DSACK0

DBEN

D31–D24

D23–D16

WORD WRITE

D15–D8

D7–D0S0S2S4OP0

OP1

OP3

LONG WORD

OP2

OP1

OP0

OP2

WORD

OP2

OP3

OP2

LONG-WORD WRITE LONG-WORD OPERAND WRITE TO 16-BIT PORT

********

For the MC68EC020, A23–A2.

LONG WORD

This signal does not apply to the MC68EC020.

MOTOROLA M68020 USER’S MANUAL 5- 37

TO 32-BIT PORT

Figure 5-28. Long-Word Operand Write—16-Bit Port

State 0

MC68020—The write cycle starts in S0. The processor negates ECS, indicating the

beginning of an external cycle. If the cycle is the first external cycle of a write operation, OCS is asserted simultaneously. During S0, the processor places a valid address on A31–A0 and valid function codes on FC2–FC0. The function codes select the address space for the cycle. The processor drives R/ W low for a write cycle. SIZ1– SIZ0 become valid, indicating the number of bytes to be transferred.

MC68EC020—The write cycle starts in S0. During S0, the processor places a valid

address on A23–A0 and valid function codes on FC2–FC0. The function codes select the address space for the cycle. The processor drives R/ W low for a write cycle. SIZ1, SIZ0 become valid, indicating the number of bytes to be transferred.

State 1

MC68020—One-half clock later in S1, the processor asserts AS, indicating that the

address on the address bus is valid. The processor also asserts DBEN during S1, which can enable external data buffers. In addition, the ECS (and OCS , if asserted) signal is negated during S1.

MC68EC020—One-half clock later in S1, the processor asserts AS, indicating that the

address on the address bus is valid.

State 2

MC68020/EC020—During S2, the processor places the data to be written onto D31–D0.

At the end of S2, the processor samples DSACK1/DSACK0.

State 3

MC68020/EC020—The processor asserts DS during S3, indicating that the data on the

data bus is stable. As long as at least one of the DSACK1/DSACK0 signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACK1/DSACK0 is not recognized by the start of S3, the processor inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the processor continues to sample the DSACK1/DSACK0 signals on the falling edges of the clock until one is recognized.

The external device uses R/W, DS , SIZ1, SIZ0, A1, and A0 to latch data from the appropriate byte(s) of the data bus (D31–D24, D23–D16, D15–D8, and D7–D0). SIZ1, SIZ0, A1, and A0 select the bytes of the data bus. If it has not already done so, the device asserts DSACK1/DSACK0 to signal that it has successfully stored the data.

5-38 M68020 USER’S MANUAL MOTOROLA

State 4

MC68020/EC020—The processor issues no new control signals during S4.

State 5

MC68020—The processor negates AS and DS during S5. It holds the address and data

valid during S5 to provide address hold time for memory systems. R/W, SIZ1, SIZ0, FC2–FC0, and DBEN also remain valid throughout S5.

The external device must keep DSACK1/DSACK0 asserted until it detects the negation of AS or DS (whichever it detects first). The device must negate DSACK1/DSACK0 within approximately one clock period after sensing the negation of AS or DS. DSACK1/DSACK0 signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle.

MC68EC020—The processor negates AS and DS during S5. It holds the address and

data valid during S5 to provide address hold time for memory systems. R/W, SIZ1, SIZ0, and FC2–FC0 also remain valid throughout S5.

5.3.3 Read-Modify-Write Cycle

The read-modify-write cycle performs a read, conditionally modifies the data in the arithmetic logic unit, and may write the data out to memory. In the MC68020/EC020, this operation is indivisible, providing semaphore capabilities for multiprocessor systems. During the entire read-modify-write sequence, the MC68020/EC020 asserts RMC to indicate that an indivisible operation is occurring. The MC68020/EC020 does not issue a BG signal in response to a BR signal during this operation.

The TAS , CAS, and CAS2 instructions are the only MC68020/EC020 instructions that utilize read-modify-write operations. Depending on the compare results of the CAS and CAS2 instructions, the write cycle(s) may not occur.

Figure 5-29 is a flowchart of the read-modify-write cycle operation. Figure 5-30 is an example timing diagram of a TAS instruction specified in terms of clock periods.

MOTOROLA M68020 USER’S MANUAL 5- 39

LOCK BUS

1) ASSERT RMC

ADDRESS DEVICE

1) ASSERT ECS/OCS FOR ONE-HALF CLOCK 2

) SET R/W TO READ

3 4 5 6 7 8

ACQUIRE DATA

1) LATCH DATA 2 3 4

START OUTPUT TRANSFER

1) ASSERT ECS/OCS FOR ONE-HALF CLOCK 2

) 3 4 5 6 7 8

TERMINATE OUTPUT TRANSFER

1) NEGATE AS AND DS 2 3

UNLOCK BUS

1) NEGATE RMC

START NEXT CYCLE

PRESENT DATA

1) DECODE ADDRESS 2 3

TERMINATE CYCLE

1) REMOVE DATA FROM D31–D0 2

ACCEPT DATA

1) DECODE ADDRESS 2 3

TERMINATE CYCLE

IF CAS2 INSTRUCTION

D ;

CB1) NEGATE DSACK1/DSACK0

IF CAS2 INSTRUCTION

EDPROCESSOR

EXTERNAL DEVICE

************

) DRIVE ADDRESS ON A31–A0 ) DRIVE FUNCTION CODES ON FC2–FC0 ) DRIVE SIZ1, SIZ0 ) ASSERT AS ) ASSERT DS ) ASSERT DBEN

) PLACE DATA ON D31–D0 ) ASSERT DSACK1/DSACK0

) NEGATE AS AND DS ) NEGATE DBEN ) START DATA MODIFICATIO

) DRIVE ADDRESS ON A31–A0 (IF DIFFERENT ) DRIVE SIZ1, SIZ0 ) SET R/W TO WRITE ) ASSERT AS ) ASSERT DBEN ) PLACE DATA ON D31–D0 ) ASSERT DS

) REMOVE DATA FROM D31–D0 ) NEGATE DBEN

ND ONLY ONE OPERAN

READ, THEN GO TO A

IF OPERANDS DO NOT

MATCH, THEN GO TO

C ; ELSE GO TO B

) NEGATE DSACK1/DSACK0

) STORE DATA FROM D31–D0 ) ASSERT DSACK1/DSACK0

ND ONLY ONE OPERAND

WRITTEN, THEN GO TO

D ; ELSE GO TO E

This step does not apply to the MC68EC020. For the MC68EC020, A23–A0.

5-40 M68020 USER’S MANUAL MOTOROLA

Figure 5-29. Read-Modify-Write Cycle Flowchart

INDIVISIBLE CYCLE

NEXT CYCLE

CLK

A31–A2

FC2–FC0

SIZ1

R/W

DSACK0

DBEN

D31–D24

SIZ0

DSACK1

S0S2S4SiS6S8S10

D7–D0

D23–D16

RMC

ECS

OP3

BERR

HALT

D15–8

S11

OCS

For the MC68EC020, A23–A2. This signal does not apply to the MC68EC020.

Figure 5-30. Byte Read-Modify-Write Cycle—32-Bit Port (TAS Instruction)

MOTOROLA M68020 USER’S MANUAL 5- 41

State 0

MC68020—The processor asserts ECS and OCS in S0 to indicate the beginning of an

external operand cycle. The processor also asserts RMC in S0 to identify a readmodify-write cycle. The processor places a valid address on A31–A0 and valid function codes on FC2–FC0. The function codes select the address space for the operation. SIZ1, SIZ0 become valid in S0 to indicate the operand size. The processor drives R/W high for the read cycle.

MC68EC020—The processor asserts RMC in S0 to identify a read-modify-write cycle.

The processor places a valid address on A23–A0 and valid function codes on FC2– FC0. The function codes select the address space for the operation. SIZ1–SIZ0 become valid in S0 to indicate the operand size. The processor drives R/W high for the read cycle.

State 1

MC68020—One-half clock later in S1, the processor asserts AS to indicate that the

address on the address bus is valid. The processor also asserts DS during S1. In addition, the ECS (and OCS, if asserted) signal is negated during S1.

MC68EC020—One-half clock later in S1, the processor asserts AS to indicate that the

address on the address bus is valid. The processor also asserts DS during S1.

State 2

MC68020—During S2, the processor asserts DBEN to enable external data buffers. The

selected device uses R/W, SIZ1, SIZ0, A1, A0, and DS to place information on the data bus. Any or all of the bytes (D31–D24, D23–D16, D15–D8, and D7–D0) are selected by SIZ1, SIZ0, A1, and A0. Concurrently, the selected device may assert the DSACK1/DSACK0 signals.

MC68EC020—During S2, the selected device uses R/W, SIZ1, SIZ0, A1, A0, and DS to

place information on the data bus. Any or all of the bytes (D31–D24, D23–D16, D15– D8, and D7–D0) are selected by SIZ1, SIZ0, A1, and A0. Concurrently, the selected device may assert the DSACK1/DSACK0 signals.

State 3

MC68020/EC020—As long as at least one of the DSACK1/DSACK0 signals is

recognized by the end of S2 (meeting the asynchronous input setup time requirement), data is latched on the next falling edge of the clock, and the cycle terminates. If DSACK1/DSACK0 is not recognized by the start of S3, the processor inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK0 and DSACK1 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the processor continues to sample the DSACK1/DSACK0 signals on the falling edges of the clock until one is recognized.

State 4

MC68020/EC020—At the end of S4, the processor latches the incoming data.

5-42 M68020 USER’S MANUAL MOTOROLA

State 5

MC68020—The processor negates AS, DS , and DBEN during S5. If more than one read

cycle is required to read in the operand(s), S0–S5 are repeated for each read cycle. When the read cycle(s) are complete, the processor holds the address, R/W, and FC2–FC0 valid in preparation for the write portion of the cycle.

The external device keeps its data and DSACK1/DSACK0 signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove the data and negate DSACK1/DSACK0 within approximately one clock period after sensing the negation of AS or DS . DSACK1/DSACK0 signals that remain asserted beyond this limit may be prematurely detected for the next portion of the operation.

MC68EC020—The processor negates AS, DS , and DBEN during S5. If more than one

read cycle is required to read in the operand(s), S0–S5 are repeated for each read cycle. When the read cycle(s) is complete, the processor holds the address, R/ W, and FC2–FC0 valid in preparation for the write portion of the cycle.

Idle States

MC68020/EC020—The processor does not assert any new control signals during the

idle states, but it may internally begin the modify portion of the cycle at this time. S6– S11 are omitted if no write cycle is required. If a write cycle is required, the R/W signal remains in the read mode until S6 to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not driven until S8.

State 6

MC68020—The processor asserts ECS and OCS in S6 to indicate that another external

cycle is beginning. The processor drives R/ W low for a write cycle. Depending on the write operation to be performed, the address lines may change during S6.

MC68EC020—During S6, the processor drives R/W low for a write cycle. Depending on

the write operation to be performed, the address lines may change during S6.

State 7

MC68020—During S7, the processor asserts AS, indicating that the address on the

address bus is valid. The processor also asserts DBEN, which can be used to enable data buffers. In addition, ECS (and OCS, if asserted) is negated during S7.

MC68EC020—During S7, the processor asserts AS, indicating that the address on the

address bus is valid.

State 8

MC68020/EC020—During S8, the processor places the data to be written onto the data

bus.

MOTOROLA M68020 USER’S MANUAL 5- 43

State 9

MC68020/EC020—The processor asserts DS during S9, indicating that the data on the

data bus is stable. As long as at least one of the DSACK1/DSACK0 signals is recognized by the end of S8 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACK1/DSACK0 is not recognized by the start of S9, the processor inserts wait states instead of proceeding to S10 and S11. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S8. If wait states are added, the processor continues to sample DSACK1/DSACK0 signals on the falling edges of the clock until one is recognized.

The external device uses R/W, DS , SIZ1, SIZ0, A1, and A0 to latch data from the appropriate section(s) of the data bus (D31–D24, D23–D16, D15–D8, and D7–D0). SIZ1, SIZ0, A1, and A0 select the data bus sections. If it has not already done so, the device asserts DSACK1/DSACK0 when it has successfully stored the data.

State 10

MC68020/EC020—The processor issues no new control signals during S10.

State 11

MC68020/EC020—The processor negates AS and DS during S11. It holds the address

and data valid during S11 to provide address hold time for memory systems. R/ W and FC2–FC0 also remain valid throughout S11.

If more than one write cycle is required, S6–S11 are repeated for each write cycle. The external device keeps DSACK1/DSACK0 asserted until it detects the negation of

AS or DS (whichever it detects first). The device must remove its data and negate DSACK1/DSACK0 within approximately one clock period after sensing the negation of AS or DS .

5.4 CPU SPACE CYCLES

FC2–FC0 select user and supervisor program and data areas as listed in Table 2-1. The area selected by FC2–FC0 = 111 is classified as the CPU space. The interrupt acknowledge, breakpoint acknowledge, module operations, and coprocessor communication cycles described in the following paragraphs utilize CPU space.

The CPU space type is encoded on A19–A16 during a CPU space operation and indicates the function that the processor is performing. On the MC68020/EC020, four of the encodings are implemented as shown in Figure 5-31. All unused values are reserved by Motorola for future use.

5-44 M68020 USER’S MANUAL MOTOROLA

1 1 1

BREAKPOINT

ACCESS LEVEL

COPROCESSOR

INTERRUPT

1 1 1

LEVEL10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

CpID

0 0 0 0 0 0 0 0

CP REG

1513403103131

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0

60MMU REG

BKPT #

0 031314200 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

19162320

FUNCTION

CODE

ADDRESS BUS

CPU SPACE T

242015517191620151216192019205415

CKNOWLEDG

CONTRO

COMMUNICATIO

CKNOWLEDG

YPE FIELD

Figure 5-31. MC68020/EC020 CPU Space Address Encoding

5.4.1 Interrupt Acknowledge Bus Cycles

When a peripheral device signals the processor (with the IPL2– IPL0 signals) that the device requires service and when the internally synchronized value on these signals indicates a higher priority than the interrupt mask in the status register (or that a transition has occurred in the case of a level 7 interrupt), the processor makes the interrupt a pending interrupt. Refer to Section 6 Exception Processing for details on the recognition of interrupts.

The MC68020/EC020 takes an interrupt exception for a pending interrupt within one instruction boundary (after processing any other pending exception with a higher priority). The following paragraphs describe the various kinds of interrupt acknowledge bus cycles that can be executed as part of interrupt exception processing.

5.4.1.1 INTERRUPT ACKNOWLEDGE CYCLE—TERMINATED NORMALLY . When the MC68020/EC020 processes an interrupt exception, it performs an interrupt acknowledge cycle to obtain the number of the vector that contains the starting location of the interrupt service routine.

Some interrupting devices have programmable vector registers that contain the interrupt vectors for the routines they use. The following paragraphs describe the interrupt acknowledge cycle for these devices. Other interrupting conditions or devices cannot supply a vector number and use the autovector cycle described in 5.4.1.2 Autovector Interrupt Acknowledge Cycle.

MOTOROLA M68020 USER’S MANUAL 5- 45

The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in

REQUEST INTERRUPT

INTERRUPTING DEVICE

PROCESSOR

1) PLACE VECTOR NUMBER ON LEAST

PROVIDE VECTOR INFORMATION

ACKNOWLEDGE INTERRUPT

1) INTERRUPT PENDING CONDITION (IPEND FOR M T 2 3 4

5 6 7

ACQUIRE VECTOR NUMBER

1) LATCH VECTOR NUMBER 2

CONTINUE INTERRUPT EXCEPTION PROCESSING

RELEASE

1) REMOVE VECTOR NUMBER FROM DATA BUS 2

5.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences are:

1. FC2–FC0 are set 111 for CPU address space.

2. A3, A2, and A1 are set to the interrupt request level (the inverted values of IPL2, IPL1, and IPL0, respectively).

3. The CPU space type field (A19–A16) is set to 1111, the interrupt acknowledge code.

4. Other address signals (A31–A20, A15–A4, and A0 for the MC68020; A23–A20, A15–A4, and A0 for the MC68EC020) are set to one.

The responding device places the vector number on the data bus during the interrupt acknowledge cycle. Beyond this, the cycle is terminated normally with DSACK1/DSACK0. Figure 5-32 is the flowchart of the interrupt acknowledge cycle.

Figure 5-33 shows the timing for an interrupt acknowledge cycle terminated with DSACK1/DSACK0.

C68020) RECOGNIZED BY CURRENT INSTRUCION—WAIT FOR INSTRUCTION BOUNDARY. ) SET R/W TO READ ) SET FUNCTION CODE TO CPU SPACE ) PLACE INTERRUPT LEVEL ON A1, A2, AND A3.

TYPE FIELD = IACK

) SET SIZE TO BYTE ) NEGATE IPEND ) ASSERT AS AND DS

) NEGATE AS AND DS

This step does not apply to the MC68EC020.

Figure 5-32. Interrupt Acknowledge Cycle Flowchart

SIGNIFICANT BYTE OF DATA PORT (DEPENDS ON PORT SIZE)

) ASSERT DSACK1/DSACK0 OR ASSERT AVEC FOR AUTOMATIC GENERA TION OF VECTOR NUMBER

) NEGATE DSACK1/DSACK0

5-46 M68020 USER’S MANUAL MOTOROLA

MOTOROLA M68020 USER’S MANUAL 5- 47

READ CYCLE

INTERRUPT

WRITE STACK

CLK

A31–A4

A3–A1A0FC2–FC0

SIZ1

R/W

ECS

OCSASDS

DSACK0

DBEN

D24–D31

IPL2–IPL0

SIZ0

DSACK1

S0S2S4S0S2S4S0S2INTERRUPT LEVEL

IPEND

D7–D0

D23–D16

VECTOR # FROM 8-BIT PORT

VECTOR # FROM 16-BIT PORT

VECTOR # FROM 32-BIT PORT

********

ACKNOWLEDGE

For the MC68EC020, A23–A4. This signal does not apply to the MC68EC020.

Figure 5-33. Interrupt Acknowledge Cycle Timing

5.4.1.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE . When the interrupting

device cannot supply a vector number, it requests an automatically generated vector or autovector. Instead of placing a vector number on the data bus and asserting DSACK1/DSACK0, the device asserts AVEC to terminate the cycle. The DSACK1/DSACK0 signals may not be asserted during an interrupt acknowledge cycle terminated by AVEC.

The vector number supplied in an autovector operation is derived from the interrupt level of the current interrupt. When AVEC is asserted instead of DSACK1/DSACK0 during an interrupt acknowledge cycle, the MC68020/EC020 ignores the state of the data bus and internally generates the vector number, the sum of the interrupt level plus 24 ($18). Seven distinct autovectors, which correspond to the seven levels of interrupt available with IPL2– IPL0, can be used. Figure 5-34 shows the timing for an autovector operation.

5.4.1.3 SPURIOUS INTERRUPT CYCLE. When a device does not respond to an interrupt acknowledge cycle with AVEC or DSACK1/DSACK0, the external logic typically returns BERR. In this case, the MC68020/EC020 automatically generates 24, the spurious interrupt vector number. If HALT is also asserted, the processor retries the cycle.

5-48 M68020 USER’S MANUAL MOTOROLA

READ CYCLE

INTERRUPT

WRITE STACK

CLK

A31–A4

A1–A3A0FC2–FC0

SIZ1

R/W

ECS

OCSASDS

DSACK0

DBEN

D31–D0

IPL2–IPL0

AVEC

SIZ0

DSACK1

S0S2S4S0S2S4S0S2INTERRUPT LEVEL

********

ACKNOWLEDGE

AUTOVECTORED

For the MC68EC020, A23–A4. This signal does not apply to the MC68EC020.

Figure 5-34. Autovector Operation Timing

MOTOROLA M68020 USER’S MANUAL 5- 49

5.4.2 Breakpoint Acknowledge Cycle

1) PLACE REPLACEMENT OPCODE ON DATA

1 P

PROCESSOR

1) SET R/W TO READ 2 3 4 5 6

BREAKPOINT ACKNOWLEDGE

1) PLACE LATCHED DATA IN INSTRUCTION

1) INITIATE ILLEGAL INSTRUCTION PROCESSING

SLAVE NEGATES DSACK1/DSACK0 OR BERR

EXTERNAL DEVICE

IF DSACK1/DSACK0 ASSERTED:

The breakpoint acknowledge cycle is generated by the execution of a BKPT instruction. The breakpoint acknowledge cycle allows the external hardware to provide an instruction word directly into the instruction pipeline as the program executes. This cycle accesses the CPU space with a type field of zero and provides the breakpoint number specified by the instruction on address lines A4–A2. If the external hardware terminates the cycle with DSACK1/DSACK0, the data on the bus (an instruction word) is inserted into the instruction pipe, replacing the breakpoint opcode, and is executed after the breakpoint acknowledge cycle completes. The BKPT instruction requires a word to be transferred so that if the first bus cycle accesses an 8-bit port, a second cycle is required. If the external logic terminates the breakpoint acknowledge cycle with BERR (i.e., no instruction word available), the processor takes an illegal instruction exception. Figure 5-35 is a flowchart of the breakpoint acknowledge cycle. Figure 5-36 shows the timing for a breakpoint acknowledge cycle that returns an instruction word. Figure 5-37 shows the timing for a breakpoint acknowledge cycle that signals an exception.

) SET FUNCTION CODE TO CPU SPACE ) PLACE CPU SPACE TYPE 0 ON A19–A16 ) PLACE BREAKPOINT NUMBER ON A4–A2 ) SET SIZE TO WORD ) ASSERT AS AND DS

1) LATCH DATA

2) NEGATE AS AND DS

3) GO TO A

BUS

) ASSERT DSACK1/DTACK0

) ASSERT BERR TO INITIATE EXCEPTION

ROCESSING

F BERR ASSERTED:

1) NEGATE AS AND DS

2) GO TO B A B

PIPELINE

) CONTINUE PROCESSING

Figure 5-35. Breakpoint Acknowledge Cycle Flowchart

5-50 M68020 USER’S MANUAL MOTOROLA

BREAKPOINT

READ CYCLE

CLK

A31–A20

A19–A16

A15–A2

FC2–FC0

SIZ1

R/W

ECS

OCSASDS

DSACK0

DBEN

D23–D16

SIZ0

DSACK1

S0S2S4S0S2S4S0S2D7–D0

D15–D8

BREAKPOINT NUMBER

WORD

FETCHED I E

(0000)

REAKPOINT ENCODIN

A1–A0

HALT

BERR

******

ACKNOWLEDGE

INSTRUCTION WORD

NSTRUCTION

XECUTION

Figure 5-36. Breakpoint Acknowledge Cycle Timing

MOTOROLA M68020 USER’S MANUAL 5- 51

CLK

A31–A0

FC2–FC0

R/W

ECS

OCSASDS

DSACK0

DBEN

SIZ1–SIZ0

DSACK1

S0S2S4S0S2

HALTSwSwSwS4

D31–D0

BERR

READ WITH BERR ASSERTED

INTERNAL

STACK WRITE

********

For the MC68EC020, A23–A0.

This signal does not apply to the MC68EC020.

5-52 M68020 USER’S MANUAL MOTOROLA

PROCESSING

Figure 5-37. Breakpoint Acknowledge Cycle Timing (Exception Signaled)

5.4.3 Coprocessor Communication Cycles

The MC68020/EC020 coprocessor interface provides instruction-oriented communication between the processor and as many as eight coprocessors. Coprocessor accesses use the MC68020/EC020 bus protocol except that the address bus supplies access information rather than a 32-bit address. The CPU space type field (A19–A16) for a coprocessor operation is 0010. A15–A13 contain the coprocessor identification number (CpID), and A5–A0 specify the coprocessor interface register to be accessed. The memory management unit of an MC68020/EC020 system is always identified by a CpID of zero and has an extended register select field (A7–A0) in CPU space 0001 for use by the CALLM and RTM access level checking mechanism. Refer to Section 9 Applications

Information for more details.

5.5 BUS EXCEPTION CONTROL CYCLES

The MC68020/EC020 bus architecture requires assertion of DSACK1/DSACK0 from an external device to signal that a bus cycle is complete. DSACK1/DSACK0 or AVEC is not asserted if:

• The external device does not respond,

• No interrupt vector is provided, or

• Various other application-dependent errors occur.

External circuitry can assert BERR when no device responds by asserting DSACK1/DSACK0 or AVEC within an appropriate period of time after the processor asserts AS. Assertion of BERR allows the cycle to terminate and the processor to enter exception processing for the error condition.

HALT is also used for bus exception control. HALT can be asserted by an external device for debugging purposes to cause single bus cycle operation or can be asserted in combination with BERR to cause a retry of a bus cycle in error.

To properly control termination of a bus cycle for a retry or a bus error condition, DSACK1/DSACK0, BERR, and HALT can be asserted and negated with the rising edge of the MC68020/EC020 clock. This procedure ensures that when two signals are asserted simultaneously, the required setup time (#47A) and hold time (#47B) for both of them is met for the same falling edge of the processor clock. (Refer to Section 10 Electrical Characteristics for timing requirements.) This or some equivalent precaution should be designed into the external circuitry that provides these signals.

MOTOROLA M68020 USER’S MANUAL 5- 53

Motorola MC68EC020FG16, MC68EC020FG25, MC68EC020RP16, MC68EC020RP25, MC68020RP16 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

TABLE OF CONTENTS

LIST OF ILLUSTRATIONS

LIST OF TABLES

MC68020/EC020 ACRONYM LIST

1.1 FEATURES

1.2 PROGRAMMING MODEL

1.3 DATA TYPES AND ADDRESSING MODES OVERVIEW

1.4 INSTRUCTION SET OVERVIEW

1.5 VIRTUAL MEMORY AND VIRTUAL MACHINE CONCEPTS

1.5.1 Virtual Memory

1.5.2 Virtual Machine

1.6 PIPELINED ARCHITECTURE

2.1 PRIVILEGE LEVELS

2.1.1 Supervisor Privilege Level

2.1.2 User Privilege Level

2.1.3 Changing Privilege Level

2.2 ADDRESS SPACE TYPES

2.3 EXCEPTION PROCESSING

2.3.1 Exception Vectors

2.3.2 Exception Stack Frame

3.1 SIGNAL INDEX

3.6 ASYNCHRONOUS BUS CONTROL SIGNALS

3.7 INTERRUPT CONTROL SIGNALS

3.8 BUS ARBITRATION CONTROL SIGNALS

3.9 BUS EXCEPTION CONTROL SIGNALS

3.10 EMULATOR SUPPORT SIGNAL

3.12 POWER SUPPLY CONNECTIONS

3.13 SIGNAL SUMMARY

4.1 ON-CHIP CACHE ORGANIZATION AND OPERATION

4.2 CACHE RESET

4.3 CACHE CONTROL

5.1 BUS TRANSFER SIGNALS

5.1.1 Bus Control Signals

5.1.2 Address Bus

5.1.3 Address Strobe

5.1.4 Data Bus

5.1.5 Data Strobe

5.1.6 Data Buffer Enable

5.1.7 Bus Cycle Termination Signals

5.2 DATA TRANSFER MECHANISM

5.2.1 Dynamic Bus Sizing

5.2.2 Misaligned Operands

5.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment

5.2.4 Address, Size, and Data Bus Relationships

5.2.5 Cache Interactions

5.2.6 Bus Operation

5.3 DATA TRANSFER CYCLES

5.3.1 Read Cycle

5.3.2 Write Cycle

5.3.3 Read-Modify-Write Cycle

5.4 CPU SPACE CYCLES

5.4.1 Interrupt Acknowledge Bus Cycles

5.4.2 Breakpoint Acknowledge Cycle

5.4.3 Coprocessor Communication Cycles

5.5 BUS EXCEPTION CONTROL CYCLES