Motorola MC54HC373AJ, MC74HC373ADW, MC74HC373ASD Datasheet



SEMICONDUCTOR TECHNICAL DATA

REV 7

 Motorola, Inc. 1997

3/97

     

High–Performance Silicon–Gate CMOS

The MC54/74HC373A is identical in pinout to the LS373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.

The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high–impedance state. Thus, data may be latched even when the outputs are not enabled.

The HC373A is identical in function to the HC573A which has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout.

The HC373A is the non–inverting version of the HC533A.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 186 FETs or 46.5 Equivalent Gates

LOGIC DIAGRAM

DATA

INPUTS

D0 D1 D2 D3 D4 D5 D6 D7

OUTPUT ENABLE

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

PIN 20 = V

PIN 10 = GND

NONINVERTING

OUTPUTS

LATCH ENABLE

ОООООООООО

Design Criteria

Value

Units

ОООООООООО

ООООООООО

Internal Gate Count*

ÎÎ

46.5

ОООООООООО

Internal Gate Propagation Delay

1.5

ОООООООООО

Internal Gate Power Dissipation

5.0

µW

ОООООООООО

Speed Power Product

0.0075

* Equivalent to a two–input NAND gate.



PIN ASSIGNMENT

OUTPUT

ENABLE

GND

Q1 5

LATCH ENABLE

FUNCTION TABLE

Inputs Output

Output Latch Enable Enable D Q

LHHH LHLL L L X No Change

HXXZ

X = Don’t Care Z = High Impedance

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ORDERING INFORMATION

MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW MC74HCXXXASD MC74HCXXXADT

Ceramic Plastic SOIC SSOP TSSOP

DT SUFFIX

TSSOP PACKAGE

CASE 948E–02

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

SD SUFFIX

SSOP PACKAGE

CASE 940C–03

MC54/74HC373A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

DC Input Current, per Pin

± 20

out

DC Output Current, per Pin

± 35

DC Supply Current, VCC and GND Pins

± 75

ОООООООООООО

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

SSOP or TSSOP Package†

ÎÎÎÎ

750 500 450

stg

ОООООООООООО

Storage Temperature

ÎÎÎÎ

– 65 to + 150

ОООООООООООО

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC, SSOP or TSSOP Package)

(Ceramic DIP)

ÎÎÎÎ

260 300

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C SSOP or TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

DC Supply Voltage (Referenced to GND)

2.0

6.0

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

Operating Temperature, All Package Types

– 55

+ 125

ÎÎ

tr, t

ОООООООООООО

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

0 0 0

1000

500 400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Symbol

ООООООО

Parameter

ООООООО

Test Conditions

ÎÎ

– 55 to

25_C

ÎÎ

85_C

ÎÎ

125_C

Unit

ÎÎ

ООООООО

Minimum High–Level Input Voltage

ООООООО

out

= VCC – 0.1 V

out

| v 20 µA

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

1.5

2.1

3.15

4.2

ÎÎ

1.5

2.1

3.15

4.2

ÎÎ

1.5

2.1

3.15

4.2

ÎÎ

ООООООО

Maximum Low–Level Input Voltage

ООООООО

out

= 0.1 V

out

| v 20 µA

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

0.5

0.9

1.35

1.8

ÎÎ

0.5

0.9

1.35

1.8

ÎÎ

0.5

0.9

1.35

1.8

ÎÎ

ООООООО

Minimum High–Level Output Voltage

ООООООО

Vin = V

out

| v 20 µA

ÎÎ

2.0

4.5

6.0

ÎÎ

1.9

4.4

5.9

ÎÎ

1.9

4.4

5.9

ÎÎ

1.9

4.4

5.9

ÎÎ

ООООООО

Vin = V

out

| v 2.4 mA

out

| v 6.0 mA

out

| v 7.8 mA

ÎÎ

3.0

4.5

6.0

ÎÎ

2.48

3.98

5.48

ÎÎ

2.34

3.84

5.34

ÎÎ

2.2

3.7

5.2

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

MC54/74HC373A

High–Speed CMOS Logic Data DL129 — Rev 6

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Unit

125_C

85_C

– 55 to

25_C

Test Conditions

Parameter

Symbol

ÎÎ

ООООООО

Maximum Low–Level Output Voltage

ООООООО

Vin = V

out

| v 20 µA

ÎÎ

2.0

4.5

6.0

ÎÎ

0.1

ÎÎ

0.1

ÎÎ

0.1

ÎÎÎОООООООÎООООООО

Vin = V

out

| v 2.4 mA

out

| v 6.0 mA

out

| v 7.8 mA

ÎÎ

3.0

4.5

6.0

ÎÎ

0.26

ÎÎ

0.33

ÎÎ

0.4

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

µA

ÎÎ

ООООООО

Maximum Three–State Leakage Current

ООООООО

Output in High–Impedance State Vin = VIL or V

out

= VCC or GND

ÎÎ

6.0

ÎÎ

± 0.5

ÎÎ

± 5.0

ÎÎ

± 10

µA

ÎÎ

ООООООО

Maximum Quiescent Supply Current (per Package)

ООООООО

Vin = VCC or GND I

out

= 0 µA

ÎÎ

6.0

ÎÎ

4.0

ÎÎ

160

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

= 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

ÎÎ

Symbol

ООООООООООООООО

Parameter

ÎÎ

– 55 to

25_C

ÎÎ

85_C

ÎÎ

125_C

Unit

ÎÎ

PLH

PHL

ООООООООООООООО

Maximum Propagation Delay, Input D to Q

(Figures 1 and 5)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

125

80 25 21

ÎÎ

155

110

31 26

ÎÎ

190 130

38 32

ÎÎ

PLH

PHL

ООООООООООООООО

Maximum Propagation Delay, Latch Enable to Q

(Figures 2 and 5)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

140

90 28 24

ÎÎ

175 120

35 30

ÎÎ

210 140

42 36

ÎÎ

PLZ

PHZ

ООООООООООООООО

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

150 100

30 26

ÎÎ

190 125

38 33

ÎÎ

225 150

45 38

ÎÎ

PZL

PZH

ООООООООООООООО

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

150 100

30 26

ÎÎ

190 125

38 33

ÎÎ

225 150

45 38

ÎÎ

TLH

THL

ООООООООООООООО

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

ÎÎ

2.0

3.0

4.5

6.0

ÎÎ

60 23 12 10

ÎÎ

75 27 15 13

ÎÎ

90 32 18 15

ÎÎ

ООООООООООООООО

Maximum Input Capacitance

ÎÎ

ÎÎ10ÎÎ10ÎÎ10Î

ÎÎ

out

ООООООООООООООО

Maximum Three–State Output Capacitance (Output in High–Impedance State)

ÎÎÎÎÎ15ÎÎ

ÎÎ

NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

Power Dissipation Capacitance (Per Enabled Output)*

*Used to determine the no–load dynamic power consumption: PD = CPD V

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

+ 5 hidden pages