MOTOROLA MC54HC365, MC74HC365 Technical data

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Hex 3-State Noninverting Buffer with Common Enables

High±Performance Silicon±Gate CMOS

The MC54/74HC365 is identical in pinout to the LS365. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device is a high±speed hex buffer with 3±state outputs and two common active±low Output Enables. When either of the enables is high, the buffer outputs are placed into high±impedance states. The HC365 has noninverting outputs.

•Output Drive Capability: 15 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 90 FETs or 22.5 Equivalent Gates

LOGIC DIAGRAM

	A0	2	3	Y0
	A1	4	5	Y1
	A2	6	7	Y2
	A3	10	9	Y3
	A4	12	11	Y4
	A5	14	13	Y5
OUTPUT ENABLE 1	1		PIN 16 = VCC
	15
OUTPUT ENABLE 2			PIN 8 = GND

MC54/74HC365

		J SUFFIX
	CERAMIC PACKAGE
	16	CASE 620±10
	1
		N SUFFIX
	16	PLASTIC PACKAGE
		CASE 648±08
	1
	16	DT SUFFIX
		TSSOP PACKAGE
	1	CASE 948F±01
	ORDERING INFORMATION
	MC54HCXXXJ	Ceramic
	MC74HCXXXN	Plastic
	MC74HCXXXDT	TSSOP

PIN ASSIGNMENT

OUTPUT		1	16	VCC
ENABLE 1
A0		2	15	OUTPUT
				ENABLE 2
Y0		3	14	A5
A1		4	13	Y5
Y1		5	12	A4
A2		6	11	Y4
Y2		7	10	A3
GND		8	9	Y3

FUNCTION TABLE

	Inputs		Output
Enable	Enable
1	2	A	Y
L	L	L	L
L	L	H	H
H	X	X	Z
X	H	X	Z

X = don't care

Z = high impedance

10/95

Motorola, Inc. 1995

REV 6

MC54/74HC365

MAXIMUM RATINGS*

	Symbol	Parameter	Value	Unit
	VCC	DC Supply Voltage (Referenced to GND)	± 0.5 to + 7.0	V
	Vin	DC Input Voltage (Referenced to GND)	± 1.5 to VCC + 1.5	V
	Vout	DC Output Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V
	Iin	DC Input Current, per Pin	± 20	mA
	Iout	DC Output Current, per Pin	± 35	mA
	ICC	DC Supply Current, VCC and GND Pins	± 75	mA
	PD	Power Dissipation in Still Air, Plastic or Ceramic DIP²	750	mW
		TSSOP Package²	450
	Tstg	Storage Temperature	± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds		_C
		(Plastic DIP or TSSOP Package)	260
		(Ceramic DIP)	300

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C

Ceramic DIP: ± 10 mW/_C from 100_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

					Guaranteed Limit
				VCC
					± 55 to
Symbol	Parameter	Test Conditions		V	25_C	v 85_C	v 125_C	Unit
VIH	Minimum High±Level Input	Vout = VCC ± 0.1 V		2.0	1.5	1.5	1.5	V
	Voltage	|Iout| v 20	μA	4.5	3.15	3.15	3.15
				6.0	4.2	4.2	4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V		2.0	0.3	0.3	0.3	V
	Voltage	|Iout| v 20 μA		4.5	0.9	0.9	0.9
				6.0	1.2	1.2	1.2
VOH	Minimum High±Level Output	Vin = VIH	μA	2.0	1.9	1.9	1.9	V
	Voltage	|Iout| v 20		4.5	4.4	4.4	4.4
				6.0	5.9	5.9	5.9
		Vin = VIH	|Iout| v 6.0 mA	4.5	3.98	3.84	3.70
			|Iout| v 7.8 mA	6.0	5.48	5.34	5.20
VOL	Maximum Low±Level Output	Vin = VIL	μA	2.0	0.1	0.1	0.1	V
	Voltage	|Iout| v 20		4.5	0.1	0.1	0.1
				6.0	0.1	0.1	0.1
		Vin = VIL	|Iout| v 6.0 mA	4.5	0.26	0.33	0.40
			|Iout| v 7.8 mA	6.0	0.26	0.33	0.40
Iin	Maximum Input Leakage Current	Vin = VCC or GND		6.0	± 0.1	± 1.0	± 1.0	μA

MOTOROLA

2

MC54/74HC365

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
IOZ	Maximum Three±State	Output in High±Impedance State	6.0	± 0.5	± 5.0	± 10	μA
	Leakage Current	Vin = VIL or VIH
		Vout = VCC or GND
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	8	80	160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

			Guaranteed Limit
		VCC
			± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C		Unit
tPLH,	Maximum Propagation Delay, Input A to Output Y	2.0	120	150	180		ns
tPHL	(Figures 1 and 3)	4.5	24	30	36
		6.0	20	26	31
tPLZ,	Maximum Propagation Delay, Output Enable to Output Y	2.0	220	275	330		ns
tPHZ	(Figures 2 and 4)	4.5	44	55	66
		6.0	37	47	56
tPZL,	Maximum Propagation Delay, Output Enable to Output Y	2.0	220	275	330		ns
tPZH	(Figures 2 and 4)	4.5	44	55	66
		6.0	37	47	56
tTLH,	Maximum Output Transition Time, Any Output	2.0	60	75	90		ns
tTHL	(Figures 1 and 3)	4.5	12	15	18
		6.0	10	13	15
Cin	Maximum Input Capacitance	Ð	10	10	10		pF
Cout	Maximum Three±State Output Capacitance	Ð	15	15	15		pF
	(Output in High±Impedance State)
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
			Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Buffer)*			40			pF

* Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

		SWITCHING WAVEFORMS
				50%		VCC
	tr	tf	OUTPUT ENABLE			GND
	90%		VCC	tPZL	tPLZ
INPUT A
	50%					HIGH
	10%		GND
				50%		IMPEDANCE
	tPLH	tPHL	OUTPUT Y
					10%	VOL
	90%			tPZH
OUTPUT Y	50%				tPHZ	VOH
					90%
	10%		OUTPUT Y	50%
	tTLH	tTHL				HIGH
						IMPEDANCE

Figure 1.

Figure 2.

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