Motorola MC54HC273AJ, MC74HC273AN, MC74HC273ADW, MC74HC273ADT Datasheet



ОООООООООО

SEMICONDUCTOR TECHNICAL DATA

    !     

High–Performance Silicon–Gate CMOS

The MC54/74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of eight D flip–flops with common Clock and Reset inputs. Each flip–flop is loaded with a low–to–high transition of the Clock input. Reset is asynchronous and active low.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 264 FETs or 66 Equivalent Gates

LOGIC DIAGRAM

12 15 16 19

NONINVERTING

Q4 Q5 Q6 Q7

PIN 20 = V PIN 10 = GND

OUTPUTS

DATA

INPUTS

D0 D1 D2 D3 D4 D5 D6 D7

CLOCK

RESET

3 4 7 8 13 14 17 18



J SUFFIX

ORDERING INFORMATION

MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW MC74HCXXXADT

PIN ASSIGNMENT

RESET

Q0 D0 D1

Q1 5 Q2 D2 D3 Q3

GND

CERAMIC PACKAGE

CASE 732–03

PLASTIC PACKAGE

CASE 738–03

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

TSSOP PACKAGE

CASE 948E–02

1 2

3 4

20 19

18 17

16 6 7 8 9 10

N SUFFIX

DT SUFFIX

Ceramic Plastic SOIC TSSOP

CC Q7 D7

D6 Q6

Q5 D5 D4 Q4 CLOCK

Design Criteria

Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation

ООООООООО

Speed Power Product

* Equivalent to a two–input NAND gate.

2/97

 Motorola, Inc. 1997

3–1

Value

1.5

5.0

ÎÎ

.0075

Units

ea ns

µW

FUNCTION TABLE

Inputs Output

Reset Clock D Q

LXX L HHH HLL H L X No Change H X No Change

REV 7

MC54/74HC273A

MAXIMUM RATINGS*

Symbol

DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

out

DC Input Current, per Pin

DC Output Current, per Pin

out

DC Supply Current, VCC and GND Pins

Power Dissipation in Still Air, Plastic or Ceramic DIP†

ОООООООООООО

Storage Temperature

stg

ОООООООООООО

Lead Temperature, 1 mm from Case for 10 Seconds

ОООООООООООО

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Parameter

SOIC Package†

TSSOP Package†

Plastic DIP, SOIC or TSSOP Package

(Ceramic DIP)

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 25 ± 50

750 500

ÎÎÎÎ

450

ÎÎÎÎ

– 65 to + 150

ÎÎÎÎ

260 300

ÎÎÎÎ

Unit

V V

V mA mA mA

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

) v VCC.

out

RECOMMENDED OPERATING CONDITIONS

Symbol

Vin, V

tr, t

ÎÎ

DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

ОООООООООООО

Parameter

VCC = 6.0 V

Min

2.0 0

– 55

0 0

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Symbol

ÎÎ

ООООООО

Minimum High–Level Input

ООООООО

Voltage

ООООООО

Maximum Low–Level Input

ООООООО

Voltage

ООООООО

Minimum High–Level Output Voltage

ООООООО

Parameter

Test Conditions

ООООООО

= VCC – 0.1 V

out

ООООООО

| v 20 µA

out

ООООООО

= 0.1 V

out

ООООООО

| v 20 µA

out

ООООООО

Vin = V

| v 20 µA

out

ООООООО

Vin = V

ООООООО

| v 2.4 mA

out

| v 6.0 mA

out

| v 7.8 mA

out

Max

6.0

+ 125

1000

500

400

Unit

V V

ÎÎ

2.0

ÎÎ

3.0

4.5

ÎÎ

6.0

2.0

ÎÎ

3.0

4.5

ÎÎ

6.0

2.0

4.5

ÎÎ

6.0

3.0

ÎÎ

4.5

6.0

ÎÎ

Guaranteed Limit

– 55 to

25_C

ÎÎ

1.5

2.1

3.15

ÎÎ

4.2

0.5

ÎÎ

0.9

1.35

1.8

ÎÎ

1.9

4.4

ÎÎ

5.9

ÎÎ

2.48

ÎÎ

3.98

5.48

ÎÎ

85_C

1.5

2.1

3.15

4.2

0.5

0.9

1.35

1.8

1.9

4.4

5.9

2.34

3.84

5.34

125_C

ÎÎ

1.5

ÎÎ

2.1

3.15

ÎÎ

4.2

0.5

ÎÎ

0.9

1.35

ÎÎ

1.8

1.9

4.4

ÎÎ

5.9

2.2

ÎÎ

3.7

5.2

ÎÎ

Unit

MOTOROLA High–Speed CMOS Logic Data

3–2

DL129 — Rev 6

MC54/74HC273A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

ÎÎ

ÎÎÎОООООООÎООООООО

ÎÎ

Maximum Low–Level Output Voltage

ООООООО

Maximum Input Leakage Current Maximum Three–State Leakage

Current

ООООООО

Maximum Quiescent Supply Current (per Package)

ООООООО

Parameter

Output in High–Impedance State

Test Conditions

Vin = V

| v 20 µA

out

ООООООО

Vin = V

| v 2.4 mA

out

| v 6.0 mA

out

| v 7.8 mA

out

Vin = VCC or GND

Vin = VIL or V

ООООООО

= VCC or GND

out

Vin = VCC or GND I

= 0 µA

out

ООООООО

2.0

4.5

6.0

ÎÎ

3.0

4.5

ÎÎ

6.0

ÎÎ

6.0

ÎÎ

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

– 55 to

25_C

0.1

ÎÎ

0.26

ÎÎ

0.26

± 0.1 ± 0.5

ÎÎ

4.0

ÎÎ

85_C

0.1

ÎÎ

0.33

ÎÎ

0.33

± 1.0 ± 5.0

ÎÎ

125_C

0.1

ÎÎ

0.4

ÎÎ

0.4

± 1.0

± 10

ÎÎ

160

ÎÎ

Unit

µA µA

µA

AC ELECTRICAL CHARACTERISTICS (C

= 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

Symbol

ÎÎ

max

ÎÎ

PLH

PHL

ÎÎ

PHL

ÎÎ

TLH

THL

ÎÎ

ООООООООООООООО

Parameter

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

ООООООООООООООО

Maximum Propagation Delay, Clock to Q

(Figures 1 and 4)

ООООООООООООООО

Maximum Propagation Delay, Reset to Q

(Figures 2 and 4)

ООООООООООООООО

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ООООООООООООООО

Maximum Input Capacitance

ОООООООООООООООООО

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

– 55 to

25_C

ÎÎ

6.0 15

ÎÎ

30 35

ÎÎ

145

ÎÎ

29 25

ÎÎ

145

ÎÎ

29 25

ÎÎ

75 27

ÎÎ

15 13

ÎÎ

ÎÎ10ÎÎ

85_C

ÎÎ

5.0 10

ÎÎ

24 28

ÎÎ

180 120

ÎÎ

36 31

ÎÎ

180 120

ÎÎ

36 31

ÎÎ

95 32

ÎÎ

19 16

ÎÎ

125_C

ÎÎ

4.0

8.0

ÎÎ

20 24

ÎÎ

220 140

ÎÎ

44 38

ÎÎ

220 140

ÎÎ

44 38

ÎÎ

110

ÎÎ

22 19

ÎÎ

Unit

MHz

NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

*Used to determine the no–load dynamic power consumption: PD = CPD V

Motorola High–Speed CMOS Data Book (DL129/D).

Power Dissipation Capacitance (Per Enabled Output)*

f + ICC VCC. For load considerations, see Chapter 2 of the

High–Speed CMOS Logic Data DL129 — Rev 6

3–3 MOTOROLA

+ 4 hidden pages