Motorola MC54HC174AJ, MC74HC174AD, MC74HC174AN Datasheet

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SEMICONDUCTOR TECHNICAL DATA

1

REV 6

 Motorola, Inc. 1995

10/95

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High–Performance Silicon–Gate CMOS

The MC54/74HC174A is identical in pinout to the LS174. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.

This device consists of six D flip–flops with common Clock and Reset
inputs. Each flip–flop is loaded with a low–to–high transition of the Clock
input. Reset is asynchronous and active–low.

• Output Drive Capability: 10 LSTTL Loads

• TTL NMOS Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1.0 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 162 FETs or 40.5 Equivalent Gates

LOGIC DIAGRAM

PIN 16 = V

CC

PIN 8 = GND

3
4

6
11
13
14

2
5

7
10
12
15

D0
D1
D2
D3
D4
D5

Q0
Q1

Q2
Q3
Q4
Q5

CLOCK

9

RESET

1

DATA

INPUTS

NONINVERTING

OUTPUTS

Design Criteria

Value

Units

Internal Gate Count*

40.5

ea.

Internal Gate Propagation Delay

1.5

ns

Internal Gate Power Dissipation

5.0

µW

Speed Power Product

.0075

pJ

*Equivalent to a two–input NAND gate.

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PIN ASSIGNMENT

FUNCTION TABLE

Inputs Output

Reset Clock D Q

L X X L
H H H
H L L
H L X No Change
H X No Change

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q4

D4

D5

Q5

V

CC

CLOCK

Q3

D3

D1

D0

Q0

RESET

GND

Q2

D2

Q1

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD

Ceramic
Plastic
SOIC

1

16

1

16

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

1

16

MC54/74HC174A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

V

out

DC Output Voltage (Referenced to GND)

–0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

P

D

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

750
500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

(Ceramic DIP)

260
300

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time (Figure 1) VCC = 2.0 V

VCC = 4.5 V
VCC = 6.0 V

0
0
0

1000

500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

0.5

1.35

1.8

0.5

1.35

1.8

0.5

1.35

1.8

V

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin = VIH or V

IL

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.7

5.2

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

Vin = VIH or V

IL

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

0.26

0.26

0.33

0.33

0.4

0.4

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

V

OH

V

OL

Minimum High–Level Output
Voltage

Maximum Low–Level Output
Voltage

V

V