Motorola MC54HC165AJ, MC74HC165AN Datasheet

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SEMICONDUCTOR TECHNICAL DATA

1

REV 0

 Motorola, Inc. 1995

10/95

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High–Performance Silicon–Gate CMOS

The MC54/74HC165A is identical in pinout to the LS165. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.

This device is an 8–bit shift register with complementary outputs from the
last stage. Data may be loaded into the register either in parallel or in serial
form. When the Serial Shift/Parallel Load

input is low, the data is loaded

asynchronously in parallel. When the Serial Shift/Parallel Load

input is high,
the data is loaded serially on the rising edge of either Clock or Clock Inhibit
(see the Function Table).

The 2–input NOR clock may be used either by combining two independent
clock sources or by designating one of the clock inputs to act as a clock
inhibit.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 286 FETs or 71.5 Equivalent Gates

FUNCTION TABLE

Inputs Internal Stages Output

Serial Shift/

Parallel Load

Clock

Clock

Inhibit

S

A

A – H Q

A

Q

B

Q

H

Operation

L X X X a … h a b h Asynchronous Parallel Load
H

H

L
L

L
H

X
X

L
H

Q

An

Q

An

Q

Gn

Q

Gn

Serial Shift via Clock

H
H

L
L

L
H

X
X

L
H

Q

An

Q

An

Q

Gn

Q

Gn

Serial Shift via Clock Inhibit

H
H

X
H

H
X

X
X

X
X

No Change Inhibited Clock

H L L X X No Change No Clock

X = don’t care QAn – QGn = Data shifted from the preceding stage

This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.

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PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

B

C

D

CLOCK INHIBIT

V

CC

Q

H

S

A

A

F

E

CLOCK

SERIAL SHIFT/

PARALLEL LOAD

GND

Q

H

H

G

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

Ceramic
Plastic
SOIC
TSSOP

1

16

1

16

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

1

16

1

16

DT SUFFIX

TSSOP PACKAGE

CASE 948F–01

LOGIC DIAGRAM

PIN 16 = V

CC

PIN 8 = GND

11
12
13
14

3
4
5
6

10

A
B
C

D
E
F
G
H

S

A

PARALLEL

DATA

INPUTS

SERIAL

DATA

INPUT

SERIAL SHIFT/

PARALLEL LOAD

1

2

15

CLOCK

CLOCK INHIBIT

9

7

Q

H

Q

H

SERIAL

DATA

OUTPUTS

MC54/74HC165A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

P

D

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

TSSOP Package†

750
500
450

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

(Ceramic DIP)

260
300

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 3.0 V

VCC = 4.5 V
VCC = 6.0 V

0
0
0

1000

600
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

3.0

4.5

6.0

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

3.0

4.5

6.0

0.5

0.9

1.35

1.80

0.5

0.9

1.35

1.80

0.5

0.9

1.35

1.80

V

V

OH

Minimum High–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

V

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC54/74HC165A

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

V

CC

V

Test Conditions

Parameter

Symbol

Unit

v

125_C

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

V

OL

Maximum Low–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

3.0

4.5

6.0

0.26

0.26

0.26

0.33

0.33

0.33

0.40

0.40

0.40

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

4

40

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

f

max

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 8)

2.0

3.0

4.5

6.0

10
15
30
50

9
14
28
45

8
12
25
40

MHz

t

PLH

,

t

PHL

Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or Q

H

(Figures 1 and 8)

2.0

3.0

4.5

6.0

110

36
22
19

125

45
26
23

160

60
32
28

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Serial Shift/Parallel Load to QH or Q

H

(Figures 2 and 8)

2.0

3.0

4.5

6.0

85
57
25
19

96
63
29
23

106

71
32
27

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Input H to QH or Q

H

(Figures 3 and 8)

2.0

3.0

4.5

6.0

110

36
22
19

125

45
26
23

160

60
32
28

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 1 and 8)

2.0

3.0

4.5

6.0

75
27
15
13

95
32
19
16

110

36
22
19

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Package)*

40

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).