Motorola MC54HC162J Datasheet
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC54/74HC160 and HC162 are identical in pinout to the LS160 and
LS162, respectively. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC160 and HC162 are programmable BCD counters with asynchronous and synchronous Reset inputs, respectively.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 234 FETs or 58.5 Equivalent Gates
LOGIC DIAGRAM
PIN 16 = V
CC
PIN 8 = GND
11
12
13
14
Q0
Q1
Q2
Q3
15
RIPPLE
CARRY
OUT
BCD OR
BINARY
OUTPUTS
3
4
5
6
P0
P1
P2
P3
2
CLOCK
RESET
LOAD
ENABLE P
ENABLE T
COUNT
ENABLES
PRESENT
DATA
INPUTS
Device
Count
Mode
Reset Mode
HC160
BCD
Asynchronous
HC162
BCD
Synchronous
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
RESET
P0
CLOCK
GND
Q1
Q0
RIPPLE
CARRY OUT
V
CC
P1
P2
P3
ENABLE P
Q2
Q3
ENABLE T
LOAD
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
Inputs Output
Clock Reset* Load Enable P Enable T Q
L X X X Reset
H L X X Load Preset Data
H H H H Count
H H L X No Count
H H X L No Count
FUNCTION TABLE
*HC162 only. HC160 is an Asynchronous Reset Device
H = high level
L = low level
X = don’t care
MC54/74HC160 MC54/74HC162
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
P
D
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
OH
Minimum High–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
V
OL
Maximum Low–Level Output
Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC54/74HC160 MC54/74HC162
High–Speed CMOS Logic Data
DL129 — Rev 6
3 MOTOROLA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)*
(Figures 1 and 7)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
t
PLH
Maximum Propagation Delay, Clock to Q
(Figures 1 and 7)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
t
PHL
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
t
PHL
Maximum Propagation Delay, Reset to Q (HC160 Only)
(Figures 2 and 7)
2.0
4.5
6.0
210
42
36
265
53
45
315
63
54
ns
t
PLH
Maximum Propagation Delay, Enable T to Ripple Carry Out
(Figures 3 and 7)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
t
PHL
2.0
4.5
6.0
195
39
33
245
49
42
295
59
50
t
PLH
Maximum Propagation Delay, Clock to Ripple Carry Out
(Figures 1 and 7)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
t
PHL
2.0
4.5
6.0
215
43
37
270
54
46
325
65
55
t
PHL
Maximum Propagation Delay, Reset to Ripple Carry Out
(HC160 Only)
(Figures 2 and 7)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
in
Maximum Input Capacitance
—
10
10
10
pF
*Applies to noncascaded/nonsynchronously clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out
propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine f
max
. However,
if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the f
max
in the table above is applicable.
See Applications Information in this data sheet.
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
60
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
MC54/74HC160 MC54/74HC162
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
TIMING REQUIREMENTS (Input t
r
= tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
t
su
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
su
Minimum Setup Time, Load to Clock
(Figure 5)
2.0
4.5
6.0
135
27
23
170
34
29
205
41
35
ns
t
su
Minimum Setup Time, Reset to Clock (HC162 only)
(Figure 4)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
t
su
Minimum Setup Time, Enable T or Enable P to Clock
(Figure 6)
2.0
4.5
6.0
200
40
34
250
50
43
300
60
51
ns
t
h
Minimum Hold Time, Clock to Preset Data Inputs
(Figure 5)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
t
h
Minimum Hold Time, Clock to Load
(Figure 5)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
h
Minimum Hold Time, Clock to Reset (HC162 only)
(Figure 4)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
h
Minimum Hold Time, Clock to Enable T or Enable P
(Figure 6)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
rec
Minimum Recovery Time, Reset Inactive to Clock (HC160 only)
(Figure 2)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
rec
Minimum Recovery Time, Load Inactive to Clock
(Figure 5)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
w
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
w
Minimum Pulse Width, Reset (HC160 only)
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Loading...