Motorola MC44462B Datasheet



SEMICONDUCTOR

TECHNICAL DATA

Y–C PICTURE–IN–PICTURE

(PIP) CONTROLLER

B SUFFIX

PLASTIC PACKAGE

CASE 859

(SDIP)

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Device

Operating

Temperature Range

Package

ORDERING INFORMATION

MC44462B TJ = –65° to +150°C SDIP

MOTOROLA ANALOG IC DEVICE DATA

 

   

The MC44462 Y–C PIP controller is a low cost member of a family of high performance PIP controllers and video signal processors for television. It is a follow–up to the MC44461 PIP and has a modified input selection to allow higher performance in TV systems which have S–Video inputs on the back panel. The S–Video input is separate luma (luminance) and chroma components. It is NTSC compatible and contains all the analog signal processing, control logic and memory necessary to provide for the overlay of a small picture from a second non synchronized source onto the main picture of a television. All control and setup of the MC44462 is via a standard two pin I2C bus interface. The device is fabricated using BICMOS technology. It is available in a 56–pin shrink dip (SDIP) package.

The main features of the MC44462 are:

• Switchable PIP Composite Video Signals – Video 1 and Video 2

• S–Video Output Allows High Performance in TV

• Two PIP Sizes; 1/16 and 1/9 Screen Area

• Freeze Field Feature

• Variable PIP Position in 64–X by 64–Y Steps

• PIP Border with Programmable Color

• Programmable PIP Tint and Saturation Control

• Automatic Main to PIP Contrast Balance

• Vertical Filter

• Integrated 64 k Bit DRAM Memory Resulting in Minimal RFI

• Minimal RFI Allows Simple Low Cost Application into TV

• I

C Bus Control – No External Variable Adjustments Needed

• Operates from a Single 5.0 V Supply

• Economical 56–Pin Shrink DIP Package

YC–PIP System Diagram

Video

Processor

Main

(unused)

main out

YC PIP

MC44462

main in

W M

T R X

Y C

Comb

Filter

(MC141625)

IIC

Tuner/IF

Cable Y

Back Panel

S–VHS Inputs

Back Panel

Composite

Video Input

R G B

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

 Motorola, Inc. 1996 Issue 2

MC44462

MOTOROLA ANALOG IC DEVICE DATA

MAXIMUM RATINGS

Rating Symbol Value Unit

Power Supply Voltage

–0.5 to +6.0

Power Supply Voltage

–0.5 to +6.0

ББББББББББББ

Input Voltage Range

ÁÁ

ÁÁÁ

–0.5,

+ 0.5

Output Current

160

Power Dissipation

Maximum Power Dissipation @ 70°C

1.3

Thermal Resistance, Junction–to–Air

θJA

°C/W

Junction T emperature (Storage and Operating)

–65 to +150

°C

NOTE: ESD data available upon request.

ELECTRICAL CHARACTERISTICS (V

= VDD = 5.0 V , TA = 25°C, unless otherwise noted.)

Characteristic

Symbol Min Typ Max Unit

POWER SUPPLY

Total Supply (Pins 8, 15, 43 and 50)

Total I

Supply

–

100

160

ÁÁÁ

VIDEO

Composite Video Input (Pin 34 or 36)

CVi

–

1.0

–

ÁÁÁ

Vpp

Luma Output (Pin 49, Unterminated)

–

2.0

–

ÁÁÁ

Vpp

Video Output DC Level (Sync Tip)

–

1.0

–

ÁÁÁ

Vdc

Video Gain

–

6.0

–

ÁÁÁ

Video Frequency Response (Main Video to –1.0 dB)

–

ÁÁÁ

MHz

Color Bar Accuracy

–

±4.0

–

ÁÁÁ

deg

Video Crosstalk (@ 75% Color Bars)

–

ÁÁÁ

Main to PIP

–

ÁÁÁ

PIP to Main

–

БББББББББББББББББ

Output Impedance

ÁÁÁ–ÁÁ–ÁÁ

5.0

ÁÁ

–

ÁÁÁ

ÁÁ

Ω

HORIZONTAL TIMEBASE

Free Run HPLL Frequency (Pin 16)

–

15734

–

ÁÁÁ

HPLL Pull–In Range

–

±400

–

ÁÁÁ

HPLL Jitter

–

±4.0

–

ÁÁÁ

Burst Gate Timing (from Trailing Edge Hsync, Pin 24)

–

1.0

–

ÁÁÁ

µs

Burst Gate Width

–

4.0

–

ÁÁÁ

µs

VERTICAL TIMEBASE

Vertical Countdown Window

–

232 – 296

–

ÁÁÁ

H lines

Vertical Sync Integration T ime

–

ÁÁÁ

µs

ANALOG TO DIGITAL CONVERTER

Resolution

–

ÁÁÁ

Bits

Integral Non–Linearity

–

±1

–

ÁÁÁ

LSB

Differential Non–Linearity

–

+2/–1

–

ÁÁÁ

LSB

ADC – Y Frequency Response @ –5.0 dB

–

1.0

–

ÁÁÁ

MHz

ADC – U, V Frequency Response @ –5.0 dB

–

200

–

ÁÁÁ

kHz

Sample Clock Frequency (4/3 FSC)

–

4.773

–

ÁÁÁ

MHz

MC44462

MOTOROLA ANALOG IC DEVICE DATA

ELECTRICAL CHARACTERISTICS (continued) (V

= VDD = 5.0 V , TA = 25°C, unless otherwise noted.)

Characteristic UnitMaxTypMinSymbol

DIGITAL TO ANALOG CONVERTER

Resolution

–

ÁÁÁ

Bits

Integral Non–Linearity

–

±1

–

ÁÁÁ

LSB

Differential Non–Linearity

–

+2/–1

–

ÁÁÁ

LSB

Tint DAC Control Range (in 64 Steps)

–

±10

–

ÁÁÁ

Deg

Saturation DAC Control Range (in 64 steps)

–

±6.0

–

ÁÁÁ

NTSC DECODER

Color Kill Threshold

–

–24/–16

–

ÁÁÁ

Threshold Hysteresis

–

±1.0

–

ÁÁÁ

ACC (Chroma Amplitude Change, +3.0 dB to –12 dB)

–

±0.5

–

ÁÁÁ

PIP CHARACTERISTICS

PIP Size

–

ÁÁÁ

1/9 Screen Horizontal

–

114

–

ÁÁÁ

pels

1/9 Screen Vertical

–

ÁÁÁ

lines

1/16 Screen Horizontal

–

ÁÁÁ

pels

1/16 Screen Vertical

–

ÁÁÁ

lines

Border Size Horizontal

–

ÁÁÁ

pels

Border Size Vertical

–

ÁÁÁ

lines

Output PEL Clock (4 FSC)

–

14.318

–

ÁÁÁ

MHz

Position Control Range Horizontal (% of Main Picture), 64 Steps

–

100

–

ÁÁÁ

Position Control Range Vertical (% of Main Picture), 64 Steps

–

100

–

ÁÁÁ

Figure 1. Representative Block Diagram

This device contains approximately 500,000 active transistors.

Y V

YUV

Clamp

Input

Switch

Low Pass

Filter

Band Pass

Filter

NTSC

Decoder

PIP

Switch

4X S/C

Osc + PLL

16X S/C

Osc + PLL

YUV

Clamp

NTSC

Encoder

4X S/C

Osc + PLL

Filter

Tracking

6–Bit ADC

H and V

Timebase

Digital

Logic

Memory

8.0 k x 8 DRAM

Tint DAC Sat DAC

V DAC

Y DAC

3.0 MHz LPF

Y V

40 41 42

1 2 3 4 5

10 30

5453524746

Vert

57.28 MHz

14.32 MHz

36 34

37 49

38 39

44 45

Multiplexer

Video 1/ Luma

Video 2/Chroma

Decoder ACC

Y Out

Decoder Xtal Decoder PLL

16 FSC PLL

Encoder Phase

Encoder ACC

H PLL

SCL SDA Reset

Vid 1/2 Sel Multi T est

Encoder Clamp Caps

Encoder Xtal

Encoder

PLL

Decoder Clamp Caps

Filter PLL

U DAC

C Out

Y Main

C Main

Sync Sep

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