Motorola MC33304D, MC33304P Datasheet

Device
Tested Operating
Temperature Range
Package

SEMICONDUCTOR
TECHNICAL DATA
OPERATIONAL AMPLIFIER
ORDERING INFORMATION
MC33304D MC33304P
TA = – 40° to +105°C
SO–14
Plastic DIP
P SUFFIX
PLASTIC PACKAGE
CASE 646
14
1
PIN CONNECTIONS
Order this document by MC33304/D
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
14
1
(Quad, Top View)
Output 1
Inputs 1
V
CC
Output 4
Inputs 4
1
12
13
14
11
3
2
1
4
105
96
Output 2
8
7
Inputs 2
2
4
3
V
EE
Inputs 3
Output 3
1
MOTOROLA ANALOG IC DEVICE DATA
 
  
t
t  
The MC33304 is a monolithic bipolar operational amplifier. This low voltage rail–to–rail amplifier has both a rail–to–rail input and output stage, with high output current capability. This amplifier also employs SLEEPMODE technology. In sleepmode, the micropower amplifier is active and waiting for an input signal. When a signal is applied, causing the amplifier to source or sink 200 µA (typically) to the load, it will automatically switch to the awakemode (supplying up to 70 mA to the load). When the output current drops below 90 µA, the amplifier automatically returns to the sleepmode.
Excellent performance can be achieved as an audio amplifier. This is due to the amplifier’s low noise and low distortion. A delay circuit is incorporated to prevent crossover distortion.
Ideal for Battery Applications
Full Output Signal (No Distortion) for Battery Applications Down
to ±0.9 VDC.
Single Supply Operation (+1.8 to +12 V)
Rail–To–Rail Performance on Both the Input and Output
Output Voltages Swings Typically within 100 mV of Both Rails
(RL = 1.0 m)
Two States: “Sleepmode” (Micropower, I
D
= 110 µA/Amp) and
“Awakemode” (High Performance, ID = 1200 µA/Amp)
Automatic Return to Sleepmode when Output Current Drops Below
Threshold, Allowing a Fully Functional Micropower Amplifier
Independent Sleepmode Function for Each Amplifier
No Phase Reversal on the Output for Overdriven Input Signals
High Output Current (70 mA typically)
600 Drive Capability
Standard Pinouts; No Additional Pins or Components Required
Drop–In Replacement for Many Other Quad Operational Amplifiers
Similar to MC33201, MC33202 and MC33204 Family
The MC33304 Amplifier is Offered in the Plastic DIP or SOIC Package
(P and D Suffixes) SLEEPMODE and Rail–To–Rail are trademarks of Motorola, Inc.
TYPICAL DC ELECTRICAL CHARACTERISTICS
(TA = 25°C)
Characteristic
VCC = 2.0 V VCC = 3.3 V VCC = 5.0 V Unit
Input Offset Voltage mV
V
IO(max)
MC33304 ±10 ±10 ±10
Output Voltage Swing
VOH (RL = 600 ) 1.85 3.10 4.75 V
min
VOL (RL = 600 ) 0.15 0.15 0.15 V
max
Power Supply Current
per Amplifier (ID)
Awakemode 1.625 1.625 1.625 mA Sleepmode 140 140 140 µA
Specifications are for reference only and not necessarily guaranteed. VEE = Gnd.
Motorola, Inc. 1995
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC33304
2
MOTOROLA ANALOG IC DEVICE DATA
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (VCC to VEE) V
S
+16 V
ESD Protection Voltage at Any Pin
Human Body Model
V
ESD
2000
V
Voltage at Any Device Pin (Note 2) V
DP
VS ± 0.5 V
Input Differential Voltage Range V
IDR
(Notes 1 & 2) V
Output Short Circuit Duration t
s
Indefinite
(Note 3)
sec
Maximum Junction Temperature T
J
+150 °C
Storage Temperature Range T
stg
–65 to +150 °C
Maximum Power Dissipation P
D
(Note 5) mW
RECOMMENDED OPERATING CONDITIONS
Characteristic Symbol Min Typ Max Unit
Supply Voltage V
S
V Single Supply 1.8 12 Split Supplies ±0.9 ±6.0
Input Voltage Range, Sleepmode and A wakemode V
ICR
V
EE
V
CC
V
Ambient Operating Temperature Range T
A
–40 +105 °C
DC ELECTRICAL CHARACTERISTICS (V
CC
= +5.0 V, VEE = Gnd, TA = 25°C, unless otherwise noted.)
Characteristic
Symbol Min Typ Max Unit
Input Offset Voltage (VCM = 0 V, VO = 0 V) (Note 4)
Sleepmode and Awakemode
TA = 25°C TA = –40° to +105°C
V
IO
–10 –13
0.7 –
+10 +13
mV
Average Temperature Coefficient of Input Offset Voltage
(RS = 50 , VCM = 0 V, VO = 0 V)
TA = –40° to +105°C, Sleepmode and Awakemode
VIO/T
2.0
µV/°C
Input Bias Current (VCM = 0 V, VO = 0 V) (Note 4)
Awakemode
TA = 25°C TA = –40° to +105°C
IIB|
– –
90
+200 +500
nA
Input Offset Current (VCM = 0 V, VO = 0 V) (Note 4)
Awakemode
TA = 25°C TA = –40° to +105°C
|IIO|
– –
3.1 –
+50
+100
nA
Large Signal Voltage Gain (VCC = +5.0 V, VEE = –5.0 V)
Awakemode, RL = 600
TA = 25°C TA = –40° to +105°C
A
VOL
90 85
116
– –
dB
Power Supply Rejection Ratio, Awakemode PSRR 65 90 dB Output Short Circuit Current (Awakemode)
(VID = ±0.2 V)
Source Sink
I
SC
–200
+50
–89 +89
–50
+200
mA
Output Transition Current, Source/Sink
Sleepmode to Awakemode, VCC = +1.0 V, VEE = –1.0 V Awakemode to Sleepmode, VCC = +5.0 V, VEE –5.0 V
|I
TH1
|
|I
TH2
|
90
– –
200
µA
MC33304
3
MOTOROLA ANALOG IC DEVICE DATA
DC ELECTRICAL CHARACTERISTICS (continued) (V
CC
= +5.0 V, VEE = Gnd, TA = 25°C, unless otherwise noted.)
Characteristic UnitMaxTypMinSymbol
Output Voltage Swing (VID = ±0.2 V)
Sleepmode
VCC = +5.0 V, VEE = 0 V, RL = 1.0 M VCC = 0 V, VEE = –5.0 V, RL = 1.0 M VCC = +2.0 V, VEE = 0 V, RL = 1.0 M VCC = 0 V, VEE = –2.0 V, RL = 1.0 M
Awakemode
VCC = +5.0 V, VEE = 0 V, RL = 600 VCC = 0 V, VEE = –5.0 V, RL = 600 VCC = +2.0 V, VEE = 0 V, RL = 600 VCC = 0 V, VEE = –2.0 V, RL = 600 VCC = +2.5 V, VEE = –2.5 V, RL = 600 VCC = +2.5 V, VEE = –2.5 V, RL = 600
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
4.90 –
1.90 –
4.75 –
1.85 – – –
4.97
–4.96
1.98
–1.97
4.86
–4.85
1.91
–1.90
2.41
–2.40
–4.90
–1.90
–4.75
–1.85
– –
V
Common Mode Rejection Ratio CMRR 60 90 dB Power Supply Current (per Amplifier)
Sleepmode
VCC = +2.0 V, VEE = 0 V TA = +25°C VCC = +2.5 V, VEE = –2.5 V TA = +25°C
TA = –40° to +105°C
VCC = +12 V, VEE = 0 V TA = +25°C
Awakemode
VCC = +2.5 V, VEE = –2.5 V TA = +25°C
TA = –40° to +105°C
I
D
– – – –
– –
85
110
125
1200
– 140 150
1625 1750
µA
Thermal Resistance
SOIC Plastic DIP
θ
JA
– –
145
75
°C/W
AC ELECTRICAL CHARACTERISTICS (V
CC
= +6.0 V, VEE = –6.0 V, RL = 600 , TA = 25°C, unless otherwise noted.)
Characteristic
Symbol Min Typ Max Unit
Slew Rate (VCC = +2.5 V, VEE = –2.5 V, AV = +1.0) (Note 6)
Awakemode
SR
0.5 0.89
V/µs
Gain Bandwidth Product (f = 100 kHz)
Awakemode
GBW
2.2
MHz
Gain Margin (CL = 0 pF)
Awakemode Sleepmode (RL = 1.0 kΩ)
A
m
– –
6.0
9.0
dB
Phase Margin (RL = 1.0 k, VO = 0 V, CL = 0 pF)
Awakemode Sleepmode
φ
m
– –
40 60
Deg
Sleepmode to Awakemode Transition Time
RL = 600 RL = 10 k
t
tr1
– –
4.0 12
– –
µsec
Awakemode to Sleepmode Transition Time t
tr2
1.5 sec
Channel Separation (f = 1.0 kHz)
Awakemode
CS
100
dB
NOTES: 1. The differential input voltage of each amplifier is limited by two internal diodes. The diodes are connected across the inputs in parallel and opposite to
each other. For more differential input voltage range, use current limiting resistors in series with the input pins.
2.The common–mode input voltage range of each amplifier is limited by diodes connected from the inputs to both power supply rails. Therefore, the voltage on either input must not exceed supply rail by more than ±500 mV.
3.Simultaneous short circuits of two or more amplifiers to the positive or negative rail can exceed the power dissipation ratings and cause eventual failure of the device.
4.Rail–to–rail performance is achieved at the input of the amplifier by using parallel NPN–PNP differential stages. When the inputs are near the negative rail (VEE < VCM < 800 mV), the PNP stage is on. When the inputs are above 800 mV (i.e. 800 mV < VCM < VCC), the NPN stage is on. This switching of the input pairs will cause a reversal of input bias current. Slight changes in the input offset voltage will be noted between the NPN and PNP pairs. Cross–coupling techniques have been used to keep this change to a minimum.
5.Power dissipation must be considered to ensure maximum junction (TJ) is not exceeded. (See Figure 2)
6.When connected as a voltage follower and used in transient conditions, a current limiting resistor may be needed between the output and the inverting input. This is because of the back to back diodes clamped across the inputs. The value of this resistor should be between 1.0 kΩ and 10 k. If the amplifier does not become slew rate limited and is processing low frequency waveforms, then no resistor would be necessary. (The output could be tied directly to the negative input.)
MC33304
4
MOTOROLA ANALOG IC DEVICE DATA
AC ELECTRICAL CHARACTERISTICS
(continued) (VCC = +6.0 V, VEE = –6.0 V, RL = 600 , TA = 25°C, unless otherwise noted.)
Characteristic UnitMaxTypMinSymbol
Power Bandwidth (VO = 4.0 V
pp, RL
= 2.0 k, THD 1.0%)
Awakemode
BW
p
28
kHz
Distortion (VO = 2.0 Vpp, AV = +1.0)
Awakemode (f = 10 kHz) Sleepmode (f = 1.0 kHz, RL = Infinite)
THD
– –
0.009
0.007
– –
%
Open Loop Output Impedance
(VO = 0 V, f = 2.0 MHz, AV = +10, IQ = 10 µA)
Awakemode Sleepmode
|ZO|
– –
100
1000
– –
Differential Input Impedance (VCM = 0 V)
Awakemode Sleepmode
R
IN
– –
200
1300
– –
k
Differential Input Capacitance (VCM = 0 V)
Awakemode Sleepmode
C
IN
– –
8.0
0.4
– –
pF
Equivalent Input Noise Voltage (RS = 100 , f = 1.0 kHz)
Awakemode Sleepmode
e
n
– –
15 60
– –
nVńHz
Ǹ
Equivalent Input Noise Current (f = 1.0 kHz)
Awakemode Sleepmode
i
n
– –
0.22
0.20
– –
pAńHz
Ǹ
NOTES: 1. The differential input voltage of each amplifier is limited by two internal diodes. The diodes are connected across the inputs in parallel and opposite to
each other. For more differential input voltage range, use current limiting resistors in series with the input pins.
2.The common–mode input voltage range of each amplifier is limited by diodes connected from the inputs to both power supply rails. Therefore, the voltage on either input must not exceed supply rail by more than ±500 mV.
3.Simultaneous short circuits of two or more amplifiers to the positive or negative rail can exceed the power dissipation ratings and cause eventual failure of the device.
4.Rail–to–rail performance is achieved at the input of the amplifier by using parallel NPN–PNP differential stages. When the inputs are near the negative rail (VEE < VCM < 800 mV), the PNP stage is on. When the inputs are above 800 mV (i.e. 800 mV < VCM < VCC), the NPN stage is on. This switching of the input pairs will cause a reversal of input bias current. Slight changes in the input offset voltage will be noted between the NPN and PNP pairs. Cross–coupling techniques have been used to keep this change to a minimum.
5.Power dissipation must be considered to ensure maximum junction (TJ) is not exceeded. (See Figure 2)
6.When connected as a voltage follower and used in transient conditions, a current limiting resistor may be needed between the output and the inverting input. This is because of the back to back diodes clamped across the inputs. The value of this resistor should be between 1.0 kΩ and 10 k. If the amplifier does not become slew rate limited and is processing low frequency waveforms, then no resistor would be necessary. (The output could be tied directly to the negative input.)
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