MOTOROLA MC14562BCP Datasheet

MC14562B

128-Bit Static Shift
Register

The MC14562B is a 128–bit static shift register constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. Data is clocked in and out of the shift
register on the positive edge of the clock input. Data outputs are
available every 16 bits, from 16 through bit 128. This complementary
MOS shift register is primarily used where low power dissipation
and/or high noise immunity is desired.

• Diode Protection on All Inputs

• Fully Static Operation

• Cascadable to Provide Longer Shift Register Lengths

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving T wo Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated T emperature Range

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

DD

Vin, V

Iin, I

P

T

T

stg

T

1. Maximum Ratings are those values beyond which damage to the device

may occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

DC Supply Voltage Range –0.5 to +18.0 V
Input or Output Voltage Range

out

Input or Output Current

out

Power Dissipation,

D

Ambient Temperature Range –55 to +125 °C

A

Storage Temperature Range –65 to +150 °C
Lead Temperature

L

Parameter Value Unit

(DC or Transient)

(DC or Transient) per Pin

per Package (Note 2.)

(8–Second Soldering)

) (Note 1.)

SS

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

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MARKING

DIAGRAMS

14

PDIP–14

P SUFFIX

CASE 646

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

MC14562BCP

AWLYYWW

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ORDERING INFORMATION

Device Package Shipping

MC14562BCP PDIP–14 25/Rail

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 3

v (Vin or V

SS

or VDD). Unused outputs must be left open.

) v VDD.

out

and V

in

should be constrained

out

1 Publication Order Number:

MC14562B/D

MC14562B

PIN ASSIGNMENT

Q64
Q96

Q128

NC

CLOCK

Q112

V

SS

NC = NO CONNECTION

BLOCK DIAGRAM

12

5

Pins 4 and 11
not used.

DATA

CLOCK

1
2
3
4

6
7

14
13
12
11
105

9
8

Q16
Q32
Q48
Q64
Q80
Q96

Q112

V

DD

V

V
Q32
DATA
NC
Q16
Q48

Q80

= PIN 14

= PIN 7

SS

DD

10
13
9
1
8
2
6
3Q128

CLOCK 5

DATA IN 12

LOGIC DIAGRAM

DCQDCQDCQDCQDCQDCQDCQDCQD

1 2 3 16173233484964

DCQDCQDCQDCQ

65 80 81 96

DCQ

97

DCQ

112

DCQ

113

DCQ

128

QDCQ

C

10 Q16

13 Q32

9 Q48

1 Q64

8 Q80

2 Q96

6Q112

3 Q128

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MC14562B

V

DD

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

V

Characteristic Symbol

Output Voltage “0” Level

V

= VDD or 0

in

“1” Level

V

= 0 or V

in

DD

Input Voltage “0” Level

(V

= 4.5 or 05 Vdc)

O

(V

= 9.0 or 1.0 Vdc)

O

(V

= 13.5 or 1.5 Vdc)

O

“1” Level

(V

= 0.5 or 4.5 Vdc)

O

= 1.0 or 9.0 Vdc)

(V

O

(V

= 1.5 or 13.5 Vdc)

O

Output Drive Current

(V

= 2.5 Vdc) Source

OH

(V

= 4.6 Vdc)

OH

(V

= 9.5 Vdc)

OH

(V

= 13.5 Vdc)

OH

(VOL = 0.4 Vdc) Sink
(V

= 0.5 Vdc)

OL

= 1.5 Vdc)

(V

OL

Input Current I
Input Capacitance

(V

= 0)

in

Quiescent Current

(Per Package)

Total Supply Current

(4.) (5.)

(Dynamic plus Quiescent,
Per Package)

= 50 pF on all outputs, all

(C

L

V

OL

V

OH

V

V

I

OH

I

OL

in

C

I

DD

I

Vdc

5.0
10
15

5.0
10
15

IL

5.0
10
15

IH

5.0
10
15

5.0

5.0
10
15

5.0
10
15

Min Max Min Typ

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

– 3.0

– 0.64

– 1.6
– 4.2

0.64

1.6

4.2

15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc

in

T

— — — — 5.0 7.5 — — pF

5.0
10
15

—
—
—

5.0
10
15

)

SS

– 55_C 25_C 125_C

(3.)

Max Min Max

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0

—
—
—

—
—
—
—

—
—
—

5.0
10
20

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

– 2.4

– 0.51

– 1.3
– 3.4

0.51

1.3

3.4

—
—
—

0
0
0

5.0
10
15

2.25

4.50

6.75

2.75

5.50

8.25

– 4.2

– 0.88

– 2.25

– 8.8

0.88

2.25

8.8

0.010

0.020

0.030

IT = (1.94 µA/kHz) f + I
IT = (3.81 µA/kHz) f + I
IT = (5.52 µA/kHz) f + I

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0

—
—
—

—
—
—
—

—
—
—

5.0
10
20

DD
DD
DD

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

– 1.7

– 0.36

– 0.9
– 2.4

0.36

0.9

2.4

—
—
—

0.05

0.05

0.05

buffers switching)

3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

4. The formulas given are for the typical characteristics only at 25_C.

5. To calculate total supply current at loads other than 50 pF:
I

) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

T

—
—
—

1.5

3.0

4.0

—
—
—

—
—
—
—

—
—
—

150
300
600

Unit

Vdc

Vdc

Vdc

Vdc

mAdc

mAdc

µAdc

µAdc

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