Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1 Publication Order Number:
MC14557B/D
MC14557B
1-to-64 Bit V ariable Length
Shift Register
The MC14557B is a static clocked serial shift register whose length
may be programmed to be any number of bits between 1 and 64. The
number of bits selected is equal to the sum of the subscripts of the
enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus
one. Serial data may be selected from the A or B data inputs with the
A/B select input. This feature is useful for recirculation purposes. A
Clock Enable (CE) input is provided to allow gating of the clock or
negative edge clocking capability .
The device can be effectively used for variable digital delay lines or
simply to implement odd length shift registers.
• 1–64 Bit Programmable Length
• Q and Q Serial Buffered Outputs
• Asynchronous Master Reset
• All Inputs Buffered
• No Limit On Clock Rise and Fall T imes
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or one Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage Range –0.5 to +18.0 V
Vin, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current
(DC or Transient) per Pin
±10 mA
P
D
Power Dissipation,
per Package (Note 3.)
500 mW
T
A
Ambient Temperature Range –55 to +125 °C
T
stg
Storage Temperature Range –65 to +150 °C
T
L
Lead Temperature
(8–Second Soldering)
260 °C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. T emperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or VDD). Unused outputs must be left open.
http://onsemi.com
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14557BCP PDIP–16 2000/Box
MC14557BDW SOIC–16 47/Rail
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC14557BCP
AWLYYWW
SOIC–16
DW SUFFIX
CASE 751G
1
16
14557B
AWLYYWW
MC14557BDWR2 SOIC–16 1000/Tape & Reel
MC14557BF SOEIAJ–16 See Note 1.
MC14557BFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14557B
AWLYWW