Motorola MC14555BCP, MC14556BCL, MC14556BCP, MC14556BD, MC14555BD Datasheet
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MOTOROLA CMOS LOGIC DATA
1
MC14555B MC14556B
The MC14555B and MC14556B are constructed with complementary
MOS (CMOS) enhancement mode devices. Each Decoder/Demultiplexer
has two select inputs (A and B), an active low Enable input (E), and four
mutually exclusive outputs (Q0, Q1, Q2, Q3). The MC14555B has the
selected output go to the “high” state, and the MC14556B has the selected
output go to the “low” state. Expanded decoding such as binary–to–hexadecimal ( 1–of–16), e tc., can be achieved by using other MC14555B or
MC14556B devices.
Applications include code conversion, address decoding, memory selection control, and demultiplexing (using the Enable input as a data input) in
digital data transmission systems.
• Diode Protection on All Inputs
• Active High or Active Low Outputs
• Expandable
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 18.0 V
Vin, V
out
Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current (DC or Transient),
per Pin
± 10 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
“P and D/DW” Packages: – 7.0 mW/C From 65_C To 125_C Ceramic
“L” Packages: – 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
2
4
MC14555B MC14556B
3
1
14
13
15
5
6
7
12
11
10
9
2
4
3
1
14
13
15
5
6
7
12
11
10
9
VDD = PIN 16
VSS = PIN 8
A
B
E
Q0
Q1
Q2
Q3
A
B
E
Q
0
Q
1
Q
2
Q
3
A
B
E
Q0
Q1
Q2
Q3
A
B
E
Q
0
Q
1
Q
2
Q3
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and V
out
should be constrained
to the range VSS v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or VDD). Unused outputs must be left open.
TRUTH TABLE
Inputs Outputs
Enable Select MC14555B MC14556B
E
B A Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0 0 0 0 0 0 1 1 1 1 0
0 0 1 0 0 1 0 1 1 0 1
0 1 0 0 1 0 0 1 0 1 1
0 1 1 1 0 0 0 0 1 1 1
1 X X 0 0 0 0 1 1 1 1
X = Don’t Care
MOTOROLA CMOS LOGIC DATAMC14555B MC14556B
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C 25_C 125_C
Characteristic
Symbol
V
DD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage “0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current I
in
15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
Input Capacitance
(Vin = 0)
C
in
— — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (0.85 µA/kHz) f + I
DD
IT = (1.70 µA/kHz) f + I
DD
IT = (2.60 µA/kHz) f + I
DD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
PIN ASSIGNMENTS
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q0
B
B
B
A
B
E
B
V
DD
Q3
B
Q2
B
Q1
B
Q0
A
B
A
A
A
E
A
V
SS
Q3
A
Q2
A
Q1
A
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q
0
B
B
B
A
B
E
B
V
DD
Q
3
B
Q
2
B
Q
1
B
Q
0
A
B
A
A
A
E
A
V
SS
Q
3
A
Q
2
A
Q
1
A
MC14555B MC14556B
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