Motorola MC14551BCL, MC14551BCP, MC14551BD Datasheet

MOTOROLA CMOS LOGIC DATA

1

MC14551B

  
  

The MC14551B is a digitally–controlled analog switch. This device
implements a 4PDT solid state switch with low ON impedance and very low
OFF Leakage current. Control of analog signals up to the complete supply
voltage range can be achieved.

• Triple Diode Protection on All Control Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V

Note: VEE must be v V

SS

• Linearized Transfer Characteristics

• Low Noise — 12 nV√Cycle

, f ≥ 1.0 kHz typical

• For Low RON, Use The HC4051, HC4052, or HC4053 High–Speed

CMOS Devices

• Switch Function is Break Before Make

MAXIMUM RATINGS*

Symbol Parameter Value Unit

V

DD

DC Supply Voltage (Referenced to VEE,
VSS ≥ VEE)

– 0.5 to + 18.0 V

Vin, V

out

Input or Output Voltage (DC or Transient)
(Referenced to VSS for Control Input &
VEE for Switch I/O)

– 0.5 to VDD + 0.5 V

I

in

Input Current (DC or Transient), per
Control Pin

± 10 mA

I

sw

Switch Through Current ± 25 mA

P

D

Power Dissipation, per Package† 500 mW

T

stg

Storage Temperature – 65 to + 150

_

C

T

L

Lead Temperature (8–Second Soldering) 260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages – 12 mW/_C From 100_C To 125_C

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Z1

Z

W

W0

V

DD

CONTROL

Y1

Z0

X

X1

X0

W1

V

SS

V

EE

Y0

Y

PIN ASSIGNMENT

VDD = Pin 16
VSS = Pin 8
VEE = Pin 7

NOTE: Control Input referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be v VSS.

Control ON

0 W0 X0 Y0 Z0
1 W1 X1 Y1 Z1

12

11

10

6

3

2

1

15

9

13

5

4

14

SWITCHES

IN/OUT

COMMONS

OUT/IN

CONTROL

W0
W1
X0
X1
Y0
Y1
Z0
Z1

W

X

Y

Z



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3
1/94



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

MOTOROLA CMOS LOGIC DATAMC14551B

2

ELECTRICAL CHARACTERISTICS

– 55_C 25_C 125_C

Characteristic

Symbol

VDDTest Conditions

Min Max Min Typ # Max Min Max

Unit

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Supply Voltage

Range

V

DD

— VDD – 3.0 ≥ VSS ≥

V

EE

3.0 18 3.0 — 18 3.0 18 V

Quiescent Current Per

Package

I

DD

5.0
10
15

Control Inputs: Vin

=

VSS or VDD,

Switch I/O: VEE v V

I/O

v

VDD, and ∆V

switch

v

500 mV**

—
—
—

5.0
10
20

—
—
—

0.005

0.010

0.015

5.0
10
20

—
—
—

150
300
600

µA

Total Supply Current

(Dynamic Plus
Quiescent, Per Package)

I

D(AV)

5.0
10
15

TA = 25_C only (The

channel component,
(Vin – V

out

)/Ron, is

not included.)

(0.07 µA/kHz) f + I

DD

Typical (0.20 µA/kHz) f + I

DD

(0.36 µA/kHz) f + I

DD

µA

CONTROL INPUT (Voltages Referenced to VSS)

Low–Level Input Voltage V

IL

5.0
10
15

Ron = per spec,
I

off

= per spec

—
—
—

1.5

3.0

4.0

—
—
—

2.25

4.50

6.75

1.5

3.0

4.0

—
—
—

1.5

3.0

4.0

V

High–Level Input Voltage V

IH

5.0
10
15

Ron = per spec,
I

off

= per spec

3.5

7.0
11

—
—
—

3.5

7.0
11

2.75

5.50

8.25

—
—
—

3.5

7.0
11

—
—
—

V

Input Leakage Current I

in

15 Vin = 0 or V

DD

— ±0.1 — ±0.00001 ±0.1 — ±1.0 µA

Input Capacitance C

in

— — — — 5.0 7.5 — — pF

SWITCHES IN/OUT AND COMMONS OUT/IN — W, X, Y, Z (Voltages Referenced to VEE)

Recommended Peak–to–

Peak Voltage Into or Out
of the Switch

V

I/O

— Channel On or Off 0 V

DD

0 — V

DD

0 V

DDVp–p

Recommended Static or

Dynamic Voltage Across
the Switch** (Figure 3)

∆V

switch

— Channel On 0 600 0 — 600 0 300 mV

Output Offset Voltage V

OO

— Vin = 0 V, No Load — — — 10 — — — µV

ON Resistance R

on

5.0
10
15

∆V

switch

v 500 mV**,

Vin = VIL or V

IH

(Control), and Vin =
0 to VDD (Switch)

——800

400
220

—
—
—

250
120

80

1050

500
280

—
—
—

1200

520
300

Ω

∆ON Resistance Between

Any Two Channels
in the Same Package

∆R

on

5.0
10
15

—
—
—

70
50
45

—
—
—

25
10
10

70
50
45

—
—
—

135

95
65

Ω

Off–Channel Leakage

Current (Figure 8)

I

off

15 Vin = VIL or V

IH

(Control) Channel to
Channel or Any One
Channel

— ±100 — ±0.05 ±100 — ±1000 nA

Capacitance, Switch I/O C

I/O

— Switch Off — — — 10 — — — pF

Capacitance, Common O/I C

O/I

— — — — 17 — — — pF

Capacitance, Feedthrough

(Channel Off)

C

I/O

——Pins Not Adjacent

Pins Adjacent

—————

—

0.15

0.47

———

—

—
—

pF

#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
**āFor voltage drops across the switch (∆V

switch

) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the

**ācurrent out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum
**āRatings are exceeded. (See first page of this data sheet.)

MOTOROLA CMOS LOGIC DATA

3

MC14551B

ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, TA = 25_C, VEE v VSS)

Characteristic

Symbol

VDD – V

EE

Vdc

Min Typ # Max Unit

Propagation Delay Times

Switch Input to Switch Output (RL = 10 kΩ)

t

PLH

, t

PHL

= (0.17 ns/pF) CL + 26.5 ns

t

PLH

, t

PHL

= (0.08 ns/pF) CL + 11 ns

t

PLH

, t

PHL

= (0.06 ns/pF) CL + 9.0 ns

t

PLH

, t

PHL

5.0
10
15

—
—
—

35
15
12

90
40
30

ns

Control Input to Output (RL = 10 kΩ)

VEE = VSS (Figure 4)

t

PLH

, t

PHL

5.0
10
15

—
—
—

350
140
100

875
350
250

ns

Second Harmonic Distortion

RL = 10 kΩ, f = 1 kHz, Vin = 5 V

p–p

— 10 — 0.07 — %

Bandwidth (Figure 5)

RL = 1 kΩ, Vin = 1/2 (VDD – VEE)

p–p

,

20 Log (V

out/Vin

) = – 3 dB, CL = 50 pF

BW 10 — 17 — MHz

Off Channel Feedthrough Attenuation, Figure 5

RL = 1 kΩ, Vin = 1/2 (VDD – VEE)

p–p

,

fin = 55 MHz

— 10 — – 50 — dB

Channel Separation (Figure 6)

RL = 1 kΩ, Vin = 1/2 (VDD – VEE)

p–p

,

fin = 3 MHz

— 10 — – 50 — dB

Crosstalk, Control Input to Common O/I, Figure 7

R1 = 1 kΩ, RL = 10 kΩ,
Control tr = tf = 20 ns

— 10 — 75 — mV

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD for control inputs and V

EE

≤

(Vin or V

out

) ≤ VDD for Switch I/O.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs must
be left open.