Motorola MC145483SD, MC145483DW Datasheet
SEMICONDUCTOR TECHNICAL DATA
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by MC145483/D
20
1
DW SUFFIX
SOG PACKAGE
CASE 751D
The MC145483 is a 13–bit linear PCM Codec–Filter with 2s complement data
format, and is offered in 20–pin SOG and SSOP packages. This device
performs the voice digitization and reconstruction as well as the band limiting
and smoothing required for the voice coding in digital communication systems.
This device is designed to operate in both synchronous and asynchronous
applications and contains an on–chip precision reference voltage.
20
1
SD SUFFIX
SSOP
CASE 940C
This device has an input operational amplifier whose output is the input to the
encoder section. The encoder section immediately low–pass filters the analog
signal with an active R–C filter to eliminate very high frequency noise from being
modulated down to the passband by the switched capacitor filter. From the
ORDERING INFORMATION
MC145483DW SOG Package
MC145483SD SSOP
active R–C filter, the analog signal is converted to a dif ferential signal. From this
point, all analog signal processing is done differentially. This allows processing
of an analog signal that is twice the amplitude allowed by a single–ended
design, which reduces the significance of noise to both the inverted and
non–inverted signal paths. Another advantage of this differential design is that
noise injected via the power supplies is a common–mode signal that is
cancelled when the inverted and non–inverted signals are recombined. This
dramatically improves the power supply rejection ratio.
After the differential converter, a differential switched capacitor filter band–
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized
by the differential 13–bit linear A/D converter. The digital output is 2s
complement format.
The decoder digital input accepts 2s complement data and reconstructs it
using a differential 13–bit linear D/A converter. The output of the D/A is
low–pass filtered at 3400 Hz and sinX/X compensated by a differential switched
capacitor filter. The signal is then filtered by an active R–C filter to eliminate the
out–of–band energy of the switched capacitor filter.
The MC145483 PCM Codec–Filter has a high impedance VAG reference pin
PIN ASSIGNMENT
RO–
PI
PO–
PO+ 5
V
DD
FSR
DR
PDI
1
2
3
4
6
7
8
9
10
VAG Ref
BCLKR
20
19
18
17
16
15
14
13
12
11
which allows for decoupling of the internal circuitry that generates the
mid–supply VAG reference voltage to the VSS power supply ground. This
reduces clock noise on the analog circuitry when external analog signals are
referenced to the power supply ground.
The MC145483 13–bit linear PCM Codec–Filter accepts both Short Frame
Sync and Long Frame Sync clock formats, and utilizes CMOS due to its reliable
low–power performance and proven capability for complex analog/digital VLSI
functions.
• Single 3 V Power Supply
• 13–Bit Linear ADC/DAC Conversions with 2s Complement Data Format
• Typical Power Dissipation of 8 mW, Power–Down of 0.01 mW
• Fully–Differential Analog Circuit Design for Lowest Noise
• Transmit Band–Pass and Receive Low–Pass Filters On–Chip
• Transmit High–Pass Filter May be Bypassed by Pin Selection
• Active R–C Pre–Filtering and Post–Filtering
• On–Chip Precision Reference Voltage of 0.886 V for a – 5 dBm TLP
@ 600 Ω
• 3–Terminal Input Op Amp Can be Used, or a 2–Channel Input Multiplexer
• Receive Gain Control from 0 dB to – 21 dB in 3 dB Steps in Synchronous
Operation
• Push–Pull 300 Ω Power Drivers with External Gain Adjust
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2
3/97 TN97033100
V
AG
TI+
TI–
TG
HB
V
SS
FST
DT
BCLKT
MCLK
Motorola, Inc. 1997
MC145483MOTOROLA
1
RO–
RECEIVE
SHIFT
FREQ
PI
DAC
REGISTER
DR
– 1
–
+
V
DD
R*
1
R*
V
SS
FREQ
PO–
PO+
V
DD
V
SS
VAG Ref
V
AG
TG
TI–
TI+
HB
–
+
Figure 1. MC145483 13–Bit Linear PCM Codec–Filter Block Diagram
DEVICE DESCRIPTION
A PCM Codec–Filter is used for digitizing and reconstructing the human voice. These devices are used primarily for
the telephone network to facilitate voice switching and transmission. Once the voice is digitized, it may be switched by
digital switching methods or transmitted long distance (T1,
microwave, satellites, etc.) without degradation. The name
codec is an acronym from ‘‘COder’’ for the analog–to–digital
converter (ADC) used to digitize voice, and ‘‘DECoder’’ for
the digital–to–analog converter (DAC) used for reconstructing voice. A codec is a single device that does both the ADC
and DAC conversions.
To digitize intelligible voice requires a signal–to–distortion
ratio of about 30 dB over a dynamic range of about 40 dB.
This may be accomplished with a linear 13–bit ADC and
DAC. The MC145483 satisfies these requirements and may
be used as the analog front–end for voice coders using DSP
technology to further compress the digital data stream.
In a sampling environment, Nyquist theory says that to
properly sample a continuous signal, it must be sampled at a
frequency higher than twice the signal’s highest frequency
component. Voice contains spectral energy above 3 kHz, but
FSR
SHARED
DAC
SEQUENCE
AND
CONTROL
0.886 V
REF
ADC
TRANSMIT
SHIFT
REGISTER
BCLKR
PDI
MCLK
BCLKT
FST
DT
its absence is not detrimental to intelligibility. To reduce the
digital data rate, which is proportional to the sampling rate, a
sample rate of 8 kHz was adopted, consistent with a bandwidth of 3 kHz. This sampling requires a low–pass filter to
limit the high frequency energy above 3 kHz from distorting
the in–band signal. The telephone line is also subject to
50/60 Hz power line coupling, which must be attenuated
from the signal by a high–pass filter before the analog–to–
digital converter. The MC145483 includes a high–pass filter
for compatibility with existing telephone applications, but it
may be removed from the analog input signal path by the
high–pass bypass pin.
The digital–to–analog conversion process reconstructs a
staircase version of the desired in–band signal, which has
spectral images of the in–band signal modulated about the
sample frequency and its harmonics. These spectral images
are called aliasing components, which need to be attenuated
to obtain the desired signal. The low–pass filter used to attenuate these aliasing components is typically called a reconstruction or smoothing filter.
The MC145483 PCM Codec–Filter has the codec, both
presampling and reconstruction filters, and a precision voltage reference on–chip.
MC145483 MOTOROLA
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PIN DESCRIPTIONS
POWER SUPPLY
V
DD
Positive Power Supply (Pin 6)
This is the most positive power supply and is typically con-
nected to + 3 V. This pin should be decoupled to VSS with a
0.1 µF ceramic capacitor.
V
SS
Negative Power Supply (Pin 15)
This is the most negative power supply and is typically
connected to 0 V.
V
AG
Analog Ground Output (Pin 20)
This output pin provides a mid–supply analog ground. This
pin should be decoupled to VSS with a 0.01 µF ceramic capacitor. All analog signal processing within this device is referenced to this pin. If the audio signals to be processed are
referenced to VSS, then special precautions must be utilized
to avoid noise between VSS and the VAG pin. Refer to the applications information in this document for more information.
The VAG pin becomes high impedance when this device is in
the powered–down mode.
VAG Ref
Analog Ground Reference Bypass (Pin 1)
This pin is used to capacitively bypass the on–chip circuitry that generates the mid–supply voltage for the VAG output
pin. This pin should be bypassed to VSS with a 0.1 µF ceramic capacitor using short, low inductance traces. The VAG Ref
pin is only used for generating the reference voltage for the
VAG pin. Nothing is to be connected to this pin in addition to
the bypass capacitor. All analog signal processing within this
device is referenced to the VAG pin. If the audio signals to be
processed are referenced to VSS, then special precautions
must be utilized to avoid noise between VSS and the VAG pin.
Refer to the applications information in this document for
more information. When this device is in the powered–down
mode, the VAG Ref pin is pulled to the VDD power supply with
a non–linear, high–impedance circuit.
CONTROL
HB
Transmit High–Pass Filter Bypass (Pin 16)
This pin selects whether the transmit high–pass filter will
be used or bypassed, which allows frequencies below
200 Hz to appear at the input of the ADC to be digitized. This
high–pass filter is a third order filter for attenuating power line
frequencies, typically 50/60 Hz. A logic low selects this filter.
A logic high deselects or bypasses this filter. When the filter
is bypassed, the transmit frequency response extends down
to dc.
when a logic 1 is applied to this pin. The device goes through
a power–up sequence when this pin is taken to a logic 1
state, which prevents the DT PCM output from going low impedance for at least two FST cycles. The VAG and VAG Ref
circuits and the signal processing filters must settle out before the DT PCM output or the RO– receive analog output
will represent a valid analog signal.
ANALOG INTERFACE
TI+
Transmit Analog Input (Non–Inverting) (Pin 19)
This is the non–inverting input of the transmit input gain
setting operational amplifier . This pin accommodates a differential to single–ended circuit for the input gain setting op
amp. This allows input signals that are referenced to the V
pin to be level shifted to the VAG pin with minimum noise.
This pin may be connected to the VAG pin for an inverting
amplifier configuration if the input signal is already referenced to the VAG pin. The common mode range of the TI+
and TI– pins is from 1.2 V , to VDD minus 1.2 V . This is an FET
gate input.
The TI+ pin also serves as a digital input control for the
transmit input multiplexer . Connecting the TI+ pin to VDD will
place this amplifier’s output (TG) into a high–impedance
state, and selects the TG pin to serve as a high–impedance
input to the transmit filter. Connecting the TI+ pin to VSS will
also place this amplifier’s output (TG) into a high–impedance
state, and selects the TI– pin to serve as a high–impedance
input to the transmit filter.
TI–
Transmit Analog Input (Inverting) (Pin 18)
This is the inverting input of the transmit gain setting operational amplifier. Gain setting resistors are usually connected from this pin to TG and from this pin to the analog
signal source. The common mode range of the TI+ and TI–
pins is from 1.2 V to VDD – 1.2 V. This is an FET gate input.
The TI– pin also serves as one of the transmit input mulitplexer pins when the TI+ pin is connected to VSS. When TI+
is connected to VDD, this pin is ignored. See the pin descriptions for the TI+ and the TG pins for more information.
TG
Transmit Gain (Pin 17)
This is the output of the transmit gain setting operational
amplifier and the input to the transmit band–pass filter. This
op amp is capable of driving a 2 kΩ load. Connecting the TI+
pin to VDD will place the TG pin into a high–impedance state,
and selects the TG pin to serve as a high–impedance input to
the transmit filter. All signals at this pin are referenced to the
VAG pin. When TI+ is connected to VSS, this pin is ignored.
See the pin descriptions for TI+ and TI– pins for more information. This pin is high impedance when the device is in
the powered–down mode.
SS
PDI
Power–Down Input (Pin 10)
This pin puts the device into a low power dissipation mode
when a logic 0 is applied. When this device is powered down,
all of the clocks are gated off and all bias currents are turned
off, which causes RO–, PO–, PO+, TG, VAG, and DT to become high impedance. The device will operate normally
RO–
Receive Analog Output (Inverting) (Pin 2)
This is the inverting output of the receive smoothing filter
from the digital–to–analog converter. This output is capable
of driving a 2 kΩ load to 0.886 V peak referenced to the V
pin. If the device is operated half–channel with the FST pin
clocking and FSR pin held low, the receive filter input will be
AG
MC145483MOTOROLA
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connected to the VAG voltage. This minimizes transients at
the RO– pin when full–channel operation is resumed by
clocking the FSR pin. This pin is high impedance when the
device is in the powered–down mode.
PI
Power Amplifier Input (Pin 3)
This is the inverting input to the PO– amplifier. The non–
inverting input to the PO– amplifier is internally tied to the
VAG pin. The PI and PO – pins are used with external resistors in an inverting op amp gain circuit to set the gain of the
PO+ and PO– push–pull power amplifier outputs. Connecting PI to VDD will power down the power driver amplifiers and
the PO+ and PO– outputs will be high impedance.
PO–
Power Amplifier Output (Inverting) (Pin 4)
This is the inverting power amplifier output, which is used
to provide a feedback signal to the PI pin to set the gain of
the push–pull power amplifier outputs. This pin is capable of
driving a 300 Ω load to PO+. The PO+ and PO– outputs are
differential (push–pull) and capable of driving a 300 Ω load to
1.772 V peak, which is 3.544 V peak–to–peak. The bias voltage and signal reference of this output is the VAG pin. The
VAG pin cannot source or sink as much current as this pin,
and therefore low impedance loads must be between PO+
and PO–. The PO+ and PO– differential drivers are also capable of driving a 100 Ω resistive load or a 100 nF Piezoelectric transducer in series with a 20 Ω resister with a smalll
increase in distortion. These drivers may be used to drive resistive loads of ≥ 32 Ω when the gain of PO– is set to 1/4 or
less. Connecting PI to VDD will power down the power driver
amplifiers, and the PO+ and PO– outputs will be high impedance. This pin is also high impedance when the device is
powered down by the PDI
PO+
Power Amplifier Output (Non–Inverting) (Pin 5)
This is the non–inverting power amplifier output, which is
an inverted version of the signal at PO–. This pin is capable
of driving a 300 Ω load to PO–. Connecting PI to VDD will
power down the power driver amplifiers and the PO+ and
PO– outputs will be high impedance. This pin is also high impedance when the device is powered down by the PDI
See PI and PO– for more information.
DIGITAL INTERFACE
MCLK
Master Clock (Pin 11)
This is the master clock input pin. The clock signal applied
to this pin is used to generate the internal 256 kHz clock and
sequencing signals for the switched–capacitor filters, ADC,
and DAC. The internal prescaler logic compares the clock on
this pin to the clock at FST (8 kHz) and will automatically
accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For
MCLK frequencies of 256 and 512 kHz, MCLK must be syn-
pin.
pin.
chronous and approximately rising edge aligned to FST. For
optimum performance at frequencies of 1.536 MHz and
higher, MCLK should be synchronous and approximately rising edge aligned to the rising edge of FST. In many applications, MCLK may be tied to the BCLKT pin.
FST
Frame Sync, Transmit (Pin 14)
This pin accepts an 8 kHz clock that synchronizes the output of the serial PCM data at the DT pin. This input is compatible with both Long Frame Sync and Short Frame Sync. If
both FST and FSR are held low for several 8 kHz frames, the
device will power down. FST must be clocking for the device
to power up affter being powered down by the frame syncs.
BCLKT
Bit Clock, Transmit (Pin 12)
This pin controls the transfer rate of transmit PCM data. In
the synchronous modes of sign–bit extended and receive
gain adjust, the BCLKT also controls the transfer rate of the
receive PCM data. This pin can accept any bit clock frequency from 256 to 4096 kHz for Long Frame Sync and Short
Frame Sync timing.
DT
Data, Transmit (Pin 13)
This pin is controlled by FST and BCLKT and is high impedance except when outputting PCM data. This pin is high
impedance when the device is in the powered–down mode.
FSR
Frame Sync, Receive (Pin 7)
This pin accepts an 8 kHz clock, which synchronizes the
input of the serial PCM data at the DR pin. FSR can be
asynchronous to FST in the Long Frame Sync or Short
Frame Sync modes.
BCLKR
Bit Clock, Receive (Pin 9)
This pin accepts any bit clock frequency from 256 to 4096
kHz. The BCLKR pin is also used as a mode select pin when
not being clocked for several 8 kHz frames. The BCKLT pin
is used to clock the receive PCM data transfers when the
BCLKR pin is not being clocked. When the BCLKR pinis a
logic 0, the sign–bit extended synchronous mode is selected,
which uses 16–bit transfers with the first four bits being the
sign bit. When the BCLKR pin is a logic 1, the receive gain
adjust synchronous mode is selected, which uses a 13–bit
transfer for the transmit PCM data, but uses a 16–bit transfer
for the receive side, with the 13–bit voice data being first, followed by three bits which control the attenuation of the receive analog output.
DR
Data, Receive (Pin 8)
This pin is the PCM data input. See the pin descriptions for
FSR, BCLKR, and BCKLT for more information.
MC145483 MOTOROLA
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FUNCTIONAL DESCRIPTION
ANALOG INTERFACE AND SIGNAL PATH
The transmit portion of this device includes a low–noise,
three–terminal op amp capable of driving a 2 kΩ load. This
op amp has inputs of TI+ (Pin 19) and TI– (Pin 18) and its
output is TG (Pin 17). This op amp is intended to be configured in an inverting gain circuit. The analog signal may be
applied directly to the TG pin if this transmit op amp is independently powered down by connecting the TI+ input to the
VDD power supply. The TG pin becomes high impedance
when the transmit op amp is powered down. The TG pin is
internally connected to a 3–pole anti–aliasing pre–filter. This
pre–filter incorporates a 2–pole Butterworth active low–pass
filter, followed by a single passive pole. This pre–filter is followed by a single–ended to differential converter that is
clocked at 512 kHz. All subsequent analog processing utilizes fully–differential circuitry. The next section is a fully–differential, 5–pole switched–capacitor low–pass filter with a
3.4 kHz frequency cutoff. After this filter is a 3–pole
switched–capacitor high–pass filter having a cutoff frequency of about 200 Hz. This high–pass stage has a transmission zero at dc that eliminates any dc coming from the
analog input or from accumulated op amp offsets in the preceding filter stages. The high–pass filter may be bypassed or
removed from the signal path by the HB pin. When the high–
pass filter is bypassed, the frequency response extends
down to include dc. The last stage of the high–pass filter is
an autozeroed sample and hold amplifier.
One bandgap voltage reference generator and digital–to–
analog converter (DAC) are shared by the transmit and receive sections. The autozeroed, switched–capacitor
bandgap reference generates precise positive and negative
reference voltages that are virtually independent of temperature and power supply voltage. A capacitor array (CDAC) is
combined with a resistor string (RDAC) to implement the
13–bit linear DAC structure. The encode process uses the
DAC, the voltage reference, and a frame–by–frame autozeroed comparator to implement a successive approximation conversion algorithm. All of the analog circuitry involved
in the data conversion (the voltage reference, RDAC, CDAC,
and comparator) are implemented with a differential architecture.
The receive section includes the DAC described above, a
sample and hold amplifier, a 5–pole, 3400 Hz switched capacitor low–pass filter with sinX/X correction, and a 2–pole
active smoothing filter to reduce the spectral components of
the switched capacitor filter. The output of the smoothing filter is buffered by an amplifier , which is output at the RO– pin.
This output is capable of driving a 2 kΩ load to the VAG pin.
The MC145483 also has a pair of power amplifiers that are
connected in a push–pull configuration. The PI pin is the inverting input to the PO– power amplifier. The non–inverting
input is internally tied to the VAG pin. This allows this amplifier
to be used in an inverting gain circuit with two external resistors. The PO+ a mplifier has a gain of minus one, and is internally connected to the PO– output. This complete power
amplifier circuit is a differential (push–pull) amplifier with adjustable gain. The power amplifier may be powered down independently of the rest of the chip by connecting the PI pin to
VDD.
The calibration level for both ADC and DAC of this 13–bit
linear PCM Codec–Filter is referenced to Mu–Law with the
same bit voltage weighting about the zero crossing. This results in the 0 dBm0 calibration level being 3.20 dB below the
peak sinusoidal level before clipping. Based on the reference
voltage of 0.886 V, the calibration level is 0.436 Vrms or
– 5 dBm at 600 Ω.
The MC145483 has the ability to attenuate the receive
analog output when used in the receive gain adjust mode.
This mode is accessed by applying a logic high to the
BCLKR pin while the rest of the clock pins are clocked normally. This allows three additional bits that will be used to
control the gain of the analog output to be clocked into the
DR pin following the 13 bits of voice data. Table 1 shows the
attenuation values and the corresponding digital codes.
T able 1. Receive Gain Adjust Mode
Coefficients and Attenuation Weightings
Coefficient Attenuation in dB
000 0
001 – 3
010 – 6
011 – 9
100 – 12
101 – 15
110 – 18
111 – 21
POWER–DOWN
There are two methods of putting this device into a low
power consumption mode, which makes the device nonfunctional and consumes virtually no power. PDI
is the power–
down input pin which, when taken low, powers down the
device. Another way to power the device down is to hold both
the FST and FSR pins low while the BCLKT and MCLK pins
are clocked. When the chip is powered down, the VAG, TG,
RO–, PO+, PO–, and DT outputs are high impedance and
the VAG Ref pin is pulled to the VDD power supply with a non–
linear, high–impedance circuit. To return the chip to the power–up state, PDI
must be high and the FST frame sync pulse
must be present while the BCLKT and MCLK pins are
clocked. The DT output will remain in a high–impedance
state for at least two 8 kHz FST pulses after power–up.
MASTER CLOCK
Since this codec–filter design has a single DAC architecture, the MCLK pin is used as the master clock for all analog
signal processing including analog–to–digital conversion,
digital–to–analog conversion, and for transmit and receive filtering functions of this device. The clock frequency applied to
the MCLK pin may be 256 kHz, 512 kHz, 1.536 MHz,
1.544 MHz, 2.048 MHz, 2.56 MHz, or 4.096 MHz. This device has a prescaler that automatically determines the proper
divide ratio to use for the MCLK input, which achieves the required 256 kHz internal sequencing clock. The clocking requirements of the MCLK input are independent of the PCM
data transfer mode (i.e., Long Frame Sync, Short Frame
Sync, whether the device is used in the synchronous modes
or not).
MC145483MOTOROLA
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DIGITAL I/O
The MC145483 is a 13–bit linear device using 2s complement data format. Table 2 shows the 13–bit data word format
for the maximum positive code and negative zero and full–
scale.
Table 3 shows the series of eight 13–bit PCM words that
correspond to a digital milliwatt. The digital milliwatt is the
1 kHz calibration signal reconstructed by the DAC that defines the absolute gain or 0 dBm0 transmission level point
(TLP) of the DAC. The calibration level for this 13–bit linear
ADC and DAC is referenced to Mu–Law with the same bit
voltage weighting about the zero crossing. This results in the
0 dBm0 calibration level being 3.20 dB below the peak sinusoidal level before clipping. Refer to Figures 2a–2d for a
summary and comparison of the four PCM data interface
modes of this device.
T able 2. PCM Codes for Zero and Full–Scale
Level Sign Bit Magnitude Bits
+ Full Scale 0 1111 1111 1111
+ One Step 0 0000 0000 0001
Zero 0 0000 0000 0000
– One Step 1 1111 1111 1111
– Full Scale 1 0000 0000 0000
Table 3. PCM Codes for 1 kHz Digital Milliwatt
Level Sign Bit Magnitude Bits
π/8
3π/8
5π/8
7π/8
9π/8
11π/8
13π/8
15π/8
MC145483 MOTOROLA
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