The MC145181 is a dual frequency synthesizer containing very–low
supply voltage circuitry. The device supports two independent loops with a
single input reference and operates down to 1.8 V. Phase noise reduction
circuitry is incorporated into the device.
The MC145181 operates up to 550 MHz on the main loop and up to
60 MHz on the secondary loop. The device has a 32/33 prescaler for the
main loop. Lock detection circuitry for both loops is multiplexed to a single
output.
Two 8–bit DACs are powered through a dedicated pin. The DAC supply
range is 1.8 to 3.6 V; this voltage may differ from the main supply.
An on–chip voltage multiplier supplies power to the phase/frequency
detectors. Thus, in a 2 V application, the detectors are supplied with 4 V
power. In 2.6 to 3.6 V applications, the multiplied voltage is regulated at
approximately 5 V . The current source/sink phase/frequency detector for the
main loop is designed to achieve faster lock times than a conventional
detector. Both high and low current outputs are available along with a timer,
double buffers, and a MOSFET switch to adjust the external low–pass filter
response.
There are several levels of standby which are controllable with a 1–byte
transfer through the serial port. Either of the PLLs and/or the reference
oscillator may be independently placed in the low–power standby state. In
addition, any of the phase/frequency detector outputs may be placed in the
floating state to facilitate modulation of the external VCOs. Either DAC may
be placed in standby via a 4–byte transfer.
The MC145181 facilitates designing the receiver’s first and second local
oscillators for ReFLEX two–way paging applications. Also, the device
accommodates generation of the transmit carrier.
• Operating Frequency
Main Loop: 100 to 550 MHz
Secondary Loop: 10 to 60 MHz
• Operating Supply Voltage: 1.8 to 3.6 V
• Nominal Supply Current, Both Loops Active: 3 mA
• Maximum Standby Current, All Systems Shut Down: 10 µA
• Phase Detector Output Current:
1.8 V Supply — PD
w
2.5 V Supply — PD
• Two Independent 8–Bit DACs with Separate Supply Pin (Up to 3.6 V)
• Lock Detect Output with Adjustable Lock Indication Window
• Independent R Counters Allow Independent Step Sizes for Each Loop
• Main Loop Divider Range: 992 to 262,143
• Secondary Loop Divider Range: 7 to 8,191
• Fractional Reference Counters Divider Range: 20 to 32,767.5
• Auxiliary Reference Divider with Small–Signal Differential
Output — Ratios: 8, 10, 12.5
• Three General–Purpose Outputs
• Direct Interface to Motorola SPI Data Port Up to 10 Mbps
–Hi: 2.8 mA, PD
out
–Hi: 4.4 mA, PD
out
–Lo: 0.7 mA
out
–Lo: 1.1 mA
out
BiCMOS COMPONENT
FOR 2 OR 3 VOLT
SYSTEMS
SEMICONDUCTOR
TECHNICAL DATA
321
(Scale 2:1)
PLASTIC PACKAGE
(LQFP–32, Tape & Reel Only)
VERY–SMALL 5 x 5 mm BODY
DEVELOPMENT SYSTEM
The MC145230EVK, which contains hardware and
software, is strongly recommended for system
development. (The user must provide the VCOs for
evaluating the MC145181.) The software supports
all features and modes of operation of the device. Up
to four boards or devices can be controlled and the
user is alerted to error conditions. The control
program may be used with any board based on the
MC145181, MC145225, or MC145230.
ORDERING INFORMATION
Device
MC145181FTAR2550/60 MHzLQFP–32
CASE 873C
Main/Secondary
Loop
Maximum
Frequency
Package
ReFLEX and BitGrabber are trademarks of Motorola, Inc.
are subject to change without notice.
MOTOROLA RF/IF DEVICE DATA
For More Information On This Product,
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Motorola, Inc. 1999Rev 1This document contains information on a new product. Specifications and information herein
Power Connections:
Pin 2 = DAC V
Pins 11, 24, 26, and 29 = V
Pins 14, 15, 18, and 31 = Gnd
pos
pos
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DAC
8 Bits
DAC
8 Bits
3
DAC1
2
DAC V
pos
4
DAC2
3
2. PIN CONNECTIONS
Freescale Semiconductor, Inc.
MC145181
查询"MC145181"供应商
V
fin′
Gnd
Osc
b
Osc
1
e
DAC V
nc...
I
pos
DAC1
DAC2
Enb
D
in
Clk
LD
2
3
4
5
6
7
8
10
9
Mode
Output
A
This device contains 15,260 active transistors.
V
11
pos
pos
12
f
in
f
out
Pol
13
f
f
/
out
′
Pol
14
Gnd
in
Output
/
pos
15
Gnd
BV
2532313029282726
16
Output
C
24
23
22
21
20
19
18
17
V
pos
PD
C
reg
C
mult
PD
PD
Gnd
Rx
out
out
out
′
–Lo
–Hi
cale Semiconductor,
Frees
3. PARAMETER TABLES
3A. MAXIMUM RATINGS (Voltages Referenced to Gnd, unless otherwise stated)
ParameterSymbolValueUnit
DC Supply VoltagesV
DC Input Voltage — Osce, fin, fini
Din, Clk, Enb
DC Output VoltageV
DC Input Current, per PinI
DC Output Current, per PinI
DC Supply Current, V
Power Dissipation, per PackageP
Storage TemperatureT
Lead Temperature, 1 mm from Case for
10 Seconds
NOTES:1. Maximum Ratings are those values beyond which damage to the device may occur.
, f
/Poli, f
out
pos
Functional operation should be restricted to the limits in the Electrical Characteristics tables
or Pin Descriptions section.
2. ESD (electrostatic discharge) immunity meets Human Body Model (HBM) up to 2000 V.
Additional ESD data available upon request.
, Mode,
/Pol
out
and Gnd PinsI25mA
pos
DAC V
V
out
out
stg
T
,
pos
in
in
D
L
–0.5 to 3.6V
–0.5 to V
–0.5 to V
–65 to 150°C
+ 0.5V
pos
+ 0.5V
pos
±10mA
±20mA
100mW
260°C
This device contains protection circuitry to
guard against damage due to high static voltages or electric fields. However, precautions
must be taken to avoid applications of any
voltage higher than maximum rated voltages
to this high–impedance circuit.
4
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MOTOROLA RF/IF DEVICE DATA
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Freescale Semiconductor, Inc.
MC145181
3B. DC ELECTRICAL CHARACTERISTICS
V
= 1.8 to 3.6 V, Voltages Referenced to Gnd, TA = –40 to 85°C, unless otherwise statedtt
pos
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Parameter
Maximum Low–Level Input Voltage
Minimum High–Level Input Voltage
Minimum Hysteresis Voltage(Clk)V
Maximum Low–Level Output Voltage
Minimum High–Level Output Voltage
Minimum Low–Level Output Current
Minimum High–Level Output Current
Minimum Low–Level Output Current(Output C) V
Maximum Input Leakage Current
Maximum Output Leakage Current
Maximum ON Resistance(Output C) 1.8 V ≤ V
Maximum Standby Supply Current
NOTES:1. For supply voltages restricted to 2.5 to 2.9 V and an ambient temperature range of –10 to 60°C, Output C has a guaranteed ON resistance range of 23
3C. PD
Maximum Source Current Variation Part–to–Part(See Note) V
Maximum Sink–versus–Source Mismatch(See Note) V
Output Voltage Range(See Note) I
Maximum Three–State Leakage CurrentV
NOTE: Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.
(Din, Clk, Enb, Mode, f
(Din, Clk, Enb
(Din, Clk, Enb
(V
to 44 Ω.
2. The total supply current drain for the keep–alive oscillator, voltage multiplier, and regulator is approximately 250 µA.
3. When the Mode pin is tied high, bit C6 must be programmed to a 0 for minimum supply current drain. Otherwise, if C6 = 1, the current drain is approximately
8 µA for a 1.8 V supply and approximately 40 µA for a 3.6 V supply. This restriction on bit C6 does not apply when the Mode pin is tied low.
4. To ensure minimum standby supply current drain, the voltage potential at the C
See discussion in Section 5E under C
–Hi AND PD
out
Nominal Output Current, V
Nominal Output Current, V
Rx = 2.0 kΩ, Voltages Referenced to Gnd, Voltage Multiplier ON, TA = –40 to 85°C
and DAC V
pos
, Mode, f
(LD, Output A, Output B)
(LD, Output A, Output B)
(LD, Output A, Output B)
(LD, Output A, Output B)
, Mode, f
out
Parameter
/Poli, f
out
out
out
(Output B, Output C)
pos
out
/Poli, f
out
/Poli, f
out
Tied Together)
.
mult
–Lo PHASE/FREQUENCY DETECTOR CHARACTERISTICS
= 1.8 V: PD
pos
≥ 2.5 V: PD
pos
f
/Poli and f
out
/Pol)
f
/Poli and f
out
/Pol)
I
= 20 µAV
out
I
= –20 µAV
out
V
= 0.3 VI
out
V
= V
out
pos
= 0.2 VI
out
Vin = V
/Pol)
–Hi = 2.8 mA, PD
out
–Hi = 4.4 mA, PD
out
pos
Configured as Inputs
V
= V
out
State
2.5 V ≤ V
Vin = V
Standby Mode; Oscillator in Standby Mode;
DAC1 and DAC2 Output = Zero; Keep–alive
Oscillator Off (Notes 2, 3, and 4)
pos
pos
pos
pos
ConditionSymbol
/Pol Configured as Inputs
out
/Pol Configured as Inputs
out
– 0.3 VI
or Gnd; f
or Gnd; Output in High–Impedance
< 2.5 V Supply
≤ 3.6 V Supply (Note 1)
or Gnd; Outputs Open; Both PLLs in
out
out
/Poli and f
out
pin must not be allowed to fall below the potential at the V
= 1.8 to 3.6 V , Voltages Referenced to Gnd, Voltage Multiplier ON, TA = –40 to 85°C
pos
Parameter
MOTOROLA RF/IF DEVICE DATA
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Guaranteed
Condition
= 0.3 V0.3mA
out
= V
out
= 0 or V
out
– 0.3 V–0.3mA
Cmult
Cmult
Limit
±50nA
Unit
5
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Freescale Semiconductor, Inc.
MC145181
3E. DAC CHARACTERISTICS
V
= 1.8 to 3.6 V, DAC V
pos
查询"MC145181"供应商
Parameter
Resolution
Maximum Integral Nonlinearity
Maximum Offset Voltage from Gnd
Maximum Offset V oltage from DAC V
Maximum Output Impedance
ББББББББББББ
Maximum Standby Current
Maximum Supply Current per DAC @ DAC V
= 1.8 to 3.6 V; TA = –40 to 85°C
pos
No External Load
pos
pos
No External Load
Over Entire Output Range, Including Zero
БББББББББББ
Output (which is Low–power Standby)
Zero Output, No External Load
pin
Except with Zero Output, No External Load
Condition
Guaranteed
Limit
8
±1
1
2
STBY
(DAC V
130
in Section 3B)
) / 36
pos
ББББББ
(See I
Unit
Bits
LSB
LSB
LSB
kΩ
Á
mA
3F. VOLTAGE MULTIPLIER AND KEEP–ALIVE OSCILLATOR CHARACTERISTICS
Voltages Referenced to Gnd, TA = –40 to 85°C
Guaranteed
nc...
I
Voltage Multiplier Output Voltage
ББББББББББББ
ББББББББББББ
Keep–alive Refresh Frequency
Parameter
5 MHz Refresh Rate, 100 µA Continuous
Sourcing, Measured at C
БББББББББББ
V
= 1.8 V
pos
V
= 3.6 V
БББББББББББ
pos
V
= 1.8 to 3.6 V
pos
Condition
mult
pin
ББББББ
ББББББ
Limit
3.32 to 3.78
4.75 to 5.35
300 to 700
Unit
Á
V
Á
kHz
cale Semiconductor,
Frees
3G. DYNAMIC CHARACTERISTICS OF DIGITAL PINS
V
= 1.8 to 3.6 V, TA = –40 to 85°C, Input tr = tf = 10 ns, CL = 25 pF
pos
Figure
Parameter
Serial Data Clk Frequency
NOTE: Refer to Clk tw Below
Maximum Propagation Delay, Enb to Output A (Selected as General–Purpose Output)2, 7t
Maximum Propagation Delay, Enb to Output B2, 3, 7, 8t
Maximum Propagation Delay, Enb to Output C4, 8t
Maximum Output Transition T ime, Output A; Output B with Active Pullup and Pulldown2, 7t
Minimum Setup and Hold Times, Din versus Clk5tsu, t
Minimum Setup, Hold, and Recovery Times, Enb versus Clk6tsu, th, t
Minimum Pulse Width, Inactive (High) Time, Enb6t
Minimum Pulse Width, Clk1t
Maximum Input Capacitance — Din, CLK, EnbC
*For Hr register access, the minimum limit is 20 Osce cycles.
For Hni register access, the minimum limit is 27 fini
For N register access, the minimum limit is 20 Osce cycles + 99 fin cycles.
When the timer is used for adapt, the minimum limit after the second N register access and before the next register access is the time–out interval + 99 fin cycles.
cycles.
No.
1f
t
t
Symbol
clk
PLH
, t
PLH
, t
PZL
PZH
PZL
TLH
, t
, t
, t
, t
w
w
in
PHL
PHL
PLZ
PHZ
PLZ
THL
h
rec
Guaranteed
Limit
dc to 10MHz
200ns
,
200ns
,
200ns
75ns
30ns
100ns
*cycles
50ns
10pF
Unit
6
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Freescale Semiconductor, Inc.
MC145181
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90%
Clk
50%
10%
Enb
Output B
Output B
Output B
Output B
D
in
Clk
Figure 1. Figure 2.
t
f
t
w
Figure 3.
t
PZL
t
PLZ
t
PZH
t
PHZ
Figure 5. Figure 6.
Valid
50%
t
su
1/f
clk
50%
50%
t
r
10%
90%
t
h
t
w
90%
10%
V
pos
Gnd
V
pos
Gnd
V
pos
Gnd
V
pos
Gnd
Enb
Clk
Enb
Output A
Output B
Enb
Output C
Output C
50%
t
50%
First
Clock
su
10%
50%
t
PLH
90%
t
TLH
Figure 4.
t
PZL
t
PLZ
t
h
Last
Clock
50%
90%
10%
t
PHL
t
THL
V
pos
Gnd
High
Impedance
High
Impedance
t
w
t
rec
V
pos
Gnd
V
Gnd
V
Gnd
pos
pos
Figure 7. Figure 8.
Device
Under
Test
*Includes all probe and fixture capacitance.
MOTOROLA RF/IF DEVICE DATA
Test Point
CL*
Device
Under
Test
*Includes all probe and fixture capacitance.
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Test Point
CL*
Source current and
limit voltage to V
for t
and t
PLZ
Sink current and
limit voltage to Gnd
for t
and t
PHZ
250 µA
PZL
PZH
pos
.
.
7
Freescale Semiconductor, Inc.
3H. DYNAMIC CHARACTERISTICS OF LOOP AND f
V
= 1.8 to 3.6 V, TA = –40 to 85°C
pos
查询"MC145181"供应商
Symbol
v
Input Voltage Range, f
in
vini
f
Osce
f
Xtal
C
f
*Refer to the Crystal Oscillator Considerations section.
nc...
I
Input Voltage Range, fini
Input Frequency Range, Osc
Crystal Frequency, Oscb and Osc
Input Capacitance of Pins Oscb and
in
Osc
e
Output Frequency Range, f
out
f
Operating Frequency Range of the
φ
Phase/Frequency Detectors, PD
PD
out
ParameterCondition
in
e
out
–Lo, PD
i
out
Figure 9. Figure 10.
e
and f
out
MC145181
PINS
out
Figure
No.
100 MHz ≤ fin < 550 MHz9100300mVpp
10 MHz ≤ fin < 60 MHz10100400mVpp
vin = 350 to 600 mVpp,
Device in External Reference Mode
Device in Crystal Mode*980MHz
Output Signal Swing > 300 mVpp per
out
pin (600 mVpp differential)
–Hi,
11980MHz
1216.2MHz
MinMaxUnit
——pF
dc600kHz
cale Semiconductor,
Frees
Sine Wave
Generator
Z
= 50
out
Sine Wave
Generator
100 pF
Ω
V
RF
Meter
RL = 50
50
Ω
in
Ω
Figure 11.
0.1
V
in
No
Connection
µ
F
Osc
Osc
Gnd
f
in
f
in
100 pF
e
Device
Under
Test
b
Device
Under
Gnd
V
pos
Test
V
pos
V
pos
V
pos
Sine Wave
Generator
Z
= 50
out
Ω
RF
Meter
Ω
RL = 50
f
out
Device
Under
Test
f
out
100 pF
V
in
Figure 12.
20 pF
20 pF
f
i
in
Device
Under
Test
Gnd
V
Peak–to–peak
Voltage
Measurement
V
V
pos
V
pos
8
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Freescale Semiconductor, Inc.
MC145181
4. DEVICE OVERVIEW
Refer to the Block Diagram in Section 1.
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4A. SERIAL INTERFACE AND REGISTERS
The serial interface is comprised of a Clock pin (Clk), a
Data In pin (Din), and an Enable pin (Enb
data input pin is shifted into a shift register on the low–to–high
transition of the serial clock. The data format is most
significant bit (MSB) first. Both Clk and Enb
Schmitt–triggered inputs.
The R and N registers contain counter divide ratios for the
main loop, PLL. The Ri and Ni registers contain counter
divide ratios for the secondary loop, PLLi. Additional contol
bits are located in the Ri, N, and C registers. The D register
controls the digital–to–analog converters (DACs). Random
access is allowed to the N, Ri, Hr, Hni, D, and C registers.
Two 16–bit holding registers, Hr and Hni, feed registers R
and Ni, respectively. [The three least significant bits (LSBs)
of the Hni register are not used.] The R and Ni registers
determine the divide ratios of the R and Ni counters,
respectively. Thus, the information presented to the R and N
counters is double–buffered. Using the proper programming
sequence, new divide ratios may be presented to the N, R,
and Ni counters; simultaneously .
Enb
is used to activate the data port and allow transfer of
data. To ensure that data is accepted by the device, the Enb
signal line must initially be a high voltage (not asserted), then
make a transition to a low voltage (asserted) prior to the
occurrence of a serial clock, and must remain asserted until
after the last serial clock of the burst. Serial data may be
transferred in an SPI format (while Enb
Data is transferred to the appropriate register on the rising
edge of Enb
BitGrabber in the table, allows access to certain registers
without requiring address bits. When Enb
Clk is inhibited from shifting the shift register.
The serial input pins may NOT be driven above the supply
voltage applied to the V
4B. REFERENCE INPUT AND COUNTERS CIRCUITS
Reference (Oscillator) Circuit
For the Colpitts reference oscillator, one pin ties to the
base (Oscb, pin 32) and the other ties to the emitter (Osce,
pin 1), of an on–chip NPN transistor. In addition, the
reference circuit may be operated in the external reference
(XRef) mode as selectable via bit C6 when the Mode pin is
high.
The Oscb and Osce pins support an external fundamental
or overtone crystal. The output of the oscillator is routed to
both the reference counter for the main loop (R counter) and
the reference counter for the secondary loop (Ri counter).
In a second mode, determined by bit C6 being 1 and the
Mode pin being high, Osce is an input which accepts an
ac–coupled signal from a TCXO or other source. Oscb must
be floated. If the Mode pin is low, this “XRef mode” is not
allowed.
(see Table 1). “Short shifting”, depicted as
pins.
pos
). Information on the
are
remains asserted).
is inactive (high),
Reference Counter for Main Loop
Main reference counter R divides down the frequency at
Osce and feeds the phase/frequency detector for the main
loop. The detector feeds the two charge pumps with outputs
PD
–Hi and PD
out
determined by bits in the R register.
Reference Counter for Secondary Loop
Secondary reference counter Ri divides down the
frequency at Osce and feeds the phase/frequency detector
for the secondary loop. The detector output is PD
division ratio of the Ri counter is determined by the 16 LSBs
of the Ri register.
The Ri counter has a special mode to provide a frequency
output at pins f
low–jitter ECL–type outputs. With the Mode pin low, software
control allows the Osce frequency to be divided–by–8, –10,
or –12.5 and routed to the f
tapping off of a front–end stage of the Ri counter and feeding
the auxiliary counter which provides the divided–down
frequency. The chip must have the Mode pin low, which
activates the f
i
divisible by 2 or 2.5 when the f
no such restriction when the Mode pin is high. See
Section 6D, RiRegister.
4C. LOOP DIVIDER INPUTS AND COUNTER CIRCUITS
fin Inputs and Counter Circuit
fin and f
feeds the N counter. A small signal can feed these inputs
either differentially or single–ended.
The N counter divides down the external VCO frequency
for the main loop. (The divide ratio of the N counter is also
known as the loop multiplying factor.) The divide ratio of this
counter is determined by the 18 LSBs of the N register. The
output of the N counter feeds the phase/frequency detector
for the main loop.
fini
Input and Counter Circuit
fini
the Ni counter. A small signal can feed this input
single–ended.
The Ni counter divides down the external VCO frequency
for the secondary loop. (The divide ratio of the Ni counter is
also known as the loop multiplying factor.) The divide ratio of
this counter is determined by bits in the Ni register. The
output of the Ni counter feeds the phase/frequency detector
for the secondary loop.
4D. VOLTAGE MULTIPLIER AND KEEP–ALIVE
The voltage multiplier produces approximately two times
the voltage present at the V
1.8 V to about 2.5 V. With a supply range of approximately
2.5 V to 3.6 V, the elevated voltage is regulated/limited to
approximately 5 V . The elevated voltage, present at the C
are high–frequency inputs to the amplifier which
in
is the high–frequency input to the amplifier which feeds
CIRCUITS
–Lo. The division ratio of the R counter is
out
and f
out
pins. The actual Ri divide ratio must be
out
(differential outputs). These are
out
pins. This output is derived by
out
pins are activated. There is
out
pins over a supply range of
pos
out
i
. The
mult
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pin, is applied to both phase detectors. An external capacitor
to Gnd is required on the C
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required for the multiplier are on–chip.
A capacitor to Gnd is also required on the C
voltage on this pin is equal to the voltage on the V
over a supply range of 1.8 V to about 2.5 V. The voltage on
C
is limited to approximately 2.5 V maximum when the
reg
V
pins exceed 2.5 V.
pos
The refresh rate determines the repetition rate that the
capacitors for the voltage multiplier are charged. Refresh is
normally derived off of the signal present at the Osce pin,
through a divider which is part of the voltage multiplier and
regulator circuitry . The refresh rate is controlled via bits in the
Ri register.
When the reference oscillator circuit is placed in standby,
an on–chip keep–alive oscillator assists in maintaining the
elevated voltage on the phase detectors. The keep–alive
refresh rate is per the spec table in Section 3F.
If desired, the keep–alive oscillator can be inhibited from
turning on, by placing the multiplier in the inactive state via R
register bits. This causes the phase/frequency detector
nc...
I
voltage to bleed off while in standby , but has the advantage of
achieving the lowest supply current if all other sections of the
chip are shut down.
pin. The other capacitors
mult
pin. The
reg
MC145181
pins
pos
i
Detector for Secondary Loop
The detector for the secondary loop senses the phase and
frequency difference between the outputs of the Ri and N
counters. Detector output PD
with a three–state push–pull driver.
The output can be forced to the floating state by a bit in the
C register. This facilitates introduction of modulation into the
VCO input.
4F. LOCK DETECTORS
Window counters in each of the lock detector circuits
determine the lock detector phase threshold for PLL and
PLLi. The window counter divide ratio for the main loop’s lock
detector is controlled via a bit in the N register. The window
counter divide ratio for the secondary loop is not controllable
by the user.
The lock detector window determines a minimum phase
difference which must occur before the Lock Detect pin goes
high. Note that the lock detect signals for each loop drive an
AND gate, which then feeds the LD pin. The LD pin indicates
the condition of both loops, or the one active loop if the other
is in standby . If both loops are in standby , LD is low indicating
unlocked.
i
is a voltage–type output
out
i
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4E. PHASE/FREQUENCY DETECTORS
Detector for Main Loop
The detector for the main loop senses the phase and
frequency difference between the outputs of the R and N
counters. The detector feeds both a high–current charge
pump with output PD
with output PD
The charge pumps can be operated in three conventional
manners as controlled by bits in the N register. PD
be enabled with PD
can be enabled with PD
enabled and tied together externally for maximum charge
pump current. Finally, both outputs can be inhibited. In this
last case, they float. The outputs can also be forced to the
floating state by a bit in the C register. This facilitates
introduction of modulation into the VCO input.
The charge pumps can be operated in an adapt mode as
controlled by bits in the N register. The bits essentially
program a timer which determines how long PD
active. After the time–out, PD
becomes active. In addition, a second set of R and N counter
values can be engaged after the time–out. For more
information, see Table 16 and Section 8, Programmer’sGuide.
out
–Hi and a low–current charge pump
out
–Lo.
–Hi inhibited. Conversely, PD
out
–Lo inhibited. Both outputs can be
out
–Hi floats and PD
out
out
out
–Lo can
–Hi
out
–Hi is
–Lo
out
4G. DACs
The two independent 8–bit DACs facilitate crystal
oscillator trimming and PA output power control. They are
also suitable for any general–purpose use.
Each DAC utilizes an R–2R ladder architecture. The
output pins, DAC1 and DAC2, are directly connected to the
ladder; that is, there is no on–chip buffer.
The DAC outputs are determined by the contents of the D
register. When a DAC output is zero scale, it is also in a
low–power mode. The power–on reset (POR) circuit
initializes the DACs in the low–power mode upon power up.
4H. GENERAL–PURPOSE OUTPUTS
There are three outputs which may be used as port
expanders for a microcontroller unit (MCU).
Output A is actually a multi–purpose output with a
push–pull output driver. See Table 2 for details.
Output B is a three–state output. The state of Output B
depends on two bits; one of these bits also controls whether
the main PLL is in standby or not. See Table 5 for details.
Output C is an open–drain output. The state of this output
is controlled by one bit per Table 4. Output C is specified with
a guaranteed ON resistance, and thus, may be used in an
analog fashion.
10
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MOTOROLA RF/IF DEVICE DATA
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MC145181
5. PIN DESCRIPTIONS
5A. DIGITAL PINS
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Enb
, Din, and Clk
Pins 5, 6, and 7 — Serial Data Port Inputs
The Enb
allow the transfer of data to the device. T o transfer data to the
device, the Enb
data is being clocked in. When Enb
(inactive), data is transferred to the appropriate register
depending either on the data stream length or address bits.
The C, Hr, and N registers can be accessed using either a
unique data stream length (BitGrabber) or by using address
bits (Conventional). The D, Hni, and Ri registers can only be
accessed using address bits. See Table 1.
The bit stream begins with the MSB and is shifted in on the
low–to–high transition of Clk. The bit pattern is 1 byte (8 bits)
long to access the C register, 2 bytes (16 bits) to access the
Hr register, or 3 bytes (24 bits) to access the N register. A bit
pattern of 4 bytes (32 bits) is used to access the registers
when using address bits. The device has double buffers for
storage of the Ni and R counter divide ratios. One double
buffer is composed of the Hr register which feeds the R
register. An Hr to R register transfer occurs whenever the N
register is written. The other double buffer is the Hni register
which feeds the Ni register. An Hni to Ni register transfer
occurs whenever the N register is written. Thus, new divide
ratios may be presented to the R, Ni, and N counters
simultaneously.
Transitions on Enb
high. This puts the device out of synchronization with the
microcontroller. Resynchronization occurs whenever Enb
high (inactive) and Clk is low.
NOTE: $0 denotes hexadecimal zero, $1 denotes hexadecimal one, etc.
ÁÁ
Accessed
Register
ÁÁ
C
Hr
N
C
Hr
N
D
R
i
Hn
i
ÁÁ
Address
Nibble
ÁÁ
—
—
—
$0
$1
$2
$3
$5
$4
Number
ÁÁ
of
Clocks
ÁÁ
8
16
24
32
32
32
32
32
32
Data is retained in the registers over a supply range of 1.8
to 3.6 V. The bit–stream formats are shown in Figures 13
through 18.
LD
Pin 8 — Lock Detectors Output
This signal is the logical AND of the lock detect signals
from both PLL and PLLi. For the main PLL, the phase
window that defines “lock” is programmable via bit N22. The
phase window for the secondary PLLi is not programmable.
If either PLL or PLLi is in standby, LD indicates the lock
condition of the active loop only. If both loops are in standby,
the LD output is a static low level.
Each PLL’s lock detector is in the high state when the
respective loop is locked (the inputs to the phase detector
being the same phase and frequency). The lock detect signal
is in the low state when a loop is out of lock. See Figure 19.
Upon power up, the LD pin indicates a
not locked
condition. The LD pin is a push–pull CMOS output. If unused,
LD should be left open.
Output A
Pin 9 — Multiple–Purpose Digital Output
Depending on control bits Ri21 and Ri20, Output A is
selectable by the user as a general–purpose output (either
high or low level), fR (output of main reference counter), fRi
(output of secondary reference counter), or a phase detector
pulse indicator for both loops. When selected as
general–purpose output, bit C7 determines whether the
output is a high or low level per Table 2. When configured as
fR, fRi
, or phase detector pulse, Output A appears as a
normally low signal and pulses high.
Output A is a slew–rate limited CMOS totem–pole output.
When the Mode pin is tied low (approximately Gnd), the
pair of pins named f
and f
. As such, these pins are the divided down reference
out
/Poli and f
out
/Pol become outputs f
out
out
frequency . The division ratio is controlled by bits per Table 6.
In addition, when Mode is low, the Ri counter is preceded by
a fixed–divide prescaler. Also, only a crystal may be used at
pins Oscb and Osce; an external reference, such as a TCXO,
should not be used to drive either pin. The default on the
phase detector polarity is positive. See the summary in
Table 3.
When the Mode pin is tied high (approximately V
pair of pins named f
/Poli and f
out
/Pol become inputs Pol
out
pos
), the
and Pol. As such, these pins control the polarity of the
phase/frequency detectors for PLLi and PLL, respectively . In
addition, when Mode is high, the Ri counter is preceded by a
dual–modulus prescaler. Therefore, the Ri counter is
completely programmable per Figure 16. Also, either a
crystal or TCXO may be used with the device. See the
summary in Table 3.
T able 3. Mode Pin Summary
Attribute
f
/Poli pin
out
ÁÁÁ
f
/Pol pin
out
ÁÁÁ
ÁÁÁ
Oscillator
circuit
Ri counter
ÁÁÁ
Output B
pin
ÁÁÁ
ÁÁÁ
Mode Pin = Low Level
Pin is f
polarity of phase
detectori is positive
Pin is f
polarity of phase
detector is positive
output;
out
БББББ
output;
out
БББББ
БББББ
Supports a crystal only
Programmable in
БББББ
increments of 2 or 2.5
State of pin controlled
by Bit C6
БББББ
БББББ
Mode Pin = High Level
Pin is Poli input and
controls polarity of
БББББ
phase detector
i
Pin is Pol input and
БББББ
controls polarity of
phase detector
БББББ
Supports crystal or
accommodates TCXO
Programmable in
БББББ
increments of 0.5
Pin not used, Bit C6
controls whether
БББББ
crystal or TCXO is
БББББ
accommodated
Output C
Pin 16 — General–Purpose Digital Output
This pin is controllable by bit C5 as either low level or high
impedance per Table 4.
The output driver is an open–drain N–channel MOSFET
connected to Gnd. The ESD (electrostatic discharge)
protection circuit for this pin is tied to Gnd and V
pos
. Thus,
voltages above V
above V
. If unused, Output C should be left open.
pos
are clipped at approximately 0.7 V
pos
Table 4. Output C Programming
Bit C5
0
ÁÁ
1
ÁÁ
State of Output C Pin
Low level
(ON resistance per
БББББББ
Electrical Table)
High impedance
БББББББ
(leakage per Electrical Table)
Output B
Pin 25 — General–Purpose Digital Output
This pin is controllable by bits C6 and C1 as either low
level, high level, or high impedance per Table 5. Note that
whenever the main PLL is placed in standby by bit C1, Output
B is forced to high impedance. The three–state MOSFET
output is slew–rate limited. If unused, Output B should be left
open.
Table 5. Output B Programming
State of
Bit C6
i
*Power–up default.
f
/Poli and f
out
Bit C1
0
0
1
1
0
1
0
1
out
Output B Pin
Low level
High impedance*
High level
High impedance
/Pol
Condition of
Main PLL
Standby*
Standby
Pins 28 and 27 — Dual–purpose Outputs/Inputs
These pins are outputs when the Mode pin is low and
inputs when the Mode pin is high.
When the Mode pin is low, these pins are small–signal
differential outputs f
out
and f
with a frequency derived from
out
the signal present at the Osce pin. The frequency of the
output signal is per Table 6. If this function is not needed, the
Mode pin should be tied high, which minimizes supply
current. In this case, these inputs must be tied high or low per
Tables 7 and 8.
T able 6. f
out
and f
Frequency
out
(Mode Pin = Low)
Bit N23
0
0
0
0
1
1
1
1
Bit Ri1
0
0
1
1
0
0
1
1
Bit Ri0
0
1
0
1
0
1
0
1
Output Frequency
Osce divided by 10
Osce divided by 12.5
Osce divided by 12.5
Osce divided by 12.5
Osce divided by 8
Osce divided by 10
Osce divided by 10
Osce divided by 10
Active
Active
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MOTOROLA RF/IF DEVICE DATA
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Freescale Semiconductor, Inc.
MC145181
When the Mode pin is high, these pins are digital inputs
Poli and Pol which control the polarity of the phase/frequency
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detectors. See Tables 7 and 8. Positive polarity is used when
an increase in an external VCO control voltage input causes
an increase in VCO output frequency. Negative polarity is
used when a decrease in an external VCO control voltage
input causes an increase in VCO output frequency.
T able 7. Main Phase/Frequency Detector Polarity
(Mode Pin = High)
ÁÁ
Mode Pin
High
High
Low
*Pin configured as an output; should not be driven.
ÁÁ
Pol Pin
Low
High
*
Main Detector Polarity
БББББББ
(PD
–Lo and PD
out
Positive
Negative
Positive
out
–Hi)
5C. LOOP PINS
fin and f
in
Pins 12 and 13 — Frequency Input for Main Loop (PLL)
These pins feed the on–chip RF amplifier which drives the
high–speed N counter. This input may be fed differentially.
However, it is usually used in a single–ended configuration
with fin driven while f
is tied to a good RF ground (via a
in
capacitor). The signal source driving this input must be ac
coupled and originates from an external VCO.
The sensitivity of the RF amplifier is dependent on
frequency as shown in the Loop Specifications table.
Sensitivity of the fin input is specified as a level across a 50 Ω
load driven by a 50 Ω source. A VCO that can drive a load
within the data sheet limits can also drive fin. Usually , to avoid
load pull and resultant frequency modulation of the VCO, fin is
lightly coupled by a small value capacitor and/or a resistor.
See the applications circuit of Figure 65.
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cale Semiconductor,
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T able 8. Secondary Phase/Frequency
Detector Polarity
(Mode Pin = High)
ÁÁ
Mode Pin
ÁÁ
High
High
Low
*Pin configured as an output; should not be driven.
ÁÁ
Poli Pin
ÁÁ
Low
High
*
Secondary Detector
БББББ
Polarity
(PD
i
БББББ
out
Positive
Negative
Positive
)
5B. REFERENCE PINS
Osce and Osc
b
Pins 1 and 32 — Reference Oscillator Transistor Emitter
and Base
These pins can be configured to support an external
crystal in a Colpitts oscillator configuration. The required
connections for the crystal circuit are shown in the CrystalOscillator Considerations section.
Additionally, the pins can be configured to accept an
external reference frequency source, such as a TCXO. In this
case, the reference signal is ac coupled into Osce and the
Oscb pin is left floating. See Figure 1 1.
Bit C6 and the Mode input pin control the configuration of
these pins per Table 9.
fini
Pin 30 — Frequency Input for Secondary Loop (PLLi)
This pin feeds the on–chip RF amplifier which drives the
high–speed Ni counter. This input is used in a single–ended
configuration. The signal source driving this input must be ac
coupled and originates from an external VCO.
The sensitivity of the RF amplifier is dependent on
frequency as shown in the Loop Specifications table.
Sensitivity of the fini
input is specified as a level across a
50 Ω load driven by a 50 Ω source. A VCO that can drive a
load within the data sheet limits can also drive fini
. Usually , to
avoid load pull and resultant frequency modulation of the
VCO, fini
is lightly coupled by a small value capacitor and/or
a resistor. See the applications circuit of Figure 65.
If the secondary loop is not used, PLLi should be placed in
standby and fini
PD
–Hi and PD
out
should be left open.
–Lo
out
Pins 19 and 20 — Phase/Frequency Detector Outputs
for Main Loop (PLL)
Each pin is a three–state current source/sink/float output
for use as a loop error signal when combined with an external
low–pass loop filter. Under bit control, PD
one–quarter or one–eighth the output current of PD
–Lo has either
out
out
–Hi per
Table 10. The detector is characterized by a linear transfer
function (no dead zone). The polarity of the detector is
controllable. The operation of the detector is described below
and shown in Figure 20.
T able 9. Reference Configuration
Mode
ÁÁ
Input
Pin
ÁÁ
Low
High
High
ÁÁ
*See Table 5.
ÁÁ
Bit C6
ÁÁ
ÁÁ1БББББ
БББББ
БББББ
X
Supports Crystal
(default)
0
Supports Crystal
Requires External
Reference
MOTOROLA RF/IF DEVICE DATA
Reference
Configuration
Table 10. Current Ratio of PD
БББББ
Comment
БББББ
C6 used to control
Output B*
Output B not useful
Output B not useful
БББББ
When the Mode pin is high, positive polarity occurs when
Bit
Á
N18
0
1
the Pol pin is low. Also, when the Mode pin is low, polarity
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and PD
Output Current Ratio
PD
ББББББ
–Lo
out
–Hi:PD
out
(Gain Ratio)
4 : 1
8 : 1
out
–Lo
out
–Hi
13
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Á
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defaults to positive. Positive polarity is described below. fV is
the output of the main loop’s VCO divider (N counter). fR is
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the output of the main loop’s reference divider (R counter).
(a) Frequency of fV > fR or phase of fV leading fR:
current–sinking pulses from a floating state.
(b) Frequency of fV < fR or phase of fV lagging fR:
current–sourcing pulses from a floating state.
(c) Frequency and phase of fV = fR: essentially a floating
state, voltage at pin determined by loop filter.
When the Mode pin is high, negative polarity occurs when
the Pol pin is high. Negative polarity is described below. fV is
the output of the main loop’s VCO divider (N counter). fR is
the output of the main loop’s reference divider (R counter).
(a) Frequency of fV > fR or phase of fV leading fR:
current–sourcing pulses from a floating state.
(b) Frequency of fV < fR or phase of fV lagging fR:
current–sinking pulses from a floating state.
(c) Frequency and phase of fV = fR: essentially a floating
state, voltage at pin determined by loop filter.
These outputs can be enabled and disabled by bits in the
C and N registers. Placing the main PLL in standby (bit C1
= 1) forces the detector outputs to a floating state. In addition,
setting the PD Float bit (bit C4 = 1) forces the detector
outputs to a floating state while allowing the counters to run
for the main PLL. For selection of the outputs, see Table 11.
The phase detector gain (in amps per radian) = PD
out
current (in amps) divided by 2π.
If a detector output is not used, that pin should be left
open.
T able 11. Selection of Main Detector Outputs
Bit
N21
ÁÁ
0
0
0
0
1
ÁÁ
1
ÁÁ
ÁÁ1Á1Á0ББББББББ
1
ÁÁ
ÁÁ
NOTES:1. When a detector output is not enabled, it is floating.
БББББББББББББББ
Bit
N20
Á
0
0
1
1
0
Á
0
Á
1
Á
Á
2. Setting bit N21 = 1 places the IC in an adapt mode and engages a
timer.
Bit
N19
Á
Á
Á
Á
Á
ББББББББ
0
Both outputs not enabled
1
PD
out
0
PD
out
1
Both PD
enabled
0
PD
out
ББББББББ
only, then PD
1
PD
out
only, then PD
ББББББББ
PD
out
only, then PD
1
PD
out
ББББББББ
cycles only, then PD
enabled
ББББББББ
Result
–Lo enabled
–Hi enabled
–Lo and PD
out
–Hi enabled for 16 fR cycles
–Hi enabled for 32 fR cycles
–Hi enabled for 64 fR cycles
–Hi enabled for 128 f
–Lo enabled
out
–Lo enabled
out
–Lo enabled
out
out
out
–Lo
–Hi
R
PD
i
out
Pin 23 — Phase/Frequency Detector Output for
Secondary Loop (PLLi)
This pin is a three–state voltage output for use as a loop
error signal when combined with an external low–pass loop
filter. The detector is characterized by a linear transfer
function (no dead zone). The polarity of the detector is
controllable. The operation of the detector is described below
and shown in Figure 21.
When the Mode pin is high, positive polarity occurs when
the Poli pin is low. Also, when the Mode pin is low, polarity
defaults to positive. Positive polarity is described below. fVi
is
the output of the secondary loop’s VCO divider (Ni counter).
fRi
is the output of the secondary loop’s reference divider (R
counter.)
(a) Frequency of fVi
> fRi
or phase of fVi
leading fRi
negative pulses from high impedance.
(b) Frequency of fVi
< fRi
or phase of fVi
lagging fRi
positive pulses from high impedance.
(c) Frequency and phase of fVi
= fRi
: essentially a
high–impedance state, voltage at pin determined by
loop filter.
When the Mode pin is high, negative polarity occurs when
the Poli pin is high. Negative polarity is described below. fVi
is the output of the secondary loop’s VCO divider (N
counter). fRi
is the output of the secondary loop’s reference
counter (Ri counter.)
(a) Frequency of fVi
> fRi
or phase of fVi
leading fRi
positive pulses from high impedance.
(b) Frequency of fVi
< fRi
or phase of fVi
lagging fRi
negative pulses from high impedance.
(c) Frequency and phase of fVi
= fRi
: essentially a
high–impedance state, voltage at pin determined by
loop filter.
This output can be enabled and disabled by bits in the C
register. Placing the secondary PLLi in standby (bit C0 = 1)
forces the detector output to a high–impedance state. In
addition, setting the PDi Float bit (bit C3 = 1) forces the
detector output to a high–impedance state while allowing the
counters to run for PLLi.
The phase detector gain (in volts per radian) = C
mult
voltage (in volts) divided by 4π.
If the secondary loop is not used, PLLi should be placed in
standby and PD
i
should be left open.
out
5D. ANALOG OUTPUTS
DAC1 and DAC2
Pins 3 and 4 — Digital–to–Analog Converter Outputs
These are independent outputs of the two 8–bit D/A
converters. The output voltage is determined by bits in the D
register. Each output is a static level with an output
impedance of approximately 100 kΩ.
The DACs may be used for crystal oscillator trimming, PA
(power amplifier) output power control, or other
general–purpose use.
If a DAC output is not used, the pin should be left open.
i
:
:
i
:
:
14
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5E. EXTERNAL COMPONENTS
Freescale Semiconductor, Inc.
MC145181
5F. SUPPLY PINS
Rx
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Pin 17 — Current–Setting Resistor
An external resistor to Gnd at this pin sets a reference
current that is used to determine the current at the
phase/frequency detector outputs PD
A value of 2 kΩ is required.
C
mult
Pin 21 — Voltage–Multiplier Capacitor
An external capacitor to Gnd at this pin is used for the
on–chip voltage multiplier circuit. The value of this capacitor
must be greater than 20 times the value of the largest loop
filter capacitor. For example, if the largest loop filter capacitor
on either the main loop or the secondary loop is 0.01 µF , then
a 0.22 µF capacitor could be used on the C
To ensure minimum standby supply current drain, the
voltage potential at the C
below the potential at the V
keep–alive oscillator is shut off, the user should tie a large
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value resistor (> 10 MΩ) between the C
resistor should be sized to overcome leakage from C
Gnd due to the printed circuit board and the external
capacitor. The consequence of not using the resistor is
higher supply current drain in standby . If standby is not used,
the resistor is not necessary . Also, if the keep–alive oscillator
is used, the resistor can be omitted.
pin must not be allowed to fall
mult
pos
–Hi and PD
out
pin.
mult
pins. Therefore, if the
pin and V
mult
out
pos
. This
mult
–Lo.
to
DAC V
pos
Pin 2 — Positive Supply Potential for DACs
This pin supplies power to both DACs and determines the
full–scale output of the DACs. The full–scale output is
approximately equal to the voltage at DAC V
applied to this pin may be more, less, or equal to the potential
applied to the V
1.8 to 3.6 V with respect to the Gnd pins.
If both DACs are not used, DAC V
same potential as V
V
pos
Pins 11, 24, 26, and 29 — Principal Positive Supply
Potential
These pins supply power to the main portion of the chip.
All V
voltage range for V
pins.
together and bypassed to a ground plane using a
low–inductance capacitor mounted very close to the device.
Lead lengths and printed circuit board traces between the
capacitor and the IC package should be minimized. (The
very–fast switching speed of the device can cause excessive
current spikes on the power leads if they are improperly
bypassed.)
pins must be at the same voltage potential. The
pos
For optimum performance, all V
pins. The voltage range for DAC V
pos
should be tied to the
.
pos
is 1.8 to 3.6 V with respect to the Gnd
pos
pos
pins should be tied
pos
. The voltage
pos
pos
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cale Semiconductor,
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C
reg
Pin 22 — Regulator Capacitor
An external capacitor to Gnd at this pin is required for the
on–chip voltage regulator . A value of 1 µF is recommended.
Gnd
Pins 14, 15, 18, and 31 — Ground
Common ground for the device. All Gnd pins must be at
the same potential and should be tied to a ground plane.
1. To access the C register, either 8 or 32 clock cycles can be used.
2. For the 8–bit stream, no address bits are needed.
3. For the 32–bit stream, address bits A3 through A0 are required.
4. At this point, the new byte is transferred to the C register. No other register is affected.
in
D
MOTOROLA RF/IF DEVICE DATA
NOTES:
5. X signifies a don’t care bit.
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C REGISTER BITS
See Figure 13 for C register access and serial data
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formats.
Out A (C7)
When the Output A pin is selected as a General–Purpose
Output (via bits Ri21 = Ri20 = 0), bit C7 determines the state
of the pin. When C7 is 1, Output A is forced to a high level.
When C0 is 0 Output A is forced low.
When Output A is not selected as a General–Purpose
Output, bit C7 has no function; i.e., C7 is a “don’t care” bit.
Out B/XRef (C6)
Bit C6 is a dual–purpose bit.
When the Mode pin is tied low, C6 and C1 (PLL Stby), can
be used to control Output B. See Table 12. (The reference
circuit defaults to crystal configuration.)
When the Mode pin is tied high, additional control of the
reference circuit is allowed. See Table 13.
Table 12. Out B/XRef Bit with Mode Pin = Low
ÁÁ
ÁÁ
Bit C6
*Power up default.
Table 13. Out B/XRef Bit with Mode Pin = High
Out C (C5)
This bit determines the state of the Output C pin. When C5
is 1, Output C is forced to a high–impedance state. When C5
is 0, Output C is forced low.
PD Float (C4)
This bit controls the phase detector for the main loop,
outputs PD
phase detector operates normally. When the bit is 1, the
outputs are forced to the floating state which opens the loop
and allows modulation to be introduced into the external VCO
input. During this time, the counters are still active. This bit is
inhibited from affecting the phase detector during a PD
or PD
out
If the loop is locked prior to C4 being set to 1, the lock
detect signal from the main loop continues to indicate “lock”
immediately after PD Float is set to 1. If the phase of the loop
drifts outside the lock detect window, then the lock detect
signal indicates “not locked”. If the loop is not locked, and PD
Float is set to 1, then the lock detect signal from the main loop
continues to indicate “not locked”.
Bit C1
0
0*
1
1
*Power up default.
0
1*
0
1
Bit C6
0*
1
–Hi and PD
out
–Lo pulse.
Supports Crystal*
Accommodates External Reference
State of
ÁÁÁÁ
Output B Pin
Low level
High impedance*
High level
High impedance
Reference Configuration
–Lo. When this bit is 0, the main
out
Condition of
ÁÁÁ
Main PLL
Active
Standby*
Active
Standby
MC145181
–Hi
out
PDi Float (C3)
This bit controls the phase/frequency detector for the
secondary loop, output PD
secondary phase detector operates normally . When the bit is
1, the output is forced to the floating state which opens the
loop and allows modulation to be introduced into the external
VCO input. During this time, the counters are still active. This
bit is inhibited from affecting the phase detector during a
PD
i
pulse.
out
If the loop is locked prior to C3 being set to 1, the lock
detect signal from the secondary loop continues to indicate
“lock” immediately after PDi Float is set to 1. If the phase of
the loop drifts outside the lock detect window, then the lock
detect signal indicates “not locked”. If the loop is not locked,
and PDi Float is set to 1, then the lock detect signal from the
secondary loop continues to indicate “not locked”.
Osc Stby (C2)
This bit controls the crystal oscillator and external
reference input circuit. When this bit is 0, the circuit is active.
When the bit is 1, the circuit is shut down and is in the
low–power standby mode. When this circuit is shut down, a
keep–alive oscillator for the voltage doubler is activated,
unless the doubler is shut off via bits in the Ri register. In the
crystal oscillator mode, when C2 transitions from a 1 to a 0
state, a kick–start circuit is engaged for a few milliseconds.
The kick–start circuit ensures self–starting for a
properly–designed crystal oscillator
Whenever C2 is 1, both bits C1 and C0 must be
1, also.
To minimize standby supply current, the voltage multiplier
may be shut down (by bits Ri19, Ri18, and Ri17 being all
zeroes). If this is the case and the voltage multiplier feature is
being used, the user must allow sufficient time for the
phase/frequency detector supply voltage to pump up when
the multiplier is brought out of standby . This “pump up” time is
dependent on the C
approximately 100 µA. During the pump up time, either the
PLL standby bits C1 and C2 must be 1 or the phase/
frequency detector float bits C3 and C4 must be 1.
PLL Stby (C1)
When set to 1, this bit places the main PLL in the standby
mode for reduced power consumption. PD
PD
–Lo are forced to the floating state, the N and R
out
counters are inhibited from counting, the main loop’s input
amp is shut off, the Rx current is inhibited, and the main
phase/frequency detector is shut off. The reference oscillator
circuit is still active and independently controlled by bit C2.
When this bit is programmed to 0, the main PLL is taken
out of standby in two steps. First, the input amplifier is
activated, all counters are enabled, and the Rx current is no
longer inhibited. Any fR and fV signals are inhibited from
toggling the phase/frequency detectors and lock detector at
this time. Second, when the fR pulse occurs, the N counter is
loaded, and the phase/frequency and lock detectors are
initialized via both flip–flops being reset. Immediately after
the load, the N and R counters begin counting down together.
At this point, the fR and fV pulses are enabled to the phase
mult
i
. When this bit is 0, the
out
NOTE
capacitor size. Pump current is
–Hi and
out
MOTOROLA RF/IF DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
17
Freescale Semiconductor, Inc.
and lock detectors, and the phase/frequency detector output
is enabled to issue an error correction pulse on the next f
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and fV pulses. (Patent issued on this method.)
During standby, data is retained in all registers and any
register may be accessed. When setting or clearing the PLL
Stby bit, other bits in the C register may be changed
simultaneously.
PLLi Stby (C0)
When set to 1, this bit places the PLLi section of the chip,
which includes the on–chip fini
mode for reduced power consumption. PD
floating state. The Ri and Ni counters are inhibited from
counting and placed in the low–current mode. The exception
is the Ri counter’s prescaler when the Mode pin is low. The
Ri counter’s prescaler remains active along with the f
f
pins when PLLi is placed in standby (Mode pin = low).
out
When the Mode pin is low, the f
nc...
I
input amp, in the standby
pin, f
out
i
is forced to the
out
pin, and R
out
MC145181
R
and
out
i
counter’s prescaler are shut down only when Osc Stby bit C2
is set to 1.
When C0 is reset to 0, PLLi is taken out of standby in two
steps. All PLLi counters and the input amp are enabled. Any
fRi
and fVi
phase/frequency detector at this time. Second, when the fRi
pulse occurs, the Ni counter is loaded and the phase/
frequency detector is initialized via both flip–flops being
reset. Immediately after the load, the Ni and Ri counters
begin counting down together. At this point, the fRi
pulses are enabled to the phase and lock detectors, and the
phase/frequency detector output is enabled to issue an error
correction pulse on the next fRi
on this method.)
During standby, data is retained in all registers, and any
register may be accessed. When setting or clearing the PLL
Stby bit, other bits in the C register may be changed
simultaneously.
signals are inhibited from toggling the associated
1. To access the N register, either 24 or 32 clock cycles can be used.
2. For the 24–bit stream, no address bits are needed.
3. For the 32–bit stream, address bits A3 through A0 are required.
4. At this point, the three new bytes are transferred to the N register. In addition, an Hr to
NOTES:
MOTOROLA RF/IF DEVICE DATA
5. X signifies a don’t care bit.
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
nc...
I
cale Semiconductor,
Frees
Freescale Semiconductor, Inc.
MC145181
N REGISTER BITS
See Figure 15 for N register access and serial data
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formats.
Control (N23)
When the Mode pin is low, Control bit N23 determines the
divide ratio of the auxiliary divider which feeds the buffers for
the f
out
and f
between Osce and f
pins. See Table 14 for the overall ratio
out
out
/f
.
out
When the Mode pin is high, N23 must be programmed
to 1.
T able 14. Osce to f
Frequency Ratio,
out
Mode = Low
Á
N23
0
0
0
0
1
1
1
1
ÁÁ
Ri1
0
0
1
1
0
0
1
1
Á
Ri0
0
1
0
1
0
1
0
1
Osce to f
ÁÁÁÁ
Frequency Ratio
out
10:1
12.5:1
12.5:1
12.5:1
8:1
10:1
10:1
10:1
LD Window (N22)
Bit N22 determines the lock detect window for the main
loop. Refer to Table 15 and Figure 19.
T able 15. Lock Detect W indow
LD Window
N22
ÁÁ
ÁÁ0ББББББ
ÁÁ1ББББББ
(Approximated)
ББББББ
32 Osce periods
128 Osce periods
Phase Detector Program (N21, N20, N19)
These bits control which phase detector outputs are active
for the main loop. These bits also control the timer interval
when adapt is utilized for the main loop. See Table 16.
T able 16. Main Phase Detector Control
N21
N20
0
0
0
0
ÁÁ1Á
1
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
Á
1
Á
Á
1
ÁÁ
ÁÁ
Á
Á
N19
0
0
1
1
0
0
1
1
Á
Á
Á
Á
Á
Á
Á
0
Both PD
1
PD
–Hi floating, PD
out
0
PD
–Hi enabled, PD
out
1
Both PD
0
PD
–Hi enabled and PD
out
floating for 16 fR cycles, then PD
БББББББББ
floating and PD
1
PD
–Hi enabled and PD
out
БББББББББ
floating for 32 fR cycles, then PD
floating and PD
БББББББББ
0
PD
–Hi enabled and PD
out
БББББББББ
floating for 64 fR cycles, then PD
floating and PD
БББББББББ
1
PD
–Hi enabled and PD
out
floating for 128 fR cycles, then
БББББББББ
PD
–Hi floating and PD
out
enabled
БББББББББ
–Hi and PD
out
–Hi and PD
out
Result
out
–Lo enabled
out
–Lo enabled
out
–Lo enabled
out
–Lo floating
out
–Lo enabled
–Lo floating
out
–Lo enabled
out
–Lo
out
–Lo
out
–Lo
out
–Lo
out
–Lo
out
out
out
out
–Hi
–Hi
–Hi
Current Ratio (N18)
This bit allows for MCU control of the PD
PD
–Lo current (or gain) ratio on the main loop
out
out
–Hi to
phase/frequency detector outputs. See Table 17.
T able 17. PD
ÁÁ
ÁÁ
Current Ratio
N18
ÁÁ
0
1
PD
–Hi to PD
out
ÁÁÁ
–Hi to
out
ÁÁÁ
PD
–Lo
out
ÁÁÁ
4:1
8:1
–Lo Current Ratio
out
PD
–Hi
out
Current
ÁÁÁ
C
mult
ÁÁÁ
Pin = 5 V
(Nominal)
ÁÁÁ
4.4 mA
4.4 mA
PD
–Lo
out
Current
ÁÁÁ
C
mult
ÁÁÁ
Pin = 5 V
(Nominal)
ÁÁÁ
1.1 mA
0.55 mA
N Counter Divide Ratio (N17 to N0)
These bits control the N Counter divide ratio or loop
multiplying factor. The minimum allowed value is 992. The
maximum value is 262,143. For ease of programming, binary
representation is used. For example, if a divide ratio of 1000
is needed, the 1000 in decimal is converted to binary
00 0000 0011 1110 1000 and is loaded into the device for
N17 to N0. See Figure 15.