Motorola MC14515BCP, MC14515BCL, MC14514BCP, MC14514BDW, MC14515BDW Datasheet
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MOTOROLA CMOS LOGIC DATA
385
MC14514B MC14515B
The MC14514B and MC14515B are two output options of a 4 to 16 line
decoder with latched inputs. The MC14514B (output active high option)
presents a logical “1” at the selected output, whereas the MC14515B (output
active low option) presents a logical “0” at the selected output. The latches
are R–S type flip–flops which hold the last input data presented prior to the
strobe transition from “1” to “0”. These high and low options of a 4–bit latch/4
to 1 6 line decoder a re constructed with N–channel and P –channel
enhancement mode devices in a single monolithic structure. The latches are
R–S type flip–flops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
These complementary circuits find primary use in decoding applications
where low power dissipation and/or high noise immunity is desired.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 18.0 V
Vin, V
out
Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current (DC or Transient),
per Pin
± 10 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
VDD = PIN 24
VSS = PIN 12
4 TO 16
DECODER
TRANSPARENT
LATCH
STROBE
INHIBIT
2
3
1
21
22
23
DATA 1
DATA 2
DATA 3
DATA 4
A
B
C
D 20
17
18
4
5
6
7
8
10
9
11
19
16
13
14
15
A
B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B
C D
A
B C D
A B C
D
A B C D
A B
C D
A B C D
A B C DS15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Data Inputs
Selected Output
MC14514 = Logic “1”
Inhibit D C B A MC14515 = Logic “0”
0 0 0 0 0 S0
0 0 0 0 1 S1
0 0 0 1 0 S2
0 0 0 1 1 S3
0 0 1 0 0 S4
0 0 1 0 1 S5
0 0 1 1 0 S6
0 0 1 1 1 S7
0 1 0 0 0 S8
0 1 0 0 1 S9
0 1 0 1 0 S10
0 1 0 1 1 S11
0 1 1 0 0 S12
0 1 1 0 1 S13
0 1 1 1 0 S14
0 1 1 1 1 S15
1 X X X X All Outputs = 0, MC14514
All Outputs = 1, MC14515
DECODE TRUTH TABLE (Strobe = 1)*
X = Don’t Care
*Strobe = 0, Data is latched
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 623
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBDW SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
MOTOROLA CMOS LOGIC DATAMC14514B MC14515B
386
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C 25_C 125_C
Characteristic
Symbol
V
DD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage
“0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
—
—
—
—
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current I
in
15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance
(Vin = 0)
C
in
— — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
TL
5.0
10
15
IT = (1.35 µA/kHz) f + I
DD
IT = (2.70 µA/kHz) f + I
DD
IT = (4.05 µA/kHz) f + I
DD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**āThe formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and V
out
should be constrained to the range VSS ≤ (Vin or V
out
) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MOTOROLA CMOS LOGIC DATA
387
MC14514B MC14515B
SWITCHING CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C)
All Types
Characteristic
Symbol
V
DD
Min Typ # Max
Unit
Output Rise Time
t
TLH
= (3.0 ns/pF) CL + 30 ns
t
TLH
= (1.5 ns/pF) CL + 15 ns
t
TLH
= (1.1 ns/pF) CL + 10 ns
t
TLH
5.0
10
15
—
—
—
180
90
65
360
180
130
ns
Output Fall Time
t
THL
= (1.5 ns/pF) CL + 25 ns
t
THL
= (0.75 ns/pF) CL + 12.5 ns
t
THL
= (0.55 ns/pF) CL + 9.5 ns
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time; Data, Strobe to S
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 465 ns
t
PLH
, t
PHL
= (0.86 ns/pF) CL + 192 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 125 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
550
225
150
1100
450
300
ns
Inhibit Propagation Delay Times
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 315 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 117 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 75 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
400
150
100
800
300
200
ns
Setup Time
Data to Strobe
t
su
5.0
10
15
250
100
75
125
50
38
—
—
—
ns
Hold Time
Strobe to Data
t
h
5.0
10
15
– 20
0
10
– 100
– 40
– 30
—
—
—
ns
Strobe Pulse Width t
WH
5.0
10
15
350
100
75
175
50
38
—
—
—
ns
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Drain Characteristics Test Circuit
EXTERNAL
POWER SUPPLY
V
SS
STROBE
INHIBIT
D1
D2
D3
D4
V
DD
V
DS
I
D
For MC14515B
1. For P–channel: Inhibit = V
DD
2. For N–channel: Inhibit = V
SS
2. and D1–D4 constitute binary
2. code for “output under test.”
For MC14514B
1. For P–channel: Inhibit = V
SS
1. and D1–D4 constitute
1. binary code for “output
1. under test.”
2. For N–channel: Inhibit = V
DD
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
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