MOTOROLA MC14511BDWR2, MC14511BF, MC14511BFEL, MC14511BFR1, MC14511BCP Datasheet
...
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1 Publication Order Number:
MC14511B/D
MC14511B
BCD-To-Seven Segment
Latch/Decoder/Driver
The MC14511B BCD–to–seven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure.
The circuit provides the functions of a 4–bit storage latch, an 8421
BCD–to–seven segment decoder, and an output drive capability. Lamp
test (L T
), blanking (BI), and latch enable (LE) inputs are used to test the
display, to turn–off or pulse modulate the brightness of the display, and
to store a BCD code, respectively. It can be used with seven–segment
light–emitting diodes (LED), incandescent, fluorescent, gas discharge,
or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.
• Low Logic Circuit Power Dissipation
• High–Current Sourcing Outputs (Up to 25 mA)
• Latch Storage of Code
• Blanking Input
• Lamp Test Provision
• Readout Blanking on all Illegal Input Combinations
• Lamp Intensity Modulation Capability
• Time Share (Multiplexing) Facility
• Supply Voltage Range = 3.0 V to 18 V
• Capable of Driving Two Low–power TTL Loads, One Low–power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range
• Chip Complexity: 216 FETs or 54 Equivalent Gates
• Triple Diode Protection on all Inputs
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
(2.)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage Range –0.5 to +18.0 V
V
in
Input Voltage Range, All Inputs –0.5 to VDD + 0.5 V
I DC Current Drain per Input Pin 10 mA
P
D
Power Dissipation,
per Package
(3.)
500 mW
T
A
Operating Temperature Range –55 to +125 °C
T
stg
Storage Temperature Range –65 to +150 °C
I
OHmax
Maximum Output Drive Current
(Source) per Output
25 mA
P
OHmax
Maximum Continuous Output
Power (Source) per Output
(4.)
50 mA
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C
4. P
OHmax
= IOH (VDD – VOH)
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A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14511BCP PDIP–16 2000/Box
MC14511BD SOIC–16 48/Rail
MC14511BDW SOIC–16 47/Rail
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC1451 1BCP
AWLYYWW
MC1451 1BDWR2 SOIC–16 1000/Tape & Reel
SOIC–16
DW SUFFIX
CASE 751G
1
16
14511B
AWLYYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14511B
AWLYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
14511B
AWLYWW
MC1451 1BF SOEIAJ–16 See Note 1.
MC1451 1BFEL SOEIAJ–16 See Note 1.
MC14511B
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2
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. A
destructive high current mode may occur if V
in
and V
out
are not constrained to the range VSS v (Vin or V
out
) v VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if V
DD
is applied, and the outputs are shorted to VSS and are at a
logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V
SS
or VDD).
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
b
a
g
f
V
DD
e
d
c
BI
LT
C
B
V
SS
A
D
LE
0123456789
DISPLAY
a
b
c
d
e
fg
Inputs Outputs
LE BI LT D C B A a b c d e f g Display
XX0XXXX1111111 8
X 0 1 X X X X 0 0 0 0 0 0 0 Blank
01100001111110 0
01100010110000 1
01100111111001 2
01100111111001 3
01101000110011 4
01101011011011 5
01101100011111 6
01101111110000 7
01110001111111 8
01110011110011 9
0 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 0 1 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 1 0 0 0 0 0 0 0 Blank
111XXXX * *
X = Don’t Care
*Depends upon the BCD code previously applied when LE = 0
TRUTH TABLE
MC14511B
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3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C 25_C 125_C
Characteristic Symbol
V
DD
Vdc
Min Max Min Typ
(5.)
Max Min Max
Unit
Output Voltage “0” Level
V
in
= VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
V
in
= 0 or V
DD
V
OH
5.0
10
15
4.1
9.1
14.1
—
—
—
4.1
9.1
14.1
4.57
9.58
14.59
—
—
—
4.1
9.1
14.1
—
—
—
Vdc
Input Voltage # “0” Level
(V
O
= 3.8 or 0.5 Vdc)
(V
O
= 8.8 or 1.0 Vdc)
(V
O
= 13.8 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(V
O
= 0.5 or 3.8 Vdc)
(V
O
= 1.0 or 8.8 Vdc)
(V
O
= 1.5 or 13.8 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Voltage
(I
OH
= 0 mA) Source
(I
OH
= 5.0 mA)
(I
OH
= 10 mA)
(I
OH
= 15 mA)
(I
OH
= 20 mA)
(I
OH
= 25 mA)
V
OH
5.0 4.1
—
3.9
—
3.4
—
—
—
—
—
—
—
4.1
—
3.9
—
3.4
—
4.57
4.24
4.12
3.94
3.70
3.54
—
—
—
—
—
—
4.1
—
3.5
—
3.0
—
—
—
—
—
—
—
Vdc
(IOH = 0 mA)
(I
OH
= 5.0 mA)
(I
OH
= 10 mA)
(I
OH
= 15 mA)
(I
OH
= 20 mA)
(I
OH
= 25 mA)
10 9.1
—
9.0
—
8.6
—
—
—
—
—
—
—
9.1
—
9.0
—
8.6
—
9.58
9.26
9.17
9.04
8.90
8.70
—
—
—
—
—
—
9.1
—
8.6
—
8.2
—
—
—
—
—
—
—
Vdc
(IOH = 0 mA)
(I
OH
= 5.0 mA)
(I
OH
= 10 mA)
(I
OH
= 15 mA)
(I
OH
= 20 mA)
(I
OH
= 25 mA)
15 14.1
—
14
—
13.6
—
—
—
—
—
—
—
14.1
—
14
—
13.6
—
14.59
14.27
14.18
14.07
13.95
13.70
—
—
—
—
—
—
14.1
—
13.6
—
13.2
—
—
—
—
—
—
—
Vdc
Output Drive Current
(V
OL
= 0.4 V) Sink
(V
OL
= 0.5 V)
(V
OL
= 1.5 V)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current I
in
15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance C
in
— — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package) V
in
= 0 or VDD,
I
out
= 0 µA
I
DD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current
(6.) (7.)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (1.9 µA/kHz) f + I
DD
IT = (3.8 µA/kHz) f + I
DD
IT = (5.7 µA/kHz) f + I
DD
µAdc
5. Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level =
1.0 Vdc min @ V
DD
= 5.0 Vdc
2.0 Vdc min @ V
DD
= 10 Vdc
2.5 Vdc min @ V
DD
= 15 Vdc
6. The formulas given are for the typical characteristics only at 25_C.
7. To calculate total supply current at loads other than 50 pF:
I
T(CL
) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: I
T
is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
MC14511B
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4
SWITCHING CHARACTERISTICS
(8.)
(C
L
= 50 pF, T
A
= 25_C)
Characteristic
Symbol
V
DD
Vdc
Min Typ Max Unit
Output Rise Time
t
TLH
= (0.40 ns/pF) CL + 20 ns
t
TLH
= (0.25 ns/pF) CL + 17.5 ns
t
TLH
= (0.20 ns/pF) CL + 15 ns
t
TLH
5.0
10
15
—
—
—
40
30
25
80
60
50
ns
Output Fall Time
t
THL
= (1.5 ns/pF) CL + 50 ns
t
THL
= (0.75 ns/pF) CL + 37.5 ns
t
THL
= (0.55 ns/pF) CL + 37.5 ns
t
THL
5.0
10
15
—
—
—
125
75
65
250
150
130
ns
Data Propagation Delay Time
t
PLH
= (0.40 ns/pF) CL + 620 ns
t
PLH
= (0.25 ns/pF) CL + 237.5 ns
t
PLH
= (0.20 ns/pF) CL + 165 ns
t
PLH
5.0
10
15
—
—
—
640
250
175
1280
500
350
ns
t
PHL
= (1.3 ns/pF) CL + 655 ns
t
PHL
= (0.60 ns/pF) CL + 260 ns
t
PHL
= (0.35 ns/pF) CL + 182.5 ns
t
PHL
5.0
10
15
—
—
—
720
290
200
1440
580
400
Blank Propagation Delay Time
t
PLH
= (0.30 ns/pF) CL + 585 ns
t
PLH
= (0.25 ns/pF) CL + 187.5 ns
t
PLH
= (0.15 ns/pF) CL + 142.5 ns
t
PLH
5.0
I0
15
—
—
—
600
200
150
750
300
220
ns
t
PHL
= (0.85 ns/pF) CL + 442.5 ns
t
PHL
= (0.45 ns/pF) CL + 177.5 ns
t
PHL
= (0.35 ns/pF) CL + 142.5 ns
t
PHL
5.0
10
15
—
—
—
485
200
160
970
400
320
Lamp Test Propagation Delay Time
t
PLH
= (0.45 ns/pF) CL + 290.5 ns
t
PLH
= (0.25 ns/pF) CL + 112.5 ns
t
PLH
= (0.20 ns/pF) CL + 80 ns
t
PLH
5.0
10
15
—
—
—
313
125
90
625
250
180
ns
t
PHL
= (1.3 ns/pF) CL + 248 ns
t
PHL
= (0.45 ns/pF) CL + 102.5 ns
t
PHL
= (0.35 ns/pF) CL + 72.5 ns
t
PHL
5.0
10
15
—
—
—
313
125
90
625
250
180
Setup Time t
su
5.0
10
15
100
40
30
—
—
—
—
—
—
ns
Hold Time t
h
5.0
10
15
60
40
30
—
—
—
—
—
—
ns
Latch Enable Pulse Width t
WL
5.0
10
15
520
220
130
260
110
65
—
—
—
ns
8. The formulas given are for the typical characteristics only.
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