Motorola MC14510BCL, MC14510BCP, MC14510BD Datasheet

MOTOROLA CMOS LOGIC DATA

351

MC14510B

  

The MC14510B synchronous up/down BCD counter is constructed with MOS P–channel and N–channel enhancement mode devices in a monolithic structure. The counter consists of type D flip–flop stages with a gating structure to provide type T flip–flop capability.

This counter can be preset by applying the desired value in BCD to the Preset inputs (P1, P2, P3, P4) and then bringing the Preset Enable (PE) high. T he direction of counting is controlled by applying a high (for up counting) or a low (for down counting) to the UP/DOWN input. The state of the counter changes on the positive transition of the clock input.

Cascading can be accomplished by connecting the Carry Out

to the

Carry In

of the next stage while clocking e ach counter i n parallel. The outputs (Q1, Q2, Q3, Q4) can be reset to a low state by applying a high to the Reset (R) pin.

This CMOS counter finds primary use in up/down and difference counting. Other applications include: (1) Frequency synthesizer applications where low power dissipation and/or high noise immunity is desired, (2) Analog–to– digital a nd digital–to–analog conversions, and (3) M agnitude and s ign generation.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Internally Synchronous for High Speed

• Logic Edge–Clocked Design — Count Occurs on Positive Going Edge

of Clock

• Asynchronous Preset Enable Operation

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range.

MAXIMUM RATINGS* (Voltages Referenced to V

)

Symbol

Parameter Value Unit

DC Supply Voltage – 0.5 to + 18.0 V

Vin, V

out

Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current (DC or Transient), per Pin

± 10 mA

Power Dissipation, per Package† 500 mW

stg

Storage Temperature – 65 to + 150

Lead Temperature (8–Second Soldering) 260

*Maximum Ratings are those values beyond which damage to the may occur. †Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

TRUTH TABLE

Carry In Up/Down

Preset

Enable

Reset Clock Action

1 X 0 0 X No Count 0 1 0 0 Count Up 0 0 0 0 Count Down X X 1 0 X Preset X X X 1 X Reset

X = Don’t Care NOTE: When counting up, the Carry Out

signal is normally high, and is low only

when Q1 and Q4 are high and Carry In

is low. When counting down, Carry

Out is low only when Q1 through Q4 and Carry In are low.



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3 1/94



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained

to the range VSS v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

or VDD). Unused outputs must be left open.

BLOCK DIAGRAM

1 5

9 10 15

4 12 13

PE CARRY IN R UP/DOWN CLOCK P1 P2 P3 P4

CARRY

OUT

VDD = PIN 16

VSS = PIN 8

MOTOROLA CMOS LOGIC DATAMC14510B

352

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

– 55_C 25_C 125_C

Characteristic

Symbol

Vdc

Min Max Min Typ # Max Min Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

5.0 10 15

— — —

0.05

— — —

0 0 0

0.05

— — —

0.05

Vdc

“1” Level

Vin = 0 or V

5.0 10 15

4.95

9.95

14.95

— — —

4.95

9.95

14.95

5.0 10 15

— — —

4.95

9.95

14.95

— — —

Vdc

Input Voltage

“0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

5.0 10 15

— — —

1.5

3.0

4.0

— — —

2.25

4.50

6.75

1.5

3.0

4.0

— — —

1.5

3.0

4.0

Vdc

“1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

5.0 10 15

3.5

7.0 11

— — —

3.5

7.0 11

2.75

5.50

8.25

— — —

3.5

7.0 11

— — —

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

5.0

5.0 10 15

– 3.0

– 0.64

– 1.6 – 4.2

— — — —

– 2.4

– 0.51

– 1.3 – 3.4

– 4.2 – 0.88 – 2.25

– 8.8

— — — —

– 1.7

– 0.36

– 0.9 – 2.4

— — — —

mAdc

(VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)

5.0 10 15

0.64

1.6

4.2

— — —

0.51

1.3

3.4

0.88

2.25

8.8

— — —

0.36

0.9

2.4

— — —

mAdc

Input Current I

15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance

(Vin = 0)

— — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package)

5.0 10 15

— — —

5.0 10 20

— — —

0.005

0.010

0.015

5.0 10 20

— — —

150 300 600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)

5.0 10 15

IT = (0.58 µA/kHz) f + I

IT = (1.20 µA/kHz) f + I

IT = (1.70 µA/kHz) f + I

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. **āThe formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

PIN ASSIGNMENT

125

U/D

CARRY OUT

CARRY IN

MOTOROLA CMOS LOGIC DATA

353

MC14510B

SWITCHING CHARACTERISTICS* (C

= 50 pF, TA = 25_C, See Figure 2)

All Types

Characteristic

Symbol

Min Typ # Max

Unit

Output Rise and Fall Time

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

TLH

THL

5.0 10 15

— — —

100

50 40

200 100

Propagation Delay Time

Clock to Q

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

PLH

PHL

5.0 10 15

— — —

315 130 100

630 260 200

Clock to Carry Out

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

PLH

PHL

5.0 10 15

— — —

315 130 100

630 260 200

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

Carry In

to Carry Out

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 47 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 35 ns

PLH

PHL

5.0 10 15

— — —

180

80 60

360 160 120

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

Carry In

to Carry Out

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 47 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 35 ns

Preset or Reset to Q

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

PLH

PHL

5.0 10 15

— — —

315 130 100

630 260 200

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

Carry In

to Carry Out

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 47 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 35 ns

Preset or Reset to Q

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

Preset or Reset to Carry Out

PLH

, t

PHL

= (1.7 ns/pF) CL + 465 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 192 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 125 ns

PLH

PHL

5.0 10 15

— — —

550 225 150

1100

450 300

Reset Pulse Width t

w(H)

5.0 10 15

360 210 160

180 105

— — —

Clock Pulse Width t

w(H)

5.0 10 15

350 170 140

200 100

— — —

Clock Pulse Frequency f

5.0 10 15

— — —

3.0

6.0

8.0

1.5

3.0

4.0

MHz

Preset or Reset Removal Time

The Preset or Reset Signal must be low prior to a positive–going transition of the clock.

rem

5.0 10 15

650 230 180

325 115

— — —

Clock Rise and Fall Time t

TLH

THL

5.0 10 15

— — —

5 4

µs

Setup Time

Carry In

to Clock

5.0 10 15

260 120 100

130

60 50

— — —

Hold Time

Clock to Carry In

5.0 10 15

0 10 10

– 50 – 15

– 5

— — —

Setup Time

Up/Down to Clock

5.0 10 15

500 200 175

250 100

— — —

Hold Time

Clock to Up/Down

5.0 10 15

– 70 – 30 – 20

– 140

– 80 – 50

— — —

Setup Time

Pn to PE

5.0 10 15

– 50 – 30 – 25

– 100

– 65 – 55

— — —

Hold Time

PE to Pn

5.0 10 15

480 410 410

240 205 205

— — —

Preset Enable Pulse Width t

5.0 10 15

200 100

100

50 40

— — —

*The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

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